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+---
+author: Florent Gluck - Florent.Gluck@hesge.ch
+
+title: Programmed Input/Output (PIO)
+
+date: \vspace{.5cm} \footnotesize \today
+
+pandoc-latex-fontsize:
+ - classes: [tiny]
+ size: tiny
+ - classes: [verysmall]
+ size: scriptsize
+ - classes: [small]
+ size: footnotesize
+ - classes: [huge, important]
+ size: huge
+---
+
+[//]: # ----------------------------------------------------------------
+## Devices
+
+::: incremental
+
+- To be used, devices must be controlled/programmed
+- Devices are controlled by a special piece of code: a **device driver**
+- Each device is controlled differently: each requires specific controlling code!
+- How to program a device is described in its datasheet/manual
+- Each device is controlled through specific device **registers**
+- How to read/write to these specific device registers?
+
+:::
+
+## Device addressing
+
+- Devices are programmed using dedicated registers
+- Each device has a different set of registers
+ - usually command, data, status, etc.
+ - each register has a specific access type (read, write, both)
+
+- **\textcolor{myred}{Device registers can be accessed in two different ways: MMIO or PMIO}**
+
+- Whether a device is accessed in MMIO or PMIO depends on the system
+ - the **only** way to know is by reading the system's documentation!
+
+[//]: # ----------------------------------------------------------------
+## Memory-Mapped I/O devices (MMIO)
+
+\small
+
+- Device registers are **mapped** into the CPU **physical address space**
+- **RAM and devices registers share the same address space!**
+- Called **MMIO**: Memory-Mapped Input/Output
+- Read/write from/to these devices happen exactly like memory (RAM)
+- All CPU instructions dealing with memory operands can interact with these devices
+ - \footnotesize e.g. `mov` instruction (x86)
+ ```{.verysmall .assembler}
+ mov al,[42] ; reads 32-bits at MMIO address 42
+ ; and stores it into al register
+ ```
+ ```{.verysmall .assembler}
+ mov ebx,42 ; store 42 into ebx register
+ mov byte[ebx],17 ; writes 8-bits value 17
+ ; to MMIO address 42
+ ```
+
+[//]: # ----------------------------------------------------------------
+## Port-Mapped I/O devices (PMIO)
+
+- Device registers are **mapped** into a **specific** memory space, **distinct** from the CPU physical address space
+- Require **specific** CPU instructions to access these devices
+ - e.g. `in` and `out` instructions (x86)
+ ```{.verysmall .assembler}
+ in al,42 ; reads 8-bits at PMIO address 42
+ ; and stores it into al register
+ ```
+ ```{.verysmall .assembler}
+ mov al,17 ; writes 8-bits value 17
+ out 42,al ; to PMIO address 42
+ ```
+
+[//]: # ----------------------------------------------------------------
+## Device address spaces
+
+\centering
+{ width=100% }
+
+\vfill
+
+:::::: {.columns}
+::: {.column width="50%"}
+
+\footnotesize
+
+- MMIO address space, accessed using regular memory instructions (`mov`)
+
+:::
+::: {.column width="50%"}
+
+\footnotesize
+
+- Distinct memory space, **only** accessed using specific machine instructions (`in`, `out`)
+
+:::
+::::::
+
+[//]: # ----------------------------------------------------------------
+## Accessing devices
+
+- Devices using MMIO registers can be programmed in C using regular memory operations, e.g.:
+ \vspace{0.2cm}
+ ```{.c .verysmall}
+ uint32_t *vbe_fb = 0xFC000000;
+ // red (0xFF), green (0x40), blue (0x80)
+ *vbe_fb = 0x00FF4080;
+ ```
+- Devices using PMIO registers cannot be programmed in C directly, they require special assembly instructions
+- PMIO addresses are often called "ports"
+
+[//]: # ----------------------------------------------------------------
+## Assembly code to access PMIO devices
+
+- `outb` instruction writes 1 byte onto the specified port:
+ ```{.assembler .verysmall}
+ ; void outb(uint16_t port, uint8_t data)
+ outb:
+ mov dx,word [esp+4] ; port into dx (2 bytes)
+ mov al,byte [esp+8] ; data into al (1 byte)
+ out dx,al ; write data to port
+ ret
+ ```
+
+- `inb` instruction reads 1 byte from the specified port:
+ ```{.assembler .verysmall}
+ ; uint8_t inb(uint16_t port)
+ inb:
+ mov dx,word [esp+4] ; port into dx (2 bytes)
+ in al,dx ; read port into al (1 byte)
+ ret
+ ```
+
+[//]: # ----------------------------------------------------------------
+## Accessing PMIO devices in C
+
+- Writing to PMIO devices using the previously implemented `outb` and `inb` functions is easy, e.g.
+ \vspace{0.2cm}
+ ```{.c .verysmall}
+ void write_sector(int idx, void *buf) {
+ while((inb(0x1F7) & 0xC0) != 0x40);
+ outb(0x1F2, 1);
+ outb(0x1F3, idx & 0xFF);
+ outb(0x1F4, (idx >> 8) & 0xFF);
+ outb(0x1F5, (idx >> 16) & 0xFF);
+ outb(0x1F6, ((idx >> 24) & 0x0F) | 0xE0);
+ outb(0x1F7, 0x30);
+ while((inb(0x1F7) & 0xC0) != 0x40);
+ uint8_t *data = (uint8_t *)buf;
+ for (int i = 0; i < 512; i++) {
+ outb(0x1F0, *data);
+ data++;
+ }
+ }
+ ```
+
+<!--
+[//]: # ----------------------------------------------------------------
+## PMIO on x86
+
+- On x86, PMIO access is done using `IN` and `OUT` assembly instructions
+- `OUT` instruction to write at a given address
+- `IN` instruction to read from a given address
+- Address **always** specified in `DX` (16-bit adress space) !
+- Read/write always done through `EAX`, `AX` or `AL`:
+ - `EAX` $\rightarrow$ read or write 32 bits
+ - `AX` $\rightarrow$ read or write 16 bits
+ - `AL` $\rightarrow$ read or write 8 bits
+
+[//]: # ----------------------------------------------------------------
+## MMIO and PMIO examples
+
+**MMIO**
+
+:::::: {.columns}
+::: {.column width="50%"}
+
+- Read 8 bits, then 32 bits from address 0x100:
+ ```{.verysmall}
+ mov ebx, 0x100
+ mov al, [ebx]
+ mov eax, [ebx]
+ ```
+
+:::
+::: {.column width="50%"}
+
+- Write 32 bits, then 8 bits to address 0xA000:
+ ```{.verysmall}
+ mov ebx,0x0A000
+ mov dword[ebx],123
+ mov byte[ebx],123
+ ```
+
+:::
+::::::
+
+**PMIO**
+
+:::::: {.columns}
+::: {.column width="50%"}
+
+- Read 16 bits from address (port) 0x60:
+ ```{.verysmall}
+ mov dx,0x60
+ in ax,dx
+ ```
+
+:::
+::: {.column width="50%"}
+
+- Write 8 bits, then 32 bits to address (port) 0x80:
+ ```{.verysmall}
+ mov dx,0x80
+ mov eax,4
+ out dx,al
+ out dx,eax
+ ```
+
+:::
+::::::
+-->
+
+[//]: # ----------------------------------------------------------------
+## Resources
+
+- Programmed input/output\
+\small [\textcolor{myblue}{https://en.wikipedia.org/wiki/Programmed\_input/output}](https://en.wikipedia.org/wiki/Programmed_input/output)
+
+- Memory-mapped I/O\
+\small [\textcolor{myblue}{https://en.wikipedia.org/wiki/Memory-mapped\_I/O}](https://en.wikipedia.org/wiki/Memory-mapped_I/O)
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diff --git a/course/05-Interrupts.md b/course/05-Interrupts.md
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+---
+author: Florent Gluck - Florent.Gluck@hesge.ch
+
+title: Interrupts
+
+date: \vspace{.5cm} \footnotesize \today
+
+pandoc-latex-fontsize:
+ - classes: [tiny]
+ size: tiny
+ - classes: [verysmall]
+ size: scriptsize
+ - classes: [small]
+ size: footnotesize
+ - classes: [huge, important]
+ size: huge
+---
+
+[//]: # ----------------------------------------------------------------
+## Interruptions
+
+- We distinguish 3 kinds of **interrupts** :
+ - \textbf{\textcolor{myorange}{processor exceptions}}
+ - \textbf{\textcolor{myblue}{software interrupts}}
+ - \textbf{\textcolor{mygreen}{hardware interrupts}}
+
+\vspace{.3cm}
+
+- **To each interrupt is associated an Interrupt Service Routine (ISR)**
+ - this ISR is a function that is executed when the associated interrupt is triggered
+
+[//]: # ----------------------------------------------------------------
+## Interrupt Vector Table (IVT)
+
+:::::: {.columns}
+::: {.column width="55%"}
+
+\small
+
+- The IVT **associates an interrupt number to a function**
+- At index `i` of the IVT is stored the **address** of the routine associated to interrupt number `i`
+- When an interrupt is triggered, the corresponding ISR is executed
+- The IA-32 architecture supports an IVT of up to 256 entries
+- IVT entries 0 to 31 are **reserved for processor exceptions**
+
+:::
+::: {.column width="45%"}
+
+\centering
+{ width=90% }
+
+:::
+::::::
+
+[//]: # ----------------------------------------------------------------
+## Processor exceptions (1/2)
+
+- \textbf{\textcolor{myorange}{Processor exceptions}} are triggered by the CPU itself
+- They are triggered when the **CPU is not able to handle an error** caused by the code being executed
+- Exception examples:
+ - accessing an invalid or unmapped address $\rightarrow$ *Page Fault*
+ - writing to a *read-only* page $\rightarrow$ *Page Fault*
+ - division by zero $\rightarrow$ *Divide Error*
+ - executing a privileged instruction while in user mode (ring 3) $\rightarrow$ *General Protection Fault*
+ - etc.
+
+[//]: # ----------------------------------------------------------------
+## Processor exceptions (2/2)
+
+- \textbf{\textcolor{myorange}{Processor exceptions}} are always **synchronous** with respect to the program's execution
+- When the exception is triggered, the corresponding ISR is executed **synchronously**:
+ - once the execution of the ISR is over, the CPU executes the code following the instruction that triggered the exception
+- Processor exceptions are hardwired to specific vector numbers in the IVT (see next slide)
+ - for instance, "division by 0" executes ISR at index 0 in the IVT
+
+[//]: # ----------------------------------------------------------------
+## Processor exceptions for the IA-32 architecture
+
+\centering
+{ width=95% }
+
+[//]: # ----------------------------------------------------------------
+## Classification of processor exceptions
+
+\footnotesize
+
+**Faults**
+
+\vspace{-.3cm}
+- Can generally be corrected; once corrected, the program can be resumed with no loss of continuity
+- The return address for the fault handler points to the faulting instruction[^1]
+
+**Traps**
+
+\vspace{-.3cm}
+- The program can be resumed with no loss of continuity
+- The return address for the trap handler points to the instruction **after** the trapping instruction
+
+**Aborts**
+
+\vspace{-.3cm}
+- Does not always report the precise location of the instruction causing the exception; disallow a restart of
+the program
+- Report severe errors, e.g. hardware, illegal values in system tables
+
+[^1]: CPU restores the machine state to the state **prior** to the faulting instruction
+
+<!--
+Excerpt from Intel64_IA32_Manual-Vol3-System_Programming_Guide "Exception Classifications" section:
+
+Exceptions are classified as faults, traps, or aborts depending on the way they are
+reported and whether the instruction that caused the exception can be restarted
+without loss of program or task continuity.
+
+- **Faults**: exception that can generally be corrected and that, once
+corrected, allows the program to be restarted with no loss of continuity. When a
+fault is reported, the processor restores the machine state to the state prior to
+the beginning of execution of the faulting instruction. The return address (saved
+contents of the CS and EIP registers) for the fault handler points to the faulting
+instruction, rather than to the instruction following the faulting instruction.
+
+- **Traps**: exception that is reported immediately following the
+execution of the trapping instruction. Traps allow execution of a program or task
+to be continued without loss of program continuity. The return address for the
+trap handler points to the instruction to be executed after the trapping
+instruction.
+
+- **Aborts**: exception that does not always report the precise
+location of the instruction causing the exception and does not allow a restart of
+the program or task that caused the exception. Aborts are used to report severe
+errors, such as hardware errors and inconsistent or illegal values in system
+tables.
+-->
+
+[//]: # ----------------------------------------------------------------
+## Double fault exception and triple fault
+
+**Double Fault Exception** (index 8 in IVT)
+
+\vspace{-.2cm}
+- The CPU detected a second exception **while** calling an exception handler for a prior exception
+
+\vspace{.5cm}
+
+**\textcolor{myred}{Triple Fault}**
+
+\vspace{-.2cm}
+- If another exception occurs **while** attempting to call the double-fault handler, the **CPU enters shutdown mode and reboots**
+- Important to implement a double fault handler **to prevent** uncontrolled **reboots**
+
+[//]: # ----------------------------------------------------------------
+## Software interrupts
+
+- A \textbf{\textcolor{myblue}{software interrupt}} is triggered by using the `INT` assembler instruction
+- For instance, `INT 42` triggers software interrupt 42
+- When the CPU encounters the following instruction,
+ ```{.small}
+ INT 42
+ ```
+ it performs the following operations:
+ - extracts the address of the ISR stored at index 42 in the IVT
+ - executes the ISR
+
+[//]: # ----------------------------------------------------------------
+## Software interrupts' execution
+
+- Like \textbf{\textcolor{myorange}{processor exceptions}}, \textbf{\textcolor{myblue}{software interrupts}} are always **synchronous**
+- When the `INT` instruction is executed, the corresponding ISR is executed **synchronously**:
+ - once the execution of the ISR is over, the CPU executes the code following the `INT` instruction
+
+[//]: # ----------------------------------------------------------------
+## Hardware interrupts and interrupt requests
+
+- \textbf{\textcolor{mygreen}{Hardware interrupts}} are typically triggered by devices (disk controller, keyboard, sound card, network card, etc.)
+- When a device requires the attention of the CPU, it sends it an **interrupt request (IRQ)**
+- A device triggers an IRQ when data are ready or when a command is completed (e.g. writing to disk, key press, etc.)
+- To each IRQ corresponds a **hardware interrupt**:
+ - a specific device, the Programmable Interrupt Controller (PIC) **maps** an IRQ number to a hardware interrupt number
+ - the hardware interrupt number corresponds to the index (in the IVT) of the ISR to execute
+
+<!--
+- Two types of hardware interrupts :
+ - Non Maskable Interrupts (NMI)
+ - Interrupt Requests (IRQ)
+- An NMI implies a hardware problem (faulty memory, bus error, etc.). NMIs cannot be ignored or masked. Purpose: to prevent the machine from running, in order to avoid data loss.
+-->
+
+[//]: # ----------------------------------------------------------------
+## Hardware interrupts' execution
+
+- When a device triggers an IRQ, the corresponding hardware interrupt is triggered
+ - the CPU is interrupted **asynchronously** and executes the ISR corresponding to the hardware interrupt
+- By opposition to software interrupts, hardware interrupts are **asynchronous**, i.e. they are triggered at any time during the CPU execution flow
+- The `STI`/`CLI` assembly instructions are used to mask/unmask (enable/disable) hardware interrupts
+
+[//]: # ----------------------------------------------------------------
+## IRQs, hardware interrupts and ISRs
+
+\centering
+{ width=100% }
+
+
+[//]: # ----------------------------------------------------------------
+## IRQ to hardware interrupt mapping at boot
+
+\scriptsize
+
+**IRQ** **Interrupt** **Description**
+------- ------------- -----------------------
+0 0x08 System timer (PIT)
+1 0x09 Keyboard
+2 0x0A Redirected to slave PIC
+3 0x0B Serial port (COM2/COM4)
+4 0x0C Serial port (COM1/COM3)
+5 0x0D Sound card
+6 0x0E Floppy disk controller
+7 0x0F Parallel port
+8 0x70 Real time clock
+9 0x71 Redirected to IRQ2
+10 0x72 Reserved
+11 0x73 Reserved
+12 0x74 P/S mouse
+13 0x75 Math coprocessor
+14 0x76 Hard disk controller
+15 0x77 Reserved
+
+[//]: # ----------------------------------------------------------------
+## Hardware interrupt acknowledgement
+
+- Once the execution of a hardware interrupt's ISR is over, the CPU **must notify the PIC** that the IRQ was handled
+ - done by sending the PIC an end of interrupt (EOI) command
+ - usually done at the end of the ISR
+ - this process is called **interrupt acknowledgement**
+ - (the PIC can be programmed to automatically issue an EOI)
+
+\vspace{.5cm}
+- **\textcolor{myred}{If an interrupt is not acknowledged, it won't be triggered again!}**
+
+[//]: # ----------------------------------------------------------------
+## Interrupt Descriptor Table
+
+- On Intel processors, the Interrupt Vector Table (IVT) is called **Interrupt Descriptor Table (IDT)**
+- The IDT defines, for **all interrupt types**, software, hardware and exception, the ISR corresponding to each interrupt number
+- The IDT resides in RAM
+
+[//]: # ----------------------------------------------------------------
+## IDT content
+
+- The IDT contains **interrupt descriptors** (also called *gates*)
+- An **interrupt descriptor** is a 64-bit data structure that mainly defines:
+ - the interrupt descriptor **type**
+ - the **address of the ISR** (also called *offset*)
+ - the **privilege level** (= who can call this interrupt)
+- The IDT is simply an array of **interrupt descriptor** structures
+
+[//]: # ----------------------------------------------------------------
+## Structure of an IDT interrupt descriptor
+
+\small
+
+```{.c .verysmall}
+typedef struct {
+ u16 offset15_0; // lower 16 bits of ISR's address
+ u16 selector; // segment selector for code segment
+ u16 reserved : 8;
+ u16 type : 5; // descriptor type: LDT, task, TSS,
+ // call, trap, interrupt
+ u16 dpl : 2; // privilege level (0-3)
+ u16 p : 1; // segment present (should be 1)
+ u16 offset31_16; // higher 16 bits of ISR's address
+} __attribute__((packed)) idt_entry_t;
+```
+
+- `offset`: specifies the ISR address (32 bits)
+- `selector`: segment selector in which the ISR resides
+- `type`: descriptor type: LDT, task, TSS, call, trap, interrupt
+- `DPL`: privilege level (kernel/ring 0 or user/ring 3) required to execute the ISR
+
+<!--
+\vspace{-.4cm}
+
+\centering
+{ width=100% }
+-->
+
+[//]: # ----------------------------------------------------------------
+## Interrupt descriptors
+
+- Many types (6) of interrupt descriptors exist, but we only present two types:
+ - **Interrupt** Gates
+ - **Trap** Gates
+
+- The only difference is their behavior during the execution of the ISR:
+ - **Interrupt** Gate: hardware interrupts are **masked** (disabled)
+ - **Trap** Gate: hardware interrupts are **not masked** (enabled)
+<!--
+ (`IF` Flag of `EFLAGS` remains unchanged)
+-->
+
+[//]: # ----------------------------------------------------------------
+## How does the CPU find the IDT?
+
+- The CPU needs to know where the IDT is located in physical memory
+ - it uses a dedicated register, `IDTR`, that must point to the IDT
+- The `IDTR` register points to a **structure in RAM** defining where the IDT is located and how long it is
+- The `LIDT` instruction is used to load the `IDTR` register with the above structure's address
+
+[//]: # ----------------------------------------------------------------
+## Code example: loading the IDT
+
+\footnotesize
+IDT initialization code (C):
+```{.c .tiny}
+typedef struct { // Struct defining where the IDT resides
+ uint16_t limit; // Size of the IDT in bytes
+ uint32_t base; // Address of the IDT
+} __attribute__((packed)) idt_ptr_t;
+
+static idt_entry_t idt[256]; // IDT
+static idt_ptr_t idt_ptr; // declares an idt_ptr_t struct
+
+void idt_init() {
+ memset(idt, 0, sizeof(idt)); // Clears the IDT
+ idt_ptr.limit = sizeof(idt)-1; // Setup the idt_ptr_t structure
+ idt_ptr.base = (uint32_t)&idt; // to points to the IDT
+ idt_load(&idt_ptr); // Loads the IDT (asm function)
+}
+```
+
+\footnotesize
+Loading the IDTR registers requires the `lidt` instruction (asm):
+```{.assembly .tiny}
+idt_load:
+ mov eax,[esp+4] ; Address of the idt_ptr struct passed in arg.
+ lidt [eax] ; Loads the IDT
+ ret
+```
+
+
+[//]: # ----------------------------------------------------------------
+## Locating the IDT with the IDTR register
+
+\centering
+{ width=100% }
+
+<!--
+[//]: # ----------------------------------------------------------------
+## IDT and IDTR register (1/2)
+
+- Similarily to the GDT, the IDT is located by the CPU using the `IDTR` register
+- The 48-bit `IDTR` register contains:
+ - IDT base address (32 bits)
+ - IDT limit (16 bits); as with the GDT, this limit indicates the size of the IDT in bytes - 1.
+- The `lidt` assembly instruction is used to load the IDT into the `IDTR` register so that it can be taken into account by the CPU.
+ - Similar to the `lgdt` instruction and `LGDTR` register when programming the GDT
+
+[//]: # ----------------------------------------------------------------
+## IDT and IDTR register (2/2)
+
+- The `lidt` instruction takes a single argument, the address of a 48-bit structure specifying the base address of the IDT and its size
+- Example: loading the `IDTR` register:
+ ```{.verysmall}
+ lidt [eax] ; where eax points to a 48 bits structure
+ ```
+-->
+
+[//]: # ----------------------------------------------------------------
+## Execution workflow of a software or hardware interrupt
+
+\footnotesize
+
+What happens when CPU executes `INT 60` or handles hardware interrupt 60?
+
+1. Using the IDTR register, CPU locates the IDT in RAM
+1. CPU checks IDT limit (size) is < 64-bits * 256; if not $\rightarrow$ exception!
+1. CPU reads interrupt descriptor at index 60 in the IDT
+1. CPU checks ISR can be executed at current privilege level; if not $\rightarrow$ exception!
+1. CPU extracts address of ISR to execute from interrupt descriptor
+1. CPU saves return context on stack (`EFLAGS`, `CS`, and `EIP` registers) to resume execution where it left of before the interruption
+1. CPU executes ISR code (which must ends with an `IRET` instruction)
+1. `IRET` reads the return context from the stack to resume execution
+
+[//]: # ----------------------------------------------------------------
+## Execution workflow of an exception
+
+\footnotesize
+
+What happens when exception 13 occurs? (difference with previous slide in \textcolor{myblue}{blue}):
+
+1. Using the IDTR register, CPU locates the IDT in RAM
+1. CPU checks IDT limit (size) is < 64-bits * 256; if not $\rightarrow$ exception!
+1. CPU reads interrupt descriptor at index 13 in the IDT
+1. CPU checks ISR can be executed at current privilege level; if not $\rightarrow$ exception!
+1. CPU extracts address of ISR to execute from interrupt descriptor
+1. \textcolor{myblue}{If a fault, loads `CS` and `EIP` with address of the instruction that caused the exception so it can be executed again}
+1. CPU saves return context on stack (`EFLAGS`, `CS`, and `EIP` registers) to resume execution where it left of before the interruption
+1. \textcolor{myblue}{If the exception carries an error code, saves it on the stack}
+1. CPU executes ISR code (which must ends with an `IRET` instruction)
+1. `IRET` reads the return context from the stack to resume execution
+
+[//]: # ----------------------------------------------------------------
+## Execution context
+
+\small
+
+- We don't want the ISR code to modify the state of registers, otherwise the code following the ISR call **will not behave properly!**
+
+- For this reason, the ISR must **perserve** the full CPU context at the beginning of the routine and **restore** it at the end
+
+\vfill
+
+\centering
+{ width=70% }
+
+[//]: # ----------------------------------------------------------------
+## ISR: important remarks
+
+- Every ISR must be **as short as possible** since during its execution hardware interrupts are often masked
+ - if an ISR takes too long to complete, subsequent hardware interrupts might be missed!
+
+- Usually, the code of an ISR is divided into two parts:
+ - a low-level part, written in assembly, which:
+ - preserves and restores the CPU context
+ - calls the high-level part of the ISR
+ - a high-level part, written in C, which implements the actual behavior of the ISR
+
+<!--
+[//]: # ----------------------------------------------------------------
+## ISR (2/2)
+
+- All ISRs must save the CPU context and update the `DS` register in order to access the correct data (typically kernel data, so `DS` $\leftarrow$ kernel data selector).
+- In the case of `textbf{\textcolor{myorange}}{processor exceptions}}, an error code may or may not be **deposited on the stack, depending on the exception** (cf. table on slide 7).
+-->
+
+[//]: # ----------------------------------------------------------------
+## Lab code: exception handler workflow
+
+\centering
+{ width=100% }
+
+[//]: # ----------------------------------------------------------------
+## Lab code: hardware interrupt handler workflow
+
+\centering
+{ width=100% }
+
+
+[//]: # ----------------------------------------------------------------
+## Resources
+
+\small
+
+- Understanding the Linux Kernel (2nd Edition), Daniel P. Bovet, Marco Cesati, O'Reilly
+
+\small
+
+- Interrupts, Exceptions, ISR and IDT at wiki.osdev.org
+
+ - \footnotesize [\textcolor{myblue}{https://wiki.osdev.org/Interrupts}](https://wiki.osdev.org/Interrupts)
+ - \footnotesize [\textcolor{myblue}{https://wiki.osdev.org/Exceptions}](https://wiki.osdev.org/Exceptions)
+ - \footnotesize [\textcolor{myblue}{https://wiki.osdev.org/Interrupt\_Service\_Routines}](https://wiki.osdev.org/Interrupt_Service_Routines)
+ - \footnotesize [\textcolor{myblue}{https://wiki.osdev.org/Interrupt\_Descriptor\_Table}](https://wiki.osdev.org/Interrupt_Descriptor_Table)
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