From d5b631e49bc810a552eb6ac0f57b943e74525243 Mon Sep 17 00:00:00 2001
From: Joachim Schmidt <joachim.schmidt@hesge.ch>
Date: Wed, 13 Mar 2024 10:43:09 +0100
Subject: [PATCH] Adding some design files.
---
design_files/debug.xdc | 0
design_files/scalp_firmware.xdc | 251 +++++++
design_files/scalp_safe_design.vhd | 438 +++++++++++++
design_files/scalp_zynqps.vhd | 177 +++++
design_files/scalp_zynqps_ipi.tcl | 985 ++++++++++++++++++++++++++++
design_files/timing_constraints.xdc | 31 +
6 files changed, 1882 insertions(+)
create mode 100644 design_files/debug.xdc
create mode 100644 design_files/scalp_firmware.xdc
create mode 100644 design_files/scalp_safe_design.vhd
create mode 100644 design_files/scalp_zynqps.vhd
create mode 100644 design_files/scalp_zynqps_ipi.tcl
create mode 100644 design_files/timing_constraints.xdc
diff --git a/design_files/debug.xdc b/design_files/debug.xdc
new file mode 100644
index 0000000..e69de29
diff --git a/design_files/scalp_firmware.xdc b/design_files/scalp_firmware.xdc
new file mode 100644
index 0000000..ef0aa1c
--- /dev/null
+++ b/design_files/scalp_firmware.xdc
@@ -0,0 +1,251 @@
+############################################################################
+# Programmable Logic placement constraints #
+############################################################################
+
+##### USB interface (bank 13) #####
+# USB_VBUS_PWRFAULT_i
+set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
+
+##### PLL interface (banks 35 and 34) #####
+# PLL_2V5_CLKuWire_o
+set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
+# PLL_2V5_DATAuWire_o
+set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
+# PLL_2V5_LEuWire_o
+set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
+# PLL_2V5_GOE_o
+set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
+# PLL_2V5_LD_i
+set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
+# PLL_2V5_SYNC_n_o
+set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
+# PLL_2V5_CLKIN0_LOS_i (bank 34)
+set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
+# PLL_2V5_CLKIN1_LOS_i (bank 34)
+set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
+
+##### GTP interfaces (bank 112) #####
+#set_property PACKAGE_PIN U9 [get_ports GTPRefClk0PxCI]
+#set_property PACKAGE_PIN V9 [get_ports GTPRefClk0NxCI]
+#set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
+#set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
+#set_property PACKAGE_PIN Y8 [get_ports GTPFromNorthNxSI]
+#set_property PACKAGE_PIN W8 [get_ports GTPFromNorthPxSI]
+#set_property PACKAGE_PIN Y4 [get_ports GTPToNorthNxSO]
+#set_property PACKAGE_PIN W4 [get_ports GTPToNorthPxSO]
+#set_property PACKAGE_PIN AB7 [get_ports GTPFromSouthNxSI]
+#set_property PACKAGE_PIN AA7 [get_ports GTPFromSouthPxSI]
+#set_property PACKAGE_PIN AB3 [get_ports GTPToSouthNxSO]
+#set_property PACKAGE_PIN AA3 [get_ports GTPToSouthPxSO]
+#set_property PACKAGE_PIN AB9 [get_ports GTPFromEastNxSI]
+#set_property PACKAGE_PIN AA9 [get_ports GTPFromEastPxSI]
+#set_property PACKAGE_PIN AB5 [get_ports GTPToEastNxSO]
+#set_property PACKAGE_PIN AA5 [get_ports GTPToEastPxSO]
+#set_property PACKAGE_PIN Y6 [get_ports GTPFromWestNxSI]
+#set_property PACKAGE_PIN W6 [get_ports GTPFromWestPxSI]
+#set_property PACKAGE_PIN Y2 [get_ports GTPToWestNxSO]
+#set_property PACKAGE_PIN W2 [get_ports GTPToWestPxSO]
+
+##### LVDS links towards edge connectors #####
+# North (bank 35)
+#set_property PACKAGE_PIN "E8" [get_ports "LVDS2V5North7PxSIO"]
+#set_property PACKAGE_PIN "D8" [get_ports "LVDS2V5North7NxSIO"]
+#set_property PACKAGE_PIN "D7" [get_ports "LVDS2V5North6PxSIO"]
+#set_property PACKAGE_PIN "D6" [get_ports "LVDS2V5North6NxSIO"]
+#set_property PACKAGE_PIN "C8" [get_ports "LVDS2V5North5PxSIO"]
+#set_property PACKAGE_PIN "B8" [get_ports "LVDS2V5North5NxSIO"]
+#set_property PACKAGE_PIN "B7" [get_ports "LVDS2V5North4PxSIO"]
+#set_property PACKAGE_PIN "B6" [get_ports "LVDS2V5North4NxSIO"]
+#set_property PACKAGE_PIN "A7" [get_ports "LVDS2V5North3PxSIO"]
+#set_property PACKAGE_PIN "A6" [get_ports "LVDS2V5North3NxSIO"]
+#set_property PACKAGE_PIN "A5" [get_ports "LVDS2V5North2PxSIO"]
+#set_property PACKAGE_PIN "A4" [get_ports "LVDS2V5North2NxSIO"]
+#set_property PACKAGE_PIN "B2" [get_ports "LVDS2V5North1PxSIO"]
+#set_property PACKAGE_PIN "B1" [get_ports "LVDS2V5North1NxSIO"]
+#set_property PACKAGE_PIN "A2" [get_ports "LVDS2V5North0PxSIO"]
+#set_property PACKAGE_PIN "A1" [get_ports "LVDS2V5North0NxSIO"]
+# South (bank 13)
+#set_property PACKAGE_PIN "V15" [get_ports "LVDS2V5South7PxSIO"]
+#set_property PACKAGE_PIN "W15" [get_ports "LVDS2V5South7NxSIO"]
+#set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
+#set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
+#set_property PACKAGE_PIN "V13" [get_ports "LVDS2V5South5PxSIO"]
+#set_property PACKAGE_PIN "V14" [get_ports "LVDS2V5South5NxSIO"]
+#set_property PACKAGE_PIN "Y12" [get_ports "LVDS2V5South4PxSIO"]
+#set_property PACKAGE_PIN "Y13" [get_ports "LVDS2V5South4NxSIO"]
+#set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
+#set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
+#set_property PACKAGE_PIN "W12" [get_ports "LVDS2V5South2PxSIO"]
+#set_property PACKAGE_PIN "W13" [get_ports "LVDS2V5South2NxSIO"]
+#set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
+#set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
+#set_property PACKAGE_PIN "V11" [get_ports "LVDS2V5South0PxSIO"]
+#set_property PACKAGE_PIN "W11" [get_ports "LVDS2V5South0NxSIO"]
+# East (bank 13)
+#set_property PACKAGE_PIN "V16" [get_ports "LVDS2V5East7PxSIO"]
+#set_property PACKAGE_PIN "W16" [get_ports "LVDS2V5East7NxSIO"]
+#set_property PACKAGE_PIN "W17" [get_ports "LVDS2V5East6PxSIO"]
+#set_property PACKAGE_PIN "Y17" [get_ports "LVDS2V5East6NxSIO"]
+#set_property PACKAGE_PIN "U13" [get_ports "LVDS2V5East5PxSIO"]
+#set_property PACKAGE_PIN "U14" [get_ports "LVDS2V5East5NxSIO"]
+#set_property PACKAGE_PIN "V18" [get_ports "LVDS2V5East4PxSIO"]
+#set_property PACKAGE_PIN "W18" [get_ports "LVDS2V5East4NxSIO"]
+#set_property PACKAGE_PIN "U11" [get_ports "LVDS2V5East3PxSIO"]
+#set_property PACKAGE_PIN "U12" [get_ports "LVDS2V5East3NxSIO"]
+#set_property PACKAGE_PIN "U19" [get_ports "LVDS2V5East2PxSIO"]
+#set_property PACKAGE_PIN "V19" [get_ports "LVDS2V5East2NxSIO"]
+#set_property PACKAGE_PIN "R17" [get_ports "LVDS2V5East1PxSIO"]
+#set_property PACKAGE_PIN "T17" [get_ports "LVDS2V5East1NxSIO"]
+#set_property PACKAGE_PIN "U17" [get_ports "LVDS2V5East0PxSIO"]
+#set_property PACKAGE_PIN "U18" [get_ports "LVDS2V5East0NxSIO"]
+# West (bank 35)
+#set_property PACKAGE_PIN "H4" [get_ports "LVDS2V5West7PxSIO"]
+#set_property PACKAGE_PIN "H3" [get_ports "LVDS2V5West7NxSIO"]
+#set_property PACKAGE_PIN "H1" [get_ports "LVDS2V5West6PxSIO"]
+#set_property PACKAGE_PIN "G1" [get_ports "LVDS2V5West6NxSIO"]
+#set_property PACKAGE_PIN "G3" [get_ports "LVDS2V5West5PxSIO"]
+#set_property PACKAGE_PIN "G2" [get_ports "LVDS2V5West5NxSIO"]
+#set_property PACKAGE_PIN "F2" [get_ports "LVDS2V5West4PxSIO"]
+#set_property PACKAGE_PIN "F1" [get_ports "LVDS2V5West4NxSIO"]
+#set_property PACKAGE_PIN "G4" [get_ports "LVDS2V5West3PxSIO"]
+#set_property PACKAGE_PIN "F4" [get_ports "LVDS2V5West3NxSIO"]
+#set_property PACKAGE_PIN "E2" [get_ports "LVDS2V5West2PxSIO"]
+#set_property PACKAGE_PIN "D2" [get_ports "LVDS2V5West2NxSIO"]
+#set_property PACKAGE_PIN "E4" [get_ports "LVDS2V5West1PxSIO"]
+#set_property PACKAGE_PIN "E3" [get_ports "LVDS2V5West1NxSIO"]
+#set_property PACKAGE_PIN "D1" [get_ports "LVDS2V5West0PxSIO"]
+#set_property PACKAGE_PIN "C1" [get_ports "LVDS2V5West0NxSIO"]
+
+##### LVDS links towards top-bottom connectors #####
+# Top (bank 34)
+#set_property PACKAGE_PIN "J8" [get_ports "LVDS2V5Top7PxSIO"]
+#set_property PACKAGE_PIN "K8" [get_ports "LVDS2V5Top7NxSIO"]
+#set_property PACKAGE_PIN "K7" [get_ports "LVDS2V5Top6PxSIO"]
+#set_property PACKAGE_PIN "L7" [get_ports "LVDS2V5Top6NxSIO"]
+#set_property PACKAGE_PIN "N8" [get_ports "LVDS2V5Top5PxSIO"]
+#set_property PACKAGE_PIN "P8" [get_ports "LVDS2V5Top5NxSIO"]
+#set_property PACKAGE_PIN "M8" [get_ports "LVDS2V5Top4PxSIO"]
+#set_property PACKAGE_PIN "M7" [get_ports "LVDS2V5Top4NxSIO"]
+#set_property PACKAGE_PIN "L6" [get_ports "LVDS2V5Top3PxSIO"]
+#set_property PACKAGE_PIN "M6" [get_ports "LVDS2V5Top3NxSIO"]
+#set_property PACKAGE_PIN "J7" [get_ports "LVDS2V5Top2PxSIO"]
+#set_property PACKAGE_PIN "J6" [get_ports "LVDS2V5Top2NxSIO"]
+#set_property PACKAGE_PIN "J5" [get_ports "LVDS2V5Top1PxSIO"]
+#set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
+#set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
+#set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
+# Bottom (bank 34)
+#set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
+#set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
+#set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
+#set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
+#set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
+#set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
+#set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
+#set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
+#set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
+#set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
+#set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
+#set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
+#set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
+#set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
+#set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
+#set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
+
+##### Switches (banks 34) #####
+set_property PACKAGE_PIN "L4" [get_ports "SwitchesxDI[0]"]
+set_property IOSTANDARD LVCMOS25 [get_ports "SwitchesxDI[0]"]
+set_property PACKAGE_PIN "T1" [get_ports "SwitchesxDI[1]"]
+set_property IOSTANDARD LVCMOS25 [get_ports "SwitchesxDI[1]"]
+
+##### RGB LEDs (banks 34 and 13) #####
+# LED1_2V5_R_o (bank 34)
+set_property PACKAGE_PIN L2 [get_ports Led12V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5RxSO]
+# LED1_2V5_G_o (bank 34)
+set_property PACKAGE_PIN L1 [get_ports Led12V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5GxSO]
+# LED1_2V5_B_o (bank 34)
+set_property PACKAGE_PIN R8 [get_ports Led12V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5BxSO]
+# LED2_2V5_R_o (bank 13)
+set_property PACKAGE_PIN T16 [get_ports Led22V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5RxSO]
+# LED2_2V5_G_o (bank 13)
+set_property PACKAGE_PIN U16 [get_ports Led22V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5GxSO]
+# LED2_2V5_B_o (bank 13)
+set_property PACKAGE_PIN AA20 [get_ports Led22V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5BxSO]
+
+##### Self reset (bank 34) #####
+set_property PACKAGE_PIN H8 [get_ports SelfRstxRNO]
+set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
+
+##### Clock dedicated pins (Multi-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "D5" [get_ports "PLLClk2V5LocalPxCI"]
+#set_property PACKAGE_PIN "C4" [get_ports "PLLClk2V5LocalNxCI"]
+#set_property PACKAGE_PIN "B4" [get_ports "PLLClk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "B3" [get_ports "PLLClk2V5NorthNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "T2" [get_ports "PLLClk2V5TopxCI"]
+#set_property PACKAGE_PIN "L5" [get_ports "PLLClk2V5BottomxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "Y14" [get_ports "PLLClk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "Y15" [get_ports "PLLClk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "Y18" [get_ports "Clk2V5RecoveryPxCO"]
+#set_property PACKAGE_PIN "Y19" [get_ports "Clk2V5RecoveryNxCO"]
+
+##### Clock dedicated pins (Single-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "C6" [get_ports "Clk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "C5" [get_ports "Clk2V5NorthNxCI"]
+#set_property PACKAGE_PIN "D3" [get_ports "Clk2V5WestPxCI"]
+#set_property PACKAGE_PIN "C3" [get_ports "Clk2V5WestNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
+#set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
+#set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
+#set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
+#set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
+
+##### Clock outputs #####
+## Bank 35
+#set_property PACKAGE_PIN "F7" [get_ports "Clk2V5NorthPxCO"]
+#set_property PACKAGE_PIN "E7" [get_ports "Clk2V5NorthNxCO"]
+#set_property PACKAGE_PIN "F5" [get_ports "Clk2V5WestPxCO"]
+#set_property PACKAGE_PIN "E5" [get_ports "Clk2V5WestNxCO"]
+# Bank 34
+#set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
+#set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
+#set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
+#set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
+# Bank 13
+#set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
+#set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
+#set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
+#set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
+
+############################################################################
+# Other constraints #
+############################################################################
+
+##### Operating conditions (for XPE report) #####
+# Extended grade (as for -2 speed grade) and maximum consumption estimation
+set_operating_conditions -grade extended -process maximum
+# 4'' by 4'' PCB, no heatsink, no air flow
+set_operating_conditions -airflow 0 -heatsink none -board small
diff --git a/design_files/scalp_safe_design.vhd b/design_files/scalp_safe_design.vhd
new file mode 100644
index 0000000..3e7f4ba
--- /dev/null
+++ b/design_files/scalp_safe_design.vhd
@@ -0,0 +1,438 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_user_design - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.2 xc7z015clg485-2
+-- Tool version: 2023.2
+-- Description: scalp_user_design
+--
+-- Last update: 2024-03-13
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+-- use ieee.math_real.all;
+use ieee.math_real."ceil";
+use ieee.math_real."log2";
+-- use ieee.std_logic_unsigned.all;
+-- use ieee.std_logic_arith.all;
+-- use ieee.std_logic_misc.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library axi_lib;
+use axi_lib.scalp_axi_pkg.all;
+
+entity scalp_user_design is
+
+ generic (
+ C_USE_IBERT : boolean := false;
+ C_DEBUG_MODE : boolean := false;
+ C_GPIO_SWITCHES_SIZE : integer range 0 to 32 := 2);
+
+ port (
+ -----------------------------------------------------------------------
+ -- Names defined and not described in the constraint file.
+ -----------------------------------------------------------------------
+ -- Zynq FIXED_IO
+ PSClkxCIO : inout std_logic;
+ PSSRstxRNIO : inout std_logic;
+ PSPorxSNIO : inout std_logic;
+ -- DDR interface
+ DDRClkxCNIO : inout std_logic;
+ DDRClkxCPIO : inout std_logic;
+ DDRDRstxRNIO : inout std_logic;
+ DDRCasxSNIO : inout std_logic;
+ DDRCkexSIO : inout std_logic;
+ DDRCsxSNIO : inout std_logic;
+ DDROdtxSIO : inout std_logic;
+ DDRRasxSNIO : inout std_logic;
+ DDRWexSNIO : inout std_logic;
+ DDRBankAddrxDIO : inout std_logic_vector(2 downto 0);
+ DDRAddrxDIO : inout std_logic_vector(14 downto 0);
+ DDRVrxSNIO : inout std_logic;
+ DDRVrxSPIO : inout std_logic;
+ DDRDmxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqxDIO : inout std_logic_vector(31 downto 0);
+ DDRDqsxDNIO : inout std_logic_vector(3 downto 0);
+ DDRDqsxDPIO : inout std_logic_vector(3 downto 0);
+ -- MIO Interface
+ MIOxDIO : inout std_logic_vector(53 downto 0);
+ -----------------------------------------------------------------------
+ -- USB signals
+ UsbVbusPwrFaultxSI : in std_logic;
+ -- PLL interface
+ Pll2V5ClkuWirexCO : out std_logic; -- Clock (from SPI1_SCLK)
+ Pll2V5DatauWirexSO : out std_logic; -- Data (from SPI1_MOSI)
+ Pll2V5LEuWirexSO : out std_logic; -- Latch enable (from SPI1_SS)
+ Pll2V5GOExSO : out std_logic; -- Global Output Enable
+ Pll2V5LDxSI : in std_logic; -- Lock Detect
+ Pll2V5SyncxSO : out std_logic; -- Sync
+ Pll2V5ClkIn0LOSxSI : in std_logic; -- FPGA clock Loss of Sync
+ Pll2V5ClkIn1LOSxSI : in std_logic; -- External oscillator Loss of Sync
+ -- GTP interfaces
+ -- Clocks
+ -- GTPRefClk0PxCI : in std_logic;
+ -- GTPRefClk0NxCI : in std_logic;
+ -- GTPRefClk1PxCI : in std_logic;
+ -- GTPRefClk1NxCI : in std_logic;
+ -- North
+ -- GTPFromNorthPxSI : in std_logic;
+ -- GTPFromNorthNxSI : in std_logic;
+ -- GTPToNorthPxSO : out std_logic;
+ -- GTPToNorthNxSO : out std_logic;
+ -- East
+ -- GTPFromEastPxSI : in std_logic;
+ -- GTPFromEastNxSI : in std_logic;
+ -- GTPToEastPxSO : out std_logic;
+ -- GTPToEastNxSO : out std_logic;
+ -- South
+ -- GTPFromSouthPxSI : in std_logic;
+ -- GTPFromSouthNxSI : in std_logic;
+ -- GTPToSouthPxSO : out std_logic;
+ -- GTPToSouthNxSO : out std_logic;
+ -- West
+ -- GTPFromWestPxSI : in std_logic;
+ -- GTPFromWestNxSI : in std_logic;
+ -- GTPToWestPxSO : out std_logic;
+ -- GTPToWestNxSO : out std_logic;
+ -- LVDS links towards edge connectors
+ -- North
+ -- LVDS2V5North0PxSIO : inout std_logic;
+ -- LVDS2V5North0NxSIO : inout std_logic;
+ -- LVDS2V5North1PxSIO : inout std_logic;
+ -- LVDS2V5North1NxSIO : inout std_logic;
+ -- LVDS2V5North2PxSIO : inout std_logic;
+ -- LVDS2V5North2NxSIO : inout std_logic;
+ -- LVDS2V5North3PxSIO : inout std_logic;
+ -- LVDS2V5North3NxSIO : inout std_logic;
+ -- LVDS2V5North4PxSIO : inout std_logic;
+ -- LVDS2V5North4NxSIO : inout std_logic;
+ -- LVDS2V5North5PxSIO : inout std_logic;
+ -- LVDS2V5North5NxSIO : inout std_logic;
+ -- LVDS2V5North6PxSIO : inout std_logic;
+ -- LVDS2V5North6NxSIO : inout std_logic;
+ -- LVDS2V5North7PxSIO : inout std_logic;
+ -- LVDS2V5North7NxSIO : inout std_logic;
+ -- South
+ -- LVDS2V5South0PxSIO : inout std_logic;
+ -- LVDS2V5South0NxSIO : inout std_logic;
+ -- LVDS2V5South1PxSIO : inout std_logic;
+ -- LVDS2V5South1NxSIO : inout std_logic;
+ -- LVDS2V5South2PxSIO : inout std_logic;
+ -- LVDS2V5South2NxSIO : inout std_logic;
+ -- LVDS2V5South3PxSIO : inout std_logic;
+ -- LVDS2V5South3NxSIO : inout std_logic;
+ -- LVDS2V5South4PxSIO : inout std_logic;
+ -- LVDS2V5South4NxSIO : inout std_logic;
+ -- LVDS2V5South5PxSIO : inout std_logic;
+ -- LVDS2V5South5NxSIO : inout std_logic;
+ -- LVDS2V5South6PxSIO : inout std_logic;
+ -- LVDS2V5South6NxSIO : inout std_logic;
+ -- LVDS2V5South7PxSIO : inout std_logic;
+ -- LVDS2V5South7NxSIO : inout std_logic;
+ -- East
+ -- LVDS2V5East0PxSIO : inout std_logic;
+ -- LVDS2V5East0NxSIO : inout std_logic;
+ -- LVDS2V5East1PxSIO : inout std_logic;
+ -- LVDS2V5East1NxSIO : inout std_logic;
+ -- LVDS2V5East2PxSIO : inout std_logic;
+ -- LVDS2V5East2NxSIO : inout std_logic;
+ -- LVDS2V5East3PxSIO : inout std_logic;
+ -- LVDS2V5East3NxSIO : inout std_logic;
+ -- LVDS2V5East4PxSIO : inout std_logic;
+ -- LVDS2V5East4NxSIO : inout std_logic;
+ -- LVDS2V5East5PxSIO : inout std_logic;
+ -- LVDS2V5East5NxSIO : inout std_logic;
+ -- LVDS2V5East6PxSIO : inout std_logic;
+ -- LVDS2V5East6NxSIO : inout std_logic;
+ -- LVDS2V5East7PxSIO : inout std_logic;
+ -- LVDS2V5East7NxSIO : inout std_logic;
+ -- West
+ -- LVDS2V5West0PxSIO : inout std_logic;
+ -- LVDS2V5West0NxSIO : inout std_logic;
+ -- LVDS2V5West1PxSIO : inout std_logic;
+ -- LVDS2V5West1NxSIO : inout std_logic;
+ -- LVDS2V5West2PxSIO : inout std_logic;
+ -- LVDS2V5West2NxSIO : inout std_logic;
+ -- LVDS2V5West3PxSIO : inout std_logic;
+ -- LVDS2V5West3NxSIO : inout std_logic;
+ -- LVDS2V5West4PxSIO : inout std_logic;
+ -- LVDS2V5West4NxSIO : inout std_logic;
+ -- LVDS2V5West5PxSIO : inout std_logic;
+ -- LVDS2V5West5NxSIO : inout std_logic;
+ -- LVDS2V5West6PxSIO : inout std_logic;
+ -- LVDS2V5West6NxSIO : inout std_logic;
+ -- LVDS2V5West7PxSIO : inout std_logic;
+ -- LVDS2V5West7NxSIO : inout std_logic;
+ -- LVDS links towards top-bottom connectors
+ -- Top
+ -- LVDS2V5Top0PxSIO : inout std_logic;
+ -- LVDS2V5Top0NxSIO : inout std_logic;
+ -- LVDS2V5Top1PxSIO : inout std_logic;
+ -- LVDS2V5Top1NxSIO : inout std_logic;
+ -- LVDS2V5Top2PxSIO : inout std_logic;
+ -- LVDS2V5Top2NxSIO : inout std_logic;
+ -- LVDS2V5Top3PxSIO : inout std_logic;
+ -- LVDS2V5Top3NxSIO : inout std_logic;
+ -- LVDS2V5Top4PxSIO : inout std_logic;
+ -- LVDS2V5Top4NxSIO : inout std_logic;
+ -- LVDS2V5Top5PxSIO : inout std_logic;
+ -- LVDS2V5Top5NxSIO : inout std_logic;
+ -- LVDS2V5Top6PxSIO : inout std_logic;
+ -- LVDS2V5Top6NxSIO : inout std_logic;
+ -- LVDS2V5Top7PxSIO : inout std_logic;
+ -- LVDS2V5Top7NxSIO : inout std_logic;
+ -- Bottom
+ -- LVDS2V5Bottom0PxSIO : inout std_logic;
+ -- LVDS2V5Bottom0NxSIO : inout std_logic;
+ -- LVDS2V5Bottom1PxSIO : inout std_logic;
+ -- LVDS2V5Bottom1NxSIO : inout std_logic;
+ -- LVDS2V5Bottom2PxSIO : inout std_logic;
+ -- LVDS2V5Bottom2NxSIO : inout std_logic;
+ -- LVDS2V5Bottom3PxSIO : inout std_logic;
+ -- LVDS2V5Bottom3NxSIO : inout std_logic;
+ -- LVDS2V5Bottom4PxSIO : inout std_logic;
+ -- LVDS2V5Bottom4NxSIO : inout std_logic;
+ -- LVDS2V5Bottom5PxSIO : inout std_logic;
+ -- LVDS2V5Bottom5NxSIO : inout std_logic;
+ -- LVDS2V5Bottom6PxSIO : inout std_logic;
+ -- LVDS2V5Bottom6NxSIO : inout std_logic;
+ -- LVDS2V5Bottom7PxSIO : inout std_logic;
+ -- LVDS2V5Bottom7NxSIO : inout std_logic;
+ -- Switches
+ SwitchesxDI : in std_logic_vector((C_GPIO_SWITCHES_SIZE - 1) downto 0);
+ -- RGB LEDs
+ Led12V5RxSO : out std_logic;
+ Led12V5GxSO : out std_logic;
+ Led12V5BxSO : out std_logic;
+ Led22V5RxSO : out std_logic;
+ Led22V5GxSO : out std_logic;
+ Led22V5BxSO : out std_logic;
+ -- Self reset (connected to PS_SRSTB)
+ SelfRstxRNO : out std_logic);
+ -- Clocks from PLLs (connected to MRCC pins)
+ -- Local
+ -- PLLClk2V5LocalPxCI : in std_logic;
+ -- PLLClk2V5LocalNxCI : in std_logic;
+ -- -- North
+ -- PLLClk2V5NorthPxCI : in std_logic;
+ -- PLLClk2V5NorthNxCI : in std_logic;
+ -- -- South
+ -- PLLClk2V5SouthPxCI : in std_logic;
+ -- PLLClk2V5SouthNxCI : in std_logic;
+ -- -- Top
+ -- PLLClk2V5TopxCI : in std_logic; -- Single-ended
+ -- -- Bottom
+ -- PLLClk2V5BottomxCI : in std_logic; -- Single-ended
+ -- -- Clocks to/from neighbours
+ -- -- North
+ -- Clk2V5NorthPxCI : in std_logic;
+ -- Clk2V5NorthNxCI : in std_logic;
+ -- Clk2V5NorthPxCO : out std_logic;
+ -- Clk2V5NorthNxCO : out std_logic;
+ -- -- South
+ -- Clk2V5SouthPxCI : in std_logic;
+ -- Clk2V5SouthNxCI : in std_logic;
+ -- Clk2V5SouthPxCO : out std_logic;
+ -- Clk2V5SouthNxCO : out std_logic;
+ -- -- East
+ -- Clk2V5EastPxCI : in std_logic;
+ -- Clk2V5EastNxCI : in std_logic;
+ -- Clk2V5EastPxCO : out std_logic;
+ -- Clk2V5EastNxCO : out std_logic;
+ -- -- West
+ -- Clk2V5WestPxCI : in std_logic;
+ -- Clk2V5WestNxCI : in std_logic;
+ -- Clk2V5WestPxCO : out std_logic;
+ -- Clk2V5WestNxCO : out std_logic;
+ -- -- Top
+ -- Clk2V5TopPxCI : in std_logic;
+ -- Clk2V5TopNxCI : in std_logic;
+ -- Clk2V5TopPxCO : out std_logic;
+ -- Clk2V5TopNxCO : out std_logic;
+ -- -- Bottom
+ -- Clk2V5BottomPxCI : in std_logic;
+ -- Clk2V5BottomNxCI : in std_logic;
+ -- Clk2V5BottomPxCO : out std_logic;
+ -- Clk2V5BottomNxCO : out std_logic;
+ -- -- Recovery
+ -- Clk2V5RecoveryPxCO : out std_logic;
+ -- Clk2V5RecoveryNxCO : out std_logic);
+
+end scalp_user_design;
+
+architecture arch of scalp_user_design is
+
+ -- Constants
+ constant C_REGS_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_REGS_ADDR_SIZE : integer := 4096;
+ constant C_REGS_ADDR_BIT_SIZE : integer range 0 to 32 := integer(ceil(log2(real(C_REGS_ADDR_SIZE))));
+ constant C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
+ constant C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
+ constant C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
+ -- Scalp PWM
+ constant C_PWM_SIZE : integer := 8;
+ constant C_CLK_CNT_LEN : positive := 256;
+
+ -- Components
+ component scalp_zynqps_wrapper is
+ generic (
+ C_AXI4_ARADDR_SIZE : integer range 0 to 32;
+ C_AXI4_RDATA_SIZE : integer range 0 to 32;
+ C_AXI4_RRESP_SIZE : integer range 0 to 2;
+ C_AXI4_AWADDR_SIZE : integer range 0 to 32;
+ C_AXI4_WDATA_SIZE : integer range 0 to 32;
+ C_AXI4_WSTRB_SIZE : integer range 0 to 4;
+ C_AXI4_BRESP_SIZE : integer range 0 to 2);
+ port (
+ FIXED_IO_ps_clk : inout std_logic;
+ FIXED_IO_ps_porb : inout std_logic;
+ FIXED_IO_ps_srstb : inout std_logic;
+ Clk125xCO : out std_logic;
+ Clk125RstxRO : out std_logic;
+ Clk125RstxRNAO : out std_logic;
+ DDR_addr : inout std_logic_vector (14 downto 0);
+ DDR_ba : inout std_logic_vector (2 downto 0);
+ DDR_cas_n : inout std_logic;
+ DDR_ck_n : inout std_logic;
+ DDR_ck_p : inout std_logic;
+ DDR_cke : inout std_logic;
+ DDR_cs_n : inout std_logic;
+ DDR_dm : inout std_logic_vector (3 downto 0);
+ DDR_dq : inout std_logic_vector (31 downto 0);
+ DDR_dqs_n : inout std_logic_vector (3 downto 0);
+ DDR_dqs_p : inout std_logic_vector (3 downto 0);
+ DDR_odt : inout std_logic;
+ DDR_ras_n : inout std_logic;
+ DDR_reset_n : inout std_logic;
+ DDR_we_n : inout std_logic;
+ FIXED_IO_ddr_vrn : inout std_logic;
+ FIXED_IO_ddr_vrp : inout std_logic;
+ Usb0VBusPwrFaultxSI : in std_logic;
+ Spi1MOSIxSO : out std_logic;
+ Spi1SSxSO : out std_logic;
+ Spi1SclkxCO : out std_logic;
+ FIXED_IO_mio : inout std_logic_vector (53 downto 0);
+ GPIOSwitchesxDI : in std_logic_vector((C_GPIO_SWITCHES_SIZE - 1) downto 0);
+ GPIOResetBtnxRNO : out std_logic;
+ IDAxixCO : out t_axi_clk;
+ IDAxixRO : out t_axi_reset;
+ IDAxixDO : out t_axi_m2s;
+ IDAxixDI : in t_axi_s2m);
+ end component scalp_zynqps_wrapper;
+
+ -- Signals
+ -- Clocks
+ -- Processing system clock
+ signal Clk125xC : std_logic := '0';
+ -- Resets
+ -- Processing system reset
+ signal Clk125RstxR : std_logic := '0';
+ signal Clk125RstxRNA : std_logic := '1';
+ -- Firmware ID
+ signal IDAxixC : t_axi_clk := C_AXI_IDLE_CLK;
+ signal IDAxixR : t_axi_reset := C_AXI_IDLE_RESET;
+ signal IDAxiM2SxD : t_axi_m2s := C_AXI_IDLE_M2S;
+ signal IDAxiS2MxD : t_axi_s2m := C_AXI_IDLE_S2M;
+ -- GPIO Switches
+ signal GPIOSwitchesxD : std_logic_vector((C_GPIO_SWITCHES_SIZE - 1) downto 0) := (others => '0');
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ -- Clocks
+ attribute keep of Clk125xC : signal is "true";
+ -- Firmware ID
+ -- attribute mark_debug of IDAxiM2SxD : signal is "true";
+ -- attribute keep of IDAxiM2SxD : signal is "true";
+ -- attribute mark_debug of IDAxiS2MxD : signal is "true";
+ -- attribute keep of IDAxiS2MxD : signal is "true";
+ -- GPIO Switches
+ -- attribute mark_debug of GPIOSwitchesxD : signal is "true";
+ -- attribute keep of GPIOSwitchesxD : signal is "true";
+
+begin
+
+ PSxB : block is
+ begin -- block PSxB
+
+ ZynqxI : entity work.scalp_zynqps_wrapper
+ generic map (
+ C_AXI4_ARADDR_SIZE => C_AXI4_ARADDR_SIZE,
+ C_AXI4_RDATA_SIZE => C_AXI4_RDATA_SIZE,
+ C_AXI4_RRESP_SIZE => C_AXI4_RRESP_SIZE,
+ C_AXI4_AWADDR_SIZE => C_AXI4_AWADDR_SIZE,
+ C_AXI4_WDATA_SIZE => C_AXI4_WDATA_SIZE,
+ C_AXI4_WSTRB_SIZE => C_AXI4_WSTRB_SIZE,
+ C_AXI4_BRESP_SIZE => C_AXI4_BRESP_SIZE)
+ port map (
+ FIXED_IO_ps_clk => PSClkxCIO,
+ FIXED_IO_ps_porb => PSPorxSNIO,
+ FIXED_IO_ps_srstb => PSSRstxRNIO,
+ -- Clk and rst (125Mhz)
+ Clk125xCO => Clk125xC,
+ Clk125RstxRO => Clk125RstxR,
+ Clk125RstxRNAO => Clk125RstxRNA,
+ -- DDR interface
+ DDR_addr => DDRAddrxDIO,
+ DDR_ba => DDRBankAddrxDIO,
+ DDR_cas_n => DDRCasxSNIO,
+ DDR_ck_n => DDRClkxCNIO,
+ DDR_ck_p => DDRClkxCPIO,
+ DDR_cke => DDRCkexSIO,
+ DDR_cs_n => DDRCsxSNIO,
+ DDR_dm => DDRDmxDIO,
+ DDR_dq => DDRDqxDIO,
+ DDR_dqs_n => DDRDqsxDNIO,
+ DDR_dqs_p => DDRDqsxDPIO,
+ DDR_odt => DDROdtxSIO,
+ DDR_ras_n => DDRRasxSNIO,
+ DDR_reset_n => DDRDRstxRNIO,
+ DDR_we_n => DDRWexSNIO,
+ FIXED_IO_ddr_vrn => DDRVrxSNIO,
+ FIXED_IO_ddr_vrp => DDRVrxSPIO,
+ -- USB interface
+ Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO => Pll2V5DatauWirexSO,
+ Spi1SSxSO => Pll2V5LEuWirexSO,
+ Spi1SclkxCO => Pll2V5ClkuWirexCO,
+ -- MIO
+ FIXED_IO_mio => MIOxDIO,
+ -- GPIOs
+ GPIOSwitchesxDI => GPIOSwitchesxD,
+ GPIOResetBtnxRNO => SelfRstxRNO,
+ -- Firmware ID
+ IDAxixCO => IDAxixC,
+ IDAxixRO => IDAxixR,
+ IDAxixDO => IDAxiM2SxD,
+ IDAxixDI => IDAxiS2MxD);
+
+ end block PSxB;
+
+ PLxB : block is
+ begin -- block PLxB
+
+
+
+ end block PLxB;
+
+end arch;
diff --git a/design_files/scalp_zynqps.vhd b/design_files/scalp_zynqps.vhd
new file mode 100644
index 0000000..98ee6db
--- /dev/null
+++ b/design_files/scalp_zynqps.vhd
@@ -0,0 +1,177 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_zynqps_wrapper - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.2 xc7z015clg485-2
+-- Tool version: 2023.2
+-- Description: scalp_zynqps_wrapper
+--
+-- Last update: 2024-03-13
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- use ieee.std_logic_unsigned.all;
+-- use ieee.std_logic_arith.all;
+-- use ieee.std_logic_misc.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library axi_lib;
+use axi_lib.scalp_axi_pkg.all;
+
+entity scalp_zynqps_wrapper is
+
+ generic (
+ C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
+ C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
+ C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
+ C_GPIO_SWITCHES_SIZE : integer range 0 to 32 := 2);
+
+ port (
+ -- Processor interface
+ FIXED_IO_ps_clk : inout std_logic;
+ FIXED_IO_ps_porb : inout std_logic;
+ FIXED_IO_ps_srstb : inout std_logic;
+ Clk125xCO : out std_logic;
+ Clk125RstxRO : out std_logic;
+ Clk125RstxRNAO : out std_logic;
+ -- DDR interface
+ DDR_addr : inout std_logic_vector (14 downto 0);
+ DDR_ba : inout std_logic_vector (2 downto 0);
+ DDR_cas_n : inout std_logic;
+ DDR_ck_n : inout std_logic;
+ DDR_ck_p : inout std_logic;
+ DDR_cke : inout std_logic;
+ DDR_cs_n : inout std_logic;
+ DDR_dm : inout std_logic_vector (3 downto 0);
+ DDR_dq : inout std_logic_vector (31 downto 0);
+ DDR_dqs_n : inout std_logic_vector (3 downto 0);
+ DDR_dqs_p : inout std_logic_vector (3 downto 0);
+ DDR_odt : inout std_logic;
+ DDR_ras_n : inout std_logic;
+ DDR_reset_n : inout std_logic;
+ DDR_we_n : inout std_logic;
+ FIXED_IO_ddr_vrn : inout std_logic;
+ FIXED_IO_ddr_vrp : inout std_logic;
+ -- USB interface
+ Usb0VBusPwrFaultxSI : in std_logic;
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO : out std_logic;
+ Spi1SSxSO : out std_logic;
+ Spi1SclkxCO : out std_logic;
+ -- MIO
+ FIXED_IO_mio : inout std_logic_vector (53 downto 0);
+ -- GPIOs
+ GPIOSwitchesxDI : in std_logic_vector((C_GPIO_SWITCHES_SIZE - 1) downto 0);
+ GPIOResetBtnxRNO : out std_logic;
+ -- Scalp ID AXI interface + (clk and rst)
+ IDAxixCO : out t_axi_clk;
+ IDAxixRO : out t_axi_reset;
+ IDAxixDO : out t_axi_m2s;
+ IDAxixDI : in t_axi_s2m);
+
+end scalp_zynqps_wrapper;
+
+architecture arch of scalp_zynqps_wrapper is
+
+ -- Signals
+ signal IDAxixC : t_axi_clk := C_AXI_IDLE_CLK;
+ signal IDAxixR : t_axi_reset := C_AXI_IDLE_RESET;
+ signal IDAxiOutxD : t_axi_m2s := C_AXI_IDLE_M2S;
+ signal IDAxiInxD : t_axi_s2m := C_AXI_IDLE_S2M;
+ signal GPIOResetBtnxR : std_logic := '0';
+
+begin
+
+ PlatformxB : block is
+ begin -- block PlatformxB
+
+ IDAxiClkxAS : IDAxixCO <= IDAxixC;
+ IDAxiRstxAS : IDAxixRO <= IDAxixR;
+ IDAxiOutxAS : IDAxixDO <= IDAxiOutxD;
+ IDAxiInxAS : IDAxiInxD <= IDAxixDI;
+ GPIOResetBtnxAS : GPIOResetBtnxRNO <= not GPIOResetBtnxR;
+
+ ScalpZynqPSxI : entity work.scalp_zynqps
+ port map (
+ ---------------------------------------------------------------
+ -- DDR3 Interface
+ ---------------------------------------------------------------
+ DDR_addr => DDR_addr,
+ DDR_ba => DDR_ba,
+ DDR_cas_n => DDR_cas_n,
+ DDR_ck_n => DDR_ck_n,
+ DDR_ck_p => DDR_ck_p,
+ DDR_cke => DDR_cke,
+ DDR_cs_n => DDR_cs_n,
+ DDR_dm => DDR_dm,
+ DDR_dq => DDR_dq,
+ DDR_dqs_n => DDR_dqs_n,
+ DDR_dqs_p => DDR_dqs_p,
+ DDR_odt => DDR_odt,
+ DDR_ras_n => DDR_ras_n,
+ DDR_reset_n => DDR_reset_n,
+ DDR_we_n => DDR_we_n,
+ FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+ FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+ FIXED_IO_mio => FIXED_IO_mio,
+ FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+ FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+ FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+ Clk125xCO => Clk125xCO,
+ Clk125RstxRO(0) => Clk125RstxRO,
+ Clk125RstxRNAO(0) => Clk125RstxRNAO,
+ Spi1MOSIxSO => Spi1MOSIxSO,
+ Spi1SSxSO => Spi1SSxSO,
+ Spi1SclkxCO => Spi1SclkxCO,
+ Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
+ ---------------------------------------------------------------
+ -- GPIOs
+ ---------------------------------------------------------------
+ GPIOSwitchesxDI_tri_i((C_GPIO_SWITCHES_SIZE - 1) downto 0) => GPIOSwitchesxDI((C_GPIO_SWITCHES_SIZE - 1) downto 0),
+ GPIOResetBtnxDO_tri_o(0) => GPIOResetBtnxR,
+ ---------------------------------------------------------------
+ -- ID Axi Interface
+ ---------------------------------------------------------------
+ SAxiMstClkxCO => IDAxixC.ClkxC,
+ SAxiMstRstxRANO => IDAxixR.ResetxRAN,
+ aximm_mst_if_araddr => IDAxiOutxD.ARAddrxD,
+ aximm_mst_if_arready => IDAxiInxD.RdxD.ARReadyxS,
+ aximm_mst_if_arvalid => IDAxiOutxD.ARValidxS,
+ aximm_mst_if_awaddr => IDAxiOutxD.AWAddrxD,
+ aximm_mst_if_awready => IDAxiInxD.WrxD.AWReadyxS,
+ aximm_mst_if_awvalid => IDAxiOutxD.AWValidxS,
+ aximm_mst_if_bready => IDAxiOutxD.BReadyxS,
+ aximm_mst_if_bresp => IDAxiInxD.WrxD.BRespxD,
+ aximm_mst_if_bvalid => IDAxiInxD.WrxD.BValidxS,
+ aximm_mst_if_rdata => IDAxiInxD.RdxD.RDataxD,
+ aximm_mst_if_rready => IDAxiOutxD.RReadyxS,
+ aximm_mst_if_rresp => IDAxiInxD.RdxD.RRespxD,
+ aximm_mst_if_rvalid => IDAxiInxD.RdxD.RValidxS,
+ aximm_mst_if_wdata => IDAxiOutxD.WDataxD,
+ aximm_mst_if_wready => IDAxiInxD.WrxD.WReadyxS,
+ aximm_mst_if_wstrb => IDAxiOutxD.WStrbxD,
+ aximm_mst_if_wvalid => IDAxiOutxD.WValidxS);
+
+ end block PlatformxB;
+
+end arch;
diff --git a/design_files/scalp_zynqps_ipi.tcl b/design_files/scalp_zynqps_ipi.tcl
new file mode 100644
index 0000000..0fff7ce
--- /dev/null
+++ b/design_files/scalp_zynqps_ipi.tcl
@@ -0,0 +1,985 @@
+
+################################################################
+# This is a generated script based on design: scalp_zynqps
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2023.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
+
+ } else {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ }
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source scalp_zynqps_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+ create_project project_1 myproj -part xc7z015clg485-2
+ set_property BOARD_PART hepia-cores.ch:scalp_node:part0:0.2 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name scalp_zynqps
+
+# This script was generated for a remote BD. To create a non-remote design,
+# change the variable <run_remote_bd_flow> to <0>.
+
+set run_remote_bd_flow 1
+if { $run_remote_bd_flow == 1 } {
+ # Set the reference directory for source file relative paths (by default
+ # the value is script directory path)
+ set origin_dir .
+
+ # Use origin directory path location variable, if specified in the tcl shell
+ if { [info exists ::origin_dir_loc] } {
+ set origin_dir $::origin_dir_loc
+ }
+
+ set str_bd_folder [file normalize ${origin_dir}]
+ set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+
+ # Check if remote design exists on disk
+ if { [file exists $str_bd_filepath ] == 1 } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
+ common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
+ common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+
+ return 1
+ }
+
+ # Check if design exists in memory
+ set list_existing_designs [get_bd_designs -quiet $design_name]
+ if { $list_existing_designs ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+ common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+ return 1
+ }
+
+ # Check if design exists on disk within project
+ set list_existing_designs [get_files -quiet */${design_name}.bd]
+ if { $list_existing_designs ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
+ $list_existing_designs"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+ common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+ return 1
+ }
+
+ # Now can create the remote BD
+ # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
+ create_bd_design -dir $str_bd_folder $design_name
+} else {
+
+ # Create regular design
+ if { [catch {create_bd_design $design_name} errmsg] } {
+ common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+
+ return 1
+ }
+}
+
+current_bd_design $design_name
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+xilinx.com:ip:xlconstant:1.1\
+xilinx.com:ip:processing_system7:5.5\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:clk_wiz:6.0\
+hepia.hesge.ch:user:scalp_axi_link:1.0\
+xilinx.com:ip:axi_gpio:2.0\
+xilinx.com:ip:axi_intc:4.1\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:system_ila:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+ variable design_name
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+ set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+
+ set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+
+ set aximm_mst_if [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 aximm_mst_if ]
+ set_property -dict [ list \
+ CONFIG.ADDR_WIDTH {32} \
+ CONFIG.DATA_WIDTH {32} \
+ CONFIG.HAS_BURST {0} \
+ CONFIG.HAS_CACHE {0} \
+ CONFIG.HAS_LOCK {0} \
+ CONFIG.HAS_PROT {0} \
+ CONFIG.HAS_QOS {0} \
+ CONFIG.HAS_REGION {0} \
+ CONFIG.PROTOCOL {AXI4LITE} \
+ ] $aximm_mst_if
+
+ set GPIOSwitchesxDI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIOSwitchesxDI ]
+
+ set GPIOResetBtnxDO [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIOResetBtnxDO ]
+
+
+ # Create ports
+ set Clk125xCO [ create_bd_port -dir O -type clk Clk125xCO ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $Clk125xCO
+ set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
+ set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
+ set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
+ set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
+ set Clk125RstxRNAO [ create_bd_port -dir O -from 0 -to 0 -type rst Clk125RstxRNAO ]
+ set Clk125RstxRO [ create_bd_port -dir O -from 0 -to 0 -type rst Clk125RstxRO ]
+ set SAxiMstClkxCO [ create_bd_port -dir O -type clk SAxiMstClkxCO ]
+ set_property -dict [ list \
+ CONFIG.ASSOCIATED_BUSIF {aximm_mst_if} \
+ ] $SAxiMstClkxCO
+ set_property CONFIG.ASSOCIATED_BUSIF.VALUE_SRC DEFAULT $SAxiMstClkxCO
+
+ set SAxiMstRstxRANO [ create_bd_port -dir O -type rst SAxiMstRstxRANO ]
+
+ # Create instance: gnd_constant, and set properties
+ set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
+ set_property CONFIG.CONST_VAL {0} $gnd_constant
+
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {750.000000} \
+ CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
+ CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.204082} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {194.444443} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {134.615387} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {159.090912} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {97.222221} \
+ CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {750} \
+ CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
+ CONFIG.PCW_CAN1_CAN1_IO {MIO 52 .. 53} \
+ CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
+ CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
+ CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_CAN_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_CLK0_FREQ {125000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CORE0_FIQ_INTR {0} \
+ CONFIG.PCW_CORE0_IRQ_INTR {0} \
+ CONFIG.PCW_CORE1_FIQ_INTR {0} \
+ CONFIG.PCW_CORE1_IRQ_INTR {0} \
+ CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {767} \
+ CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
+ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
+ CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
+ CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x0FFFFFFF} \
+ CONFIG.PCW_DM_WIDTH {4} \
+ CONFIG.PCW_DQS_WIDTH {4} \
+ CONFIG.PCW_DQ_WIDTH {32} \
+ CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
+ CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
+ CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
+ CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
+ CONFIG.PCW_ENET0_RESET_ENABLE {0} \
+ CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_ENET_RESET_ENABLE {1} \
+ CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_EN_4K_TIMER {0} \
+ CONFIG.PCW_EN_CAN0 {0} \
+ CONFIG.PCW_EN_CAN1 {1} \
+ CONFIG.PCW_EN_CLK0_PORT {1} \
+ CONFIG.PCW_EN_CLK1_PORT {0} \
+ CONFIG.PCW_EN_CLK2_PORT {0} \
+ CONFIG.PCW_EN_CLK3_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
+ CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
+ CONFIG.PCW_EN_DDR {1} \
+ CONFIG.PCW_EN_EMIO_CAN0 {0} \
+ CONFIG.PCW_EN_EMIO_CAN1 {0} \
+ CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
+ CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_ENET0 {0} \
+ CONFIG.PCW_EN_EMIO_ENET1 {0} \
+ CONFIG.PCW_EN_EMIO_GPIO {0} \
+ CONFIG.PCW_EN_EMIO_I2C0 {0} \
+ CONFIG.PCW_EN_EMIO_I2C1 {0} \
+ CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
+ CONFIG.PCW_EN_EMIO_PJTAG {0} \
+ CONFIG.PCW_EN_EMIO_SDIO0 {0} \
+ CONFIG.PCW_EN_EMIO_SDIO1 {0} \
+ CONFIG.PCW_EN_EMIO_SPI0 {0} \
+ CONFIG.PCW_EN_EMIO_SPI1 {1} \
+ CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
+ CONFIG.PCW_EN_EMIO_TRACE {0} \
+ CONFIG.PCW_EN_EMIO_TTC0 {0} \
+ CONFIG.PCW_EN_EMIO_TTC1 {0} \
+ CONFIG.PCW_EN_EMIO_UART0 {0} \
+ CONFIG.PCW_EN_EMIO_UART1 {0} \
+ CONFIG.PCW_EN_EMIO_WDT {0} \
+ CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
+ CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
+ CONFIG.PCW_EN_ENET0 {1} \
+ CONFIG.PCW_EN_ENET1 {0} \
+ CONFIG.PCW_EN_GPIO {1} \
+ CONFIG.PCW_EN_I2C0 {1} \
+ CONFIG.PCW_EN_I2C1 {0} \
+ CONFIG.PCW_EN_MODEM_UART0 {0} \
+ CONFIG.PCW_EN_MODEM_UART1 {0} \
+ CONFIG.PCW_EN_PJTAG {0} \
+ CONFIG.PCW_EN_PTP_ENET0 {0} \
+ CONFIG.PCW_EN_PTP_ENET1 {0} \
+ CONFIG.PCW_EN_QSPI {1} \
+ CONFIG.PCW_EN_RST0_PORT {1} \
+ CONFIG.PCW_EN_RST1_PORT {0} \
+ CONFIG.PCW_EN_RST2_PORT {0} \
+ CONFIG.PCW_EN_RST3_PORT {0} \
+ CONFIG.PCW_EN_SDIO0 {0} \
+ CONFIG.PCW_EN_SDIO1 {1} \
+ CONFIG.PCW_EN_SMC {0} \
+ CONFIG.PCW_EN_SPI0 {1} \
+ CONFIG.PCW_EN_SPI1 {1} \
+ CONFIG.PCW_EN_TRACE {0} \
+ CONFIG.PCW_EN_TTC0 {0} \
+ CONFIG.PCW_EN_TTC1 {0} \
+ CONFIG.PCW_EN_UART0 {1} \
+ CONFIG.PCW_EN_UART1 {1} \
+ CONFIG.PCW_EN_USB0 {1} \
+ CONFIG.PCW_EN_USB1 {0} \
+ CONFIG.PCW_EN_WDT {0} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {125} \
+ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \
+ CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
+ CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
+ CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \
+ CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
+ CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
+ CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
+ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
+ CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
+ CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
+ CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
+ CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
+ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+ CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {125.000000} \
+ CONFIG.PCW_I2C_RESET_ENABLE {1} \
+ CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
+ CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
+ CONFIG.PCW_IRQ_F2P_INTR {1} \
+ CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
+ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_0_PULLUP {enabled} \
+ CONFIG.PCW_MIO_0_SLEW {slow} \
+ CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_10_PULLUP {enabled} \
+ CONFIG.PCW_MIO_10_SLEW {slow} \
+ CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_11_PULLUP {enabled} \
+ CONFIG.PCW_MIO_11_SLEW {slow} \
+ CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_12_PULLUP {enabled} \
+ CONFIG.PCW_MIO_12_SLEW {slow} \
+ CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_13_PULLUP {enabled} \
+ CONFIG.PCW_MIO_13_SLEW {slow} \
+ CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_14_PULLUP {enabled} \
+ CONFIG.PCW_MIO_14_SLEW {slow} \
+ CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_15_PULLUP {enabled} \
+ CONFIG.PCW_MIO_15_SLEW {slow} \
+ CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_16_PULLUP {enabled} \
+ CONFIG.PCW_MIO_16_SLEW {slow} \
+ CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_17_PULLUP {enabled} \
+ CONFIG.PCW_MIO_17_SLEW {slow} \
+ CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_18_PULLUP {enabled} \
+ CONFIG.PCW_MIO_18_SLEW {slow} \
+ CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_19_PULLUP {enabled} \
+ CONFIG.PCW_MIO_19_SLEW {slow} \
+ CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_1_PULLUP {enabled} \
+ CONFIG.PCW_MIO_1_SLEW {slow} \
+ CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_20_PULLUP {enabled} \
+ CONFIG.PCW_MIO_20_SLEW {slow} \
+ CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_21_PULLUP {enabled} \
+ CONFIG.PCW_MIO_21_SLEW {slow} \
+ CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_22_PULLUP {enabled} \
+ CONFIG.PCW_MIO_22_SLEW {slow} \
+ CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_23_PULLUP {enabled} \
+ CONFIG.PCW_MIO_23_SLEW {slow} \
+ CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_24_PULLUP {enabled} \
+ CONFIG.PCW_MIO_24_SLEW {slow} \
+ CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_25_PULLUP {enabled} \
+ CONFIG.PCW_MIO_25_SLEW {slow} \
+ CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_26_PULLUP {enabled} \
+ CONFIG.PCW_MIO_26_SLEW {slow} \
+ CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_27_PULLUP {enabled} \
+ CONFIG.PCW_MIO_27_SLEW {slow} \
+ CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_28_PULLUP {enabled} \
+ CONFIG.PCW_MIO_28_SLEW {slow} \
+ CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_29_PULLUP {enabled} \
+ CONFIG.PCW_MIO_29_SLEW {slow} \
+ CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_2_SLEW {slow} \
+ CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_30_PULLUP {enabled} \
+ CONFIG.PCW_MIO_30_SLEW {slow} \
+ CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_31_PULLUP {enabled} \
+ CONFIG.PCW_MIO_31_SLEW {slow} \
+ CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_32_PULLUP {enabled} \
+ CONFIG.PCW_MIO_32_SLEW {slow} \
+ CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_33_PULLUP {enabled} \
+ CONFIG.PCW_MIO_33_SLEW {slow} \
+ CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_34_PULLUP {enabled} \
+ CONFIG.PCW_MIO_34_SLEW {slow} \
+ CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_35_PULLUP {enabled} \
+ CONFIG.PCW_MIO_35_SLEW {slow} \
+ CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_36_PULLUP {enabled} \
+ CONFIG.PCW_MIO_36_SLEW {slow} \
+ CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_37_PULLUP {enabled} \
+ CONFIG.PCW_MIO_37_SLEW {slow} \
+ CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_38_PULLUP {enabled} \
+ CONFIG.PCW_MIO_38_SLEW {slow} \
+ CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_39_PULLUP {enabled} \
+ CONFIG.PCW_MIO_39_SLEW {slow} \
+ CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_3_SLEW {slow} \
+ CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_40_PULLUP {enabled} \
+ CONFIG.PCW_MIO_40_SLEW {slow} \
+ CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_41_PULLUP {enabled} \
+ CONFIG.PCW_MIO_41_SLEW {slow} \
+ CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_42_PULLUP {enabled} \
+ CONFIG.PCW_MIO_42_SLEW {slow} \
+ CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_43_PULLUP {enabled} \
+ CONFIG.PCW_MIO_43_SLEW {slow} \
+ CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_44_PULLUP {enabled} \
+ CONFIG.PCW_MIO_44_SLEW {slow} \
+ CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_45_PULLUP {enabled} \
+ CONFIG.PCW_MIO_45_SLEW {slow} \
+ CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_46_PULLUP {enabled} \
+ CONFIG.PCW_MIO_46_SLEW {slow} \
+ CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_47_PULLUP {enabled} \
+ CONFIG.PCW_MIO_47_SLEW {slow} \
+ CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_48_PULLUP {enabled} \
+ CONFIG.PCW_MIO_48_SLEW {slow} \
+ CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_49_PULLUP {enabled} \
+ CONFIG.PCW_MIO_49_SLEW {slow} \
+ CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_4_SLEW {slow} \
+ CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_50_PULLUP {enabled} \
+ CONFIG.PCW_MIO_50_SLEW {slow} \
+ CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_51_PULLUP {enabled} \
+ CONFIG.PCW_MIO_51_SLEW {slow} \
+ CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_52_PULLUP {enabled} \
+ CONFIG.PCW_MIO_52_SLEW {slow} \
+ CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 2.5V} \
+ CONFIG.PCW_MIO_53_PULLUP {enabled} \
+ CONFIG.PCW_MIO_53_SLEW {slow} \
+ CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_5_SLEW {slow} \
+ CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_6_SLEW {slow} \
+ CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_7_SLEW {slow} \
+ CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_8_SLEW {slow} \
+ CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
+ CONFIG.PCW_MIO_9_PULLUP {enabled} \
+ CONFIG.PCW_MIO_9_SLEW {slow} \
+ CONFIG.PCW_MIO_PRIMITIVE {54} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet\
+0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C\
+0#CAN 1#CAN 1} \
+ CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx}\
+\
+ CONFIG.PCW_NAND_CYCLES_T_AR {1} \
+ CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
+ CONFIG.PCW_NAND_CYCLES_T_RC {11} \
+ CONFIG.PCW_NAND_CYCLES_T_REA {1} \
+ CONFIG.PCW_NAND_CYCLES_T_RR {1} \
+ CONFIG.PCW_NAND_CYCLES_T_WC {11} \
+ CONFIG.PCW_NAND_CYCLES_T_WP {1} \
+ CONFIG.PCW_NOR_CS0_T_CEOE {1} \
+ CONFIG.PCW_NOR_CS0_T_PC {1} \
+ CONFIG.PCW_NOR_CS0_T_RC {11} \
+ CONFIG.PCW_NOR_CS0_T_TR {1} \
+ CONFIG.PCW_NOR_CS0_T_WC {11} \
+ CONFIG.PCW_NOR_CS0_T_WP {1} \
+ CONFIG.PCW_NOR_CS0_WE_TIME {0} \
+ CONFIG.PCW_NOR_CS1_T_CEOE {1} \
+ CONFIG.PCW_NOR_CS1_T_PC {1} \
+ CONFIG.PCW_NOR_CS1_T_RC {11} \
+ CONFIG.PCW_NOR_CS1_T_TR {1} \
+ CONFIG.PCW_NOR_CS1_T_WC {11} \
+ CONFIG.PCW_NOR_CS1_T_WP {1} \
+ CONFIG.PCW_NOR_CS1_WE_TIME {0} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
+ CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
+ CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
+ CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
+ CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
+ CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
+ CONFIG.PCW_P2F_CAN1_INTR {0} \
+ CONFIG.PCW_P2F_ENET0_INTR {0} \
+ CONFIG.PCW_P2F_GPIO_INTR {0} \
+ CONFIG.PCW_P2F_I2C0_INTR {0} \
+ CONFIG.PCW_P2F_QSPI_INTR {0} \
+ CONFIG.PCW_P2F_SDIO1_INTR {0} \
+ CONFIG.PCW_P2F_SPI0_INTR {0} \
+ CONFIG.PCW_P2F_SPI1_INTR {0} \
+ CONFIG.PCW_P2F_UART0_INTR {0} \
+ CONFIG.PCW_P2F_UART1_INTR {0} \
+ CONFIG.PCW_P2F_USB0_INTR {0} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.075} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.070} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.077} \
+ CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.094} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.000} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.001} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {0.004} \
+ CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.035} \
+ CONFIG.PCW_PACKAGE_NAME {clg485} \
+ CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
+ CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \
+ CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
+ CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
+ CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V} \
+ CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
+ CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+ CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
+ CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
+ CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {133} \
+ CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+ CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \
+ CONFIG.PCW_SD1_GRP_CD_IO {MIO 9} \
+ CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
+ CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
+ CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
+ CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
+ CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
+ CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
+ CONFIG.PCW_SMC_CYCLE_T0 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T1 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T2 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T3 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T4 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T5 {NA} \
+ CONFIG.PCW_SMC_CYCLE_T6 {NA} \
+ CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
+ CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
+ CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
+ CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
+ CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
+ CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SPI0_SPI0_IO {MIO 40 .. 45} \
+ CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
+ CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
+ CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
+ CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
+ CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
+ CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
+ CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
+ CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
+ CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
+ CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
+ CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
+ CONFIG.PCW_UART0_BAUD_RATE {115200} \
+ CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
+ CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47} \
+ CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
+ CONFIG.PCW_UART1_BAUD_RATE {115200} \
+ CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
+ CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
+ CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
+ CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {500.000000} \
+ CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
+ CONFIG.PCW_UIPARAM_DDR_AL {0} \
+ CONFIG.PCW_UIPARAM_DDR_BL {8} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {76.428} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {76.428} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {76.428} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {76.428} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {76.687} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {77.8025} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {72.8405} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {111.904} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \
+ CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {73.119} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.8935} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {77.045} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {111.903} \
+ CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
+ CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
+ CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
+ CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
+ CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
+ CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
+ CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
+ CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
+ CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
+ CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
+ CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_USB0_RESET_ENABLE {0} \
+ CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
+ CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
+ CONFIG.PCW_USB_RESET_ENABLE {1} \
+ CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
+ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
+ CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
+ CONFIG.PCW_USE_AXI_NONSECURE {0} \
+ CONFIG.PCW_USE_CORESIGHT {0} \
+ CONFIG.PCW_USE_CROSS_TRIGGER {0} \
+ CONFIG.PCW_USE_CR_FABRIC {1} \
+ CONFIG.PCW_USE_DDR_BYPASS {0} \
+ CONFIG.PCW_USE_DEBUG {0} \
+ CONFIG.PCW_USE_DMA0 {0} \
+ CONFIG.PCW_USE_DMA1 {0} \
+ CONFIG.PCW_USE_DMA2 {0} \
+ CONFIG.PCW_USE_DMA3 {0} \
+ CONFIG.PCW_USE_EXPANDED_IOP {0} \
+ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
+ CONFIG.PCW_USE_HIGH_OCM {0} \
+ CONFIG.PCW_USE_M_AXI_GP0 {1} \
+ CONFIG.PCW_USE_M_AXI_GP1 {0} \
+ CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
+ CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
+ CONFIG.PCW_USE_S_AXI_ACP {0} \
+ CONFIG.PCW_USE_S_AXI_GP0 {0} \
+ CONFIG.PCW_USE_S_AXI_GP1 {0} \
+ CONFIG.PCW_USE_S_AXI_HP0 {0} \
+ CONFIG.PCW_USE_S_AXI_HP1 {0} \
+ CONFIG.PCW_USE_S_AXI_HP2 {0} \
+ CONFIG.PCW_USE_S_AXI_HP3 {0} \
+ CONFIG.PCW_USE_TRACE {0} \
+ CONFIG.PCW_VALUE_SILVERSION {3} \
+ CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
+ CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
+ ] $processing_system7_0
+
+
+ # Create instance: rst_ps7_0_125M, and set properties
+ set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
+
+ # Create instance: sys_clock, and set properties
+ set sys_clock [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 sys_clock ]
+ set_property -dict [list \
+ CONFIG.CLKIN1_JITTER_PS {80.0} \
+ CONFIG.CLKOUT1_JITTER {124.615} \
+ CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100} \
+ CONFIG.CLKOUT1_USED {true} \
+ CONFIG.CLKOUT2_JITTER {119.348} \
+ CONFIG.CLKOUT2_PHASE_ERROR {96.948} \
+ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \
+ CONFIG.CLKOUT2_USED {true} \
+ CONFIG.CLKOUT3_JITTER {119.348} \
+ CONFIG.CLKOUT3_PHASE_ERROR {96.948} \
+ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {100.000} \
+ CONFIG.CLKOUT3_USED {false} \
+ CONFIG.CLKOUT4_JITTER {109.241} \
+ CONFIG.CLKOUT4_PHASE_ERROR {96.948} \
+ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {100.000} \
+ CONFIG.CLKOUT4_USED {false} \
+ CONFIG.CLK_OUT1_PORT {clk_100} \
+ CONFIG.CLK_OUT2_PORT {clk_125} \
+ CONFIG.CLK_OUT3_PORT {clk_out3} \
+ CONFIG.CLK_OUT4_PORT {clk_out4} \
+ CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
+ CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \
+ CONFIG.MMCM_CLKOUT1_DIVIDE {8} \
+ CONFIG.MMCM_CLKOUT2_DIVIDE {1} \
+ CONFIG.MMCM_CLKOUT3_DIVIDE {1} \
+ CONFIG.NUM_OUT_CLKS {2} \
+ CONFIG.PRIM_SOURCE {Global_buffer} \
+ CONFIG.RESET_PORT {resetn} \
+ CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ ] $sys_clock
+
+
+ # Create instance: scalp_axi_link_scalpid, and set properties
+ set scalp_axi_link_scalpid [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi_link:1.0 scalp_axi_link_scalpid ]
+
+ # Create instance: ps7_0_axi_periph, and set properties
+ set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
+ set_property CONFIG.NUM_MI {4} $ps7_0_axi_periph
+
+
+ # Create instance: axi_gpio_switches, and set properties
+ set axi_gpio_switches [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_switches ]
+ set_property -dict [list \
+ CONFIG.C_ALL_INPUTS {1} \
+ CONFIG.C_GPIO_WIDTH {2} \
+ CONFIG.C_INTERRUPT_PRESENT {1} \
+ ] $axi_gpio_switches
+
+
+ # Create instance: axi_intc_0, and set properties
+ set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
+ set_property CONFIG.C_IRQ_CONNECTION {1} $axi_intc_0
+
+
+ # Create instance: xlconcat_0, and set properties
+ set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+ set_property CONFIG.NUM_PORTS {1} $xlconcat_0
+
+
+ # Create instance: axi_gpio_reset_btn, and set properties
+ set axi_gpio_reset_btn [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_reset_btn ]
+ set_property -dict [list \
+ CONFIG.C_ALL_INPUTS {0} \
+ CONFIG.C_ALL_OUTPUTS {1} \
+ CONFIG.C_GPIO_WIDTH {1} \
+ CONFIG.C_INTERRUPT_PRESENT {0} \
+ ] $axi_gpio_reset_btn
+
+
+ # Create instance: system_ila_0, and set properties
+ set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
+ set_property -dict [list \
+ CONFIG.C_MON_TYPE {NATIVE} \
+ CONFIG.C_NUM_OF_PROBES {2} \
+ CONFIG.C_PROBE0_TYPE {0} \
+ CONFIG.C_PROBE1_TYPE {0} \
+ ] $system_ila_0
+
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports GPIOSwitchesxDI] [get_bd_intf_pins axi_gpio_switches/GPIO]
+ connect_bd_intf_net -intf_net axi_gpio_reset_btn_GPIO [get_bd_intf_ports GPIOResetBtnxDO] [get_bd_intf_pins axi_gpio_reset_btn/GPIO]
+ connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
+ connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+ connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi_link_scalpid/aximm_slv_if]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins axi_intc_0/s_axi]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins ps7_0_axi_periph/M02_AXI] [get_bd_intf_pins axi_gpio_switches/S_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins axi_gpio_reset_btn/S_AXI]
+ connect_bd_intf_net -intf_net scalp_axi_link_0_aximm_mst_if [get_bd_intf_ports aximm_mst_if] [get_bd_intf_pins scalp_axi_link_scalpid/aximm_mst_if]
+
+ # Create port connections
+ connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
+ connect_bd_net -net axi_gpio_0_ip2intc_irpt [get_bd_pins axi_gpio_switches/ip2intc_irpt] [get_bd_pins xlconcat_0/In0] [get_bd_pins system_ila_0/probe0]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets axi_gpio_0_ip2intc_irpt]
+ connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins system_ila_0/probe1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets axi_intc_0_irq]
+ connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins sys_clock/clk_in1]
+ connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins sys_clock/resetn]
+ connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_pins processing_system7_0/SPI1_MOSI_O] [get_bd_ports Spi1MOSIxSO]
+ connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_pins processing_system7_0/SPI1_SCLK_O] [get_bd_ports Spi1SclkxCO]
+ connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_pins processing_system7_0/SPI1_SS_O] [get_bd_ports Spi1SSxSO]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_ports Clk125RstxRNAO] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins scalp_axi_link_scalpid/SAxiSlvRstxRANI] [get_bd_pins axi_gpio_switches/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins axi_gpio_reset_btn/s_axi_aresetn]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_reset [get_bd_pins rst_ps7_0_125M/peripheral_reset] [get_bd_ports Clk125RstxRO]
+ connect_bd_net -net scalp_axi_link_0_SAxiMstClkxCO [get_bd_pins scalp_axi_link_scalpid/SAxiMstClkxCO] [get_bd_ports SAxiMstClkxCO]
+ connect_bd_net -net scalp_axi_link_0_SAxiMstRstxRANO [get_bd_pins scalp_axi_link_scalpid/SAxiMstRstxRANO] [get_bd_ports SAxiMstRstxRANO]
+ connect_bd_net -net sys_clock_clk_125 [get_bd_pins sys_clock/clk_125] [get_bd_ports Clk125xCO] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins scalp_axi_link_scalpid/SAxiSlvClkxCI] [get_bd_pins axi_gpio_switches/s_axi_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins axi_gpio_reset_btn/s_axi_aclk] [get_bd_pins system_ila_0/clk]
+ connect_bd_net -net sys_clock_locked [get_bd_pins sys_clock/locked] [get_bd_pins rst_ps7_0_125M/dcm_locked]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_intc_0/intr]
+
+ # Create address segments
+ assign_bd_address -offset 0x41200000 -range 0x00010000 -with_name SEG_axi_gpio_0_Reg -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_switches/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_gpio_reset_btn/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C00000 -range 0x00001000 -with_name SEG_scalp_axi_link_0_Reg -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi_link_scalpid/aximm_slv_if/Reg] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+ # Create PFM attributes
+ set_property PFM_NAME {hepia:scalp:scalp_zynq_safe_pltfm:1.0} [get_files [current_bd_design].bd]
+ set_property PFM.AXI_PORT {M_AXI_GP1 {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HP0 {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1 {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2 {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3 {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /processing_system7_0]
+ set_property PFM.CLOCK {clk_125 {id "2" is_default "true" proc_sys_reset "/rst_ps7_0_125M" status "fixed" freq_hz "125000000"}} [get_bd_cells /sys_clock]
+ set_property PFM.AXI_PORT {M04_AXI { memport "M_AXI_GP" sptag "" memory "" is_range "false" } M05_AXI { memport "M_AXI_GP" sptag "" memory "" is_range "false" } M06_AXI { memport "M_AXI_GP" sptag "" memory "" is_range "false" } M07_AXI { memport "M_AXI_GP" sptag "" memory "" is_range "false" } M08_AXI { memport "M_AXI_GP" sptag "" memory "" is_range "false" } } [get_bd_cells /ps7_0_axi_periph]
+
+
+ validate_bd_design
+ save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/design_files/timing_constraints.xdc b/design_files/timing_constraints.xdc
new file mode 100644
index 0000000..4ce41c8
--- /dev/null
+++ b/design_files/timing_constraints.xdc
@@ -0,0 +1,31 @@
+############################################################################
+# Timing constraints #
+############################################################################
+
+##### PS_CLK (125 MHz) #####
+create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
+
+##### GTP reference clocks (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk1xC]
+
+##### Clocks from PLLs (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Local}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Bottom}]
+
+##### Clocks from neighbours (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_East}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_West}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Bottom}]
+
+# Output delays
+#create_clock -name clk_125 -period 8.000 [get_nets sys_clock_clk_125]
+#set_output_delay 1.000 -clock [get_clocks clk_125] [get_ports Led12V5RxSO]
+#set_output_delay 1.000 -clock [get_clocks clk_125] [get_ports Led12V5RxSO]
+#set_output_delay 1.000 -clock [get_clocks clk_125] [get_ports Led12V5RxSO]
--
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