From 9cfe91a184e7d7f7424b4eff64cf5dacc6ecba93 Mon Sep 17 00:00:00 2001
From: iliya <iliya.saroukha@hes-so.ch>
Date: Wed, 20 Dec 2023 15:33:45 +0100
Subject: [PATCH] feat: ex1 seemingly finished
---
assembleur.s | 5 ++++-
macro.h | 31 +++++++++++++++++++++++++++++++
mpu_user_console_etu.c | 38 +++++++++++++++++++++++++++++++++++---
3 files changed, 70 insertions(+), 4 deletions(-)
create mode 100644 macro.h
diff --git a/assembleur.s b/assembleur.s
index 98c0be0..b2cbed7 100644
--- a/assembleur.s
+++ b/assembleur.s
@@ -11,7 +11,10 @@
switch_to_user_mode:
-
+ ldr r0, =user_stack
+ msr PSP, r0
+ mov r1, #1
+ msr CONTROL, r1
bx lr
diff --git a/macro.h b/macro.h
new file mode 100644
index 0000000..30581ec
--- /dev/null
+++ b/macro.h
@@ -0,0 +1,31 @@
+/*
+ * macro.h
+ *
+ * Created on: 20 Dec 2023
+ * Author: iliya
+ */
+
+#ifndef MACRO_H_
+#define MACRO_H_
+
+// Region enable bit
+#define REGION_ENABLE (0x1 << 0)
+
+// Memory region sizes
+#define SET_SIZE_512KB (0x12 << 1)
+#define SET_SIZE_32KB (0xE << 1)
+#define SET_SIZE_16KB (0xD << 1)
+
+// Access permission attribute
+#define BTEX_NORMAL_NOT_SHAREABLE (0x1 << 19)
+#define BTEX_NOT_SHAREABLE_DEVICE (0x2 << 19)
+
+// Access permission field
+#define RO (0x7 << 24)
+#define RW (0x3 << 24)
+#define RW_PRIV (0x1 << 24)
+#define RW_PRIV_R_UNPRIV (0x2 << 24)
+
+
+
+#endif /* MACRO_H_ */
diff --git a/mpu_user_console_etu.c b/mpu_user_console_etu.c
index 0397fdf..123bfe7 100644
--- a/mpu_user_console_etu.c
+++ b/mpu_user_console_etu.c
@@ -20,6 +20,7 @@
#include "globals.h"
#include "user_cmd.h"
#include "uart.h"
+#include "macro.h"
#define MMFAR *(unsigned *)0xE000ED34
@@ -31,8 +32,6 @@ void switch_to_user_mode();
void asm_test_fault();
void MemManage_Handler() {
- SCB->SHCSR |= (1 << 16);
- // Activez le MPU
}
void test_supervisor_mode() {
@@ -55,11 +54,44 @@ void test_user_mode() {
n = LPC_TIM0->TC; // not OK (privileged access only)
}
+
int main(void) {
// MPU configuration here...
+ // Region 0 (Flash)
+ MPU->RNR = 0;
+ MPU->RBAR = 0x00000000;
+ MPU->RASR = RO | BTEX_NORMAL_NOT_SHAREABLE | SET_SIZE_512KB | REGION_ENABLE;
+
+ // Region 1 (SRAM1)
+ MPU->RNR = 1;
+ MPU->RBAR = 0x10000000;
+ MPU->RASR = RW | BTEX_NORMAL_NOT_SHAREABLE | SET_SIZE_32KB | REGION_ENABLE;
+
+ // Region 2 (SRAM1)
+ MPU->RNR = 2;
+ MPU->RBAR = 0x2007C000;
+ MPU->RASR = RW_PRIV_R_UNPRIV | BTEX_NORMAL_NOT_SHAREABLE | SET_SIZE_32KB | REGION_ENABLE;
+
+ // Region 3 (GPIO)
+ MPU->RNR = 3;
+ MPU->RBAR = 0x2009C000;
+ MPU->RASR = RW_PRIV_R_UNPRIV | BTEX_NOT_SHAREABLE_DEVICE | SET_SIZE_16KB | REGION_ENABLE;
+
+ // Region 4 (périphériques dont timers)
+ MPU->RNR = 4;
+ MPU->RBAR = 0x40000000;
+ MPU->RASR = RW_PRIV | BTEX_NOT_SHAREABLE_DEVICE | SET_SIZE_32KB | REGION_ENABLE;
+
+ // Region 5 (UART)
+ MPU->RNR = 5;
+ MPU->RBAR = 0x4000C000;
+ MPU->RASR = RW | BTEX_NOT_SHAREABLE_DEVICE | SET_SIZE_16KB | REGION_ENABLE;
+
+ SCB->SHCSR |= (1 << 16);
+ MPU->CTRL |= 0x1 << 0;
// testing memory accesses in supervisor mode:
- test_supervisor_mode(); // to be removed after checking
+// test_supervisor_mode(); // to be removed after checking
user_start: user_stating_address = &&user_start;// save the address of the label 'user_start' (for exercise 2)
--
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