Updated the scalp_firmware project with packet control through an AXI Lite interface.

designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Cleanup Vitis SDK workspace directory
 #
-# Last update: 2021-05-17 08:38:48
+# Last update: 2021-05-21 08:30:39
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Generate Vitis workspace for software applications
 #
-# Last update: 2021-05-17 08:38:48
+# Last update: 2021-05-21 08:30:39
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script for re-creating Vitis workspace
 #
-# Last update: 2021-05-17 08:38:48
+# Last update: 2021-05-21 08:30:39
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Open the Vitis workspace
 #
-# Last update: 2021-05-17 08:38:48
+# Last update: 2021-05-21 08:30:39
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh

@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script creating aliases for Vitis workspace management scripts
 #
-# Last update: 2021-05-17 08:38:48
+# Last update: 2021-05-21 08:30:39
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h

@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: Software application
 --
--- Last update: 2021-05-17 08:38:48
+-- Last update: 2021-05-21 08:30:39
 --
 -----------------------------------------------------------------------------*/
 

designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c

@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: Software application
 --
--- Last update: 2021-05-17 08:38:48
+-- Last update: 2021-05-21 08:30:39
 --
 -----------------------------------------------------------------------------*/
 

ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci

@@ -108,7 +108,7 @@
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
-        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.gen/sources_1/ip/axis_data_fifo</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
         <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>

ips/hw/scalp_axis_fifo_wrapper/src/hdl/scalp_axis_fifo_wrapper.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_axis_fifo_wrapper - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_axis_fifo_wrapper
+--
+-- Last update: 2021-05-31
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_axis_fifo_wrapper is
+
+    port (
+        ClkxCI        : in  t_axi4_dual_clk;
+        ResetxRI      : in  t_axi4_rst;
+        RXM2SxDI      : in  t_axi4m2s;
+        RXS2MxSO      : out t_axi4s2m;
+        TXM2SxDO      : out t_axi4m2s;
+        TXS2MxSI      : in  t_axi4s2m;
+        FifoStatusxDO : out t_axi4fifo_status);
+
+end scalp_axis_fifo_wrapper;
+
+architecture arch of scalp_axis_fifo_wrapper is
+
+    component scalp_axis_fifo
+        port (
+            s_axis_aresetn     : in  std_logic;
+            s_axis_aclk        : in  std_logic;
+            s_axis_tvalid      : in  std_logic;
+            s_axis_tready      : out std_logic;
+            s_axis_tdata       : in  std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+            s_axis_tstrb       : in  std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0);
+            s_axis_tkeep       : in  std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
+            s_axis_tlast       : in  std_logic;
+            s_axis_tid         : in  std_logic_vector(0 downto 0);
+            s_axis_tdest       : in  std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0);
+            s_axis_tuser       : in  std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0);
+            m_axis_aclk        : in  std_logic;
+            m_axis_tvalid      : out std_logic;
+            m_axis_tready      : in  std_logic;
+            m_axis_tdata       : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+            m_axis_tstrb       : out std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0);
+            m_axis_tkeep       : out std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
+            m_axis_tlast       : out std_logic;
+            m_axis_tid         : out std_logic_vector(0 downto 0);
+            m_axis_tdest       : out std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0);
+            m_axis_tuser       : out std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0);
+            axis_wr_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+            axis_rd_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+            prog_full          : out std_logic);
+    end component;
+
+begin  -- architecture arch
+
+    ScalpAxisFifoCorexI : entity work.scalp_axis_fifo
+        port map (
+            s_axis_aresetn     => ResetxRI.RstxRAN,
+            s_axis_aclk        => ClkxCI.RXClkxC,
+            s_axis_tvalid      => RXM2SxDI.ValidxS,
+            s_axis_tready      => RXS2MxSO.ReadyxS,
+            s_axis_tdata       => RXM2SxDI.DataxD,
+            s_axis_tstrb       => RXM2SxDI.StrbxD,
+            s_axis_tkeep       => RXM2SxDI.KeepxD,
+            s_axis_tlast       => RXM2SxDI.LastxS,
+            s_axis_tid(0)      => RXM2SxDI.IdxS,
+            s_axis_tdest       => RXM2SxDI.DestxD,
+            s_axis_tuser       => RXM2SxDI.UserxD,
+            m_axis_aclk        => ClkxCI.TXClkxC,
+            m_axis_tvalid      => TXM2SxDO.ValidxS,
+            m_axis_tready      => TXS2MxSI.ReadyxS,
+            m_axis_tdata       => TXM2SxDO.DataxD,
+            m_axis_tstrb       => TXM2SxDO.StrbxD,
+            m_axis_tkeep       => TXM2SxDO.KeepxD,
+            m_axis_tlast       => TXM2SxDO.LastxS,
+            m_axis_tid(0)      => TXM2SxDO.IdxS,
+            m_axis_tdest       => TXM2SxDO.DestxD,
+            m_axis_tuser       => TXM2SxDO.UserxD,
+            axis_wr_data_count => FifoStatusxDO.WrDataCntxD,
+            axis_rd_data_count => FifoStatusxDO.RdDataCntxD,
+            prog_full          => FifoStatusxDO.ProgFullxS);
+
+end architecture arch;

ips/hw/scalp_axis_fifo_wrapper/src/sim/tb_scalp_axis_fifo_wrapper.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_axis_fifo_wrapper - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_axis_fifo_wrapper
+--
+-- Last update: 2021-05-21 08:14:52
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_axis_fifo_wrapper is
+end tb_scalp_axis_fifo_wrapper;
+
+
+architecture behavioral of tb_scalp_axis_fifo_wrapper is
+
+begin
+
+end behavioral;

ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd

@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: scalp_packet_fifo_wrapper
 --
--- Last update: 2020-11-08
+-- Last update: 2021-05-21
 --
 ---------------------------------------------------------------------------------
 
@@ -25,6 +25,9 @@ use ieee.numeric_std.all;
 
 use work.axi4_pkg.all;
 
+library unisim;
+use unisim.vcomponents.all;
+
 entity scalp_packet_fifo_wrapper is
 
     port (

ips/hw/scalp_router/src/hdl/scalp_misc.vhd

@@ -15,7 +15,7 @@
 -- Tool version: 2018.2
 -- Description: Scalp Miscellanous
 --
--- Last update: 2021-05-18
+-- Last update: 2021-06-07
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -297,6 +297,60 @@ package scalp_misc is
         DataxD : std_logic_vector)
         return integer;
 
+    ---------------------------------------------------------------------------
+
+    -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian).
+    function scalp_sp_h0_to_axis_ul (
+        SpDstAddrXxD : std_ulogic_vector;
+        SpDstAddrYxD : std_ulogic_vector;
+        SpDstAddrZxD : std_ulogic_vector;
+        SpTypexD     : std_ulogic_vector)
+        return std_ulogic_vector;
+
+    -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian).
+    function scalp_sp_h0_to_axis (
+        SpDstAddrXxD : std_ulogic_vector;
+        SpDstAddrYxD : std_ulogic_vector;
+        SpDstAddrZxD : std_ulogic_vector;
+        SpTypexD     : std_ulogic_vector)
+        return std_logic_vector;
+
+    -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian).
+    function scalp_sp_h1_to_axis_ul (
+        SpSrcAddrXxD : std_ulogic_vector;
+        SpSrcAddrYxD : std_ulogic_vector;
+        SpSrcAddrZxD : std_ulogic_vector)
+        return std_ulogic_vector;
+
+    -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian).
+    function scalp_sp_h1_to_axis (
+        SpSrcAddrXxD : std_ulogic_vector;
+        SpSrcAddrYxD : std_ulogic_vector;
+        SpSrcAddrZxD : std_ulogic_vector)
+        return std_logic_vector;
+
+    -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian).
+    function scalp_sp_h2_to_axis_ul (
+        SpPldSizexD : std_ulogic_vector)
+        return std_ulogic_vector;
+
+    -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian).
+    function scalp_sp_h2_to_axis (
+        SpPldSizexD : std_ulogic_vector)
+        return std_logic_vector;
+
+    -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian).
+    function scalp_sp_p_to_axis_ul (
+        SpPayloadxD : std_ulogic_vector)
+        return std_ulogic_vector;
+
+    -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian).
+    function scalp_sp_p_to_axis (
+        SpPayloadxD : std_ulogic_vector)
+        return std_logic_vector;
+
+    ---------------------------------------------------------------------------
+
     -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian).
     function scalp_sp_header_h0_to_axis_ul (
         SpHeaderxD : t_scalp_packet_header)
@@ -567,6 +621,124 @@ package body scalp_misc is
         return std_logic_vector(scalp_peek_pld_ul(std_ulogic_vector(DataxD)));
     end function scalp_peek_pld;
 
+    ---------------------------------------------------------------------------
+
+    -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian).
+    function scalp_sp_h0_to_axis_ul (
+        SpDstAddrXxD : std_ulogic_vector;
+        SpDstAddrYxD : std_ulogic_vector;
+        SpDstAddrZxD : std_ulogic_vector;
+        SpTypexD     : std_ulogic_vector)
+        return std_ulogic_vector is
+        variable H0xD             : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1))     := (others => '0');
+        variable H0LittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0');
+        variable DstAddrXxD       : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+        variable DstAddrYxD       : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+        variable DstAddrZxD       : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+        variable TypexD           : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+    begin
+        DstAddrXxD       := std_ulogic_vector(SpDstAddrXxD(SpDstAddrXxD'left to SpDstAddrXxD'right));
+        DstAddrYxD       := std_ulogic_vector(SpDstAddrYxD(SpDstAddrYxD'left to SpDstAddrYxD'right));
+        DstAddrZxD       := std_ulogic_vector(SpDstAddrZxD(SpDstAddrZxD'left to SpDstAddrZxD'right));
+        TypexD           := std_ulogic_vector(SpTypexD(SpTypexD'left to SpTypexD'right));
+        H0LittleEndianxD := DstAddrXxD & DstAddrYxD & DstAddrZxD & TypexD;
+        H0xD             := change_endian_ul(H0LittleEndianxD);
+        return H0xD;
+    end function scalp_sp_h0_to_axis_ul;
+
+    -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian).
+    function scalp_sp_h0_to_axis (
+        SpDstAddrXxD : std_ulogic_vector;
+        SpDstAddrYxD : std_ulogic_vector;
+        SpDstAddrZxD : std_ulogic_vector;
+        SpTypexD     : std_ulogic_vector)
+        return std_logic_vector is
+    begin
+        return std_logic_vector(scalp_sp_h0_to_axis_ul(SpDstAddrXxD(SpDstAddrXxD'left to SpDstAddrXxD'right),
+                                                       SpDstAddrYxD(SpDstAddrYxD'left to SpDstAddrYxD'right),
+                                                       SpDstAddrZxD(SpDstAddrZxD'left to SpDstAddrZxD'right),
+                                                       SpTypexD(SpTypexD'left to SpTypexD'right)));
+    end function scalp_sp_h0_to_axis;
+
+    -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian).
+    function scalp_sp_h1_to_axis_ul (
+        SpSrcAddrXxD : std_ulogic_vector;
+        SpSrcAddrYxD : std_ulogic_vector;
+        SpSrcAddrZxD : std_ulogic_vector)
+        return std_ulogic_vector is
+        variable H1xD             : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1))     := (others => '0');
+        variable H1LittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0');
+        variable SrcAddrXxD       : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+        variable SrcAddrYxD       : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+        variable SrcAddrZxD       : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+        variable PadxD            : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0)       := (others => '0');
+    begin
+        SrcAddrXxD       := std_ulogic_vector(SpSrcAddrXxD(SpSrcAddrXxD'left to SpSrcAddrXxD'right));
+        SrcAddrYxD       := std_ulogic_vector(SpSrcAddrYxD(SpSrcAddrYxD'left to SpSrcAddrYxD'right));
+        SrcAddrZxD       := std_ulogic_vector(SpSrcAddrZxD(SpSrcAddrZxD'left to SpSrcAddrZxD'right));
+        -- 31 downto 0
+        H1LittleEndianxD := SrcAddrXxD & SrcAddrYxD & SrcAddrZxD & PadxD;
+        H1xD             := change_endian_ul(H1LittleEndianxD);
+        return H1xD;
+    end function scalp_sp_h1_to_axis_ul;
+
+    -- Fonction de conversion Scalp Packet Header H1 vers Axis (big endian).
+    function scalp_sp_h1_to_axis (
+        SpSrcAddrXxD : std_ulogic_vector;
+        SpSrcAddrYxD : std_ulogic_vector;
+        SpSrcAddrZxD : std_ulogic_vector)
+        return std_logic_vector is
+    begin
+        return std_logic_vector(scalp_sp_h1_to_axis_ul(SpSrcAddrXxD(SpSrcAddrXxD'left to SpSrcAddrXxD'right),
+                                                       SpSrcAddrYxD(SpSrcAddrYxD'left to SpSrcAddrYxD'right),
+                                                       SpSrcAddrZxD(SpSrcAddrZxD'left to SpSrcAddrZxD'right)));
+    end function scalp_sp_h1_to_axis;
+
+    -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian).
+    function scalp_sp_h2_to_axis_ul (
+        SpPldSizexD : std_ulogic_vector)
+        return std_ulogic_vector is
+        variable H2xD             : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1))     := (others => '0');
+        variable H2LittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0');
+        variable PldSizexD        : std_ulogic_vector(((C_BYTE_SIZE * 2) - 1) downto 0) := (others => '0');
+        variable PadxD            : std_ulogic_vector(((C_BYTE_SIZE * 2) - 1) downto 0) := (others => '0');
+    begin
+        PldSizexD        := std_ulogic_vector(SpPldSizexD(SpPldSizexD'left to SpPldSizexD'right));
+        H2LittleEndianxD := PldSizexD & PadxD;
+        H2xD             := change_endian_ul(H2LittleEndianxD);
+        return H2xD;
+    end function scalp_sp_h2_to_axis_ul;
+
+    -- Fonction de conversion Scalp Packet Header H2 vers Axis (big endian).
+    function scalp_sp_h2_to_axis (
+        SpPldSizexD : std_ulogic_vector)
+        return std_logic_vector is
+    begin
+        return std_logic_vector(scalp_sp_h2_to_axis_ul(SpPldSizexD(SpPldSizexD'left to SpPldSizexD'right)));
+    end function scalp_sp_h2_to_axis;
+
+    -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian).
+    function scalp_sp_p_to_axis_ul (
+        SpPayloadxD : std_ulogic_vector)
+        return std_ulogic_vector is
+        variable PxD             : std_ulogic_vector(0 to ((C_BYTE_SIZE * 4) - 1))     := (others => '0');
+        variable PLittleEndianxD : std_ulogic_vector(((C_BYTE_SIZE * 4) - 1) downto 0) := (others => '0');
+    begin
+        PLittleEndianxD := SpPayloadxD(SpPayloadxD'left to SpPayloadxD'right);
+        PxD             := change_endian_ul(PLittleEndianxD);
+        return PxD;
+    end function scalp_sp_p_to_axis_ul;
+
+    -- Fonction de conversion Scalp Packet Payload P vers Axis (big endian).
+    function scalp_sp_p_to_axis (
+        SpPayloadxD : std_ulogic_vector)
+        return std_logic_vector is
+    begin
+        return std_logic_vector(scalp_sp_p_to_axis_ul(SpPayloadxD(SpPayloadxD'left to SpPayloadxD'right)));
+    end function scalp_sp_p_to_axis;
+
+    ---------------------------------------------------------------------------
+
     -- Fonction de conversion Scalp Packet Header H0 vers Axis (big endian).
     function scalp_sp_header_h0_to_axis_ul (
         SpHeaderxD : t_scalp_packet_header)

ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd

+-- THIS IS AN AUTOGENERATED FILE. DO NOT EDIT THIS FILE DIRECTLY.
+-- scalp_regedit v0.1 - 05.2021
+-- Author : Joachim Schmidt <joachim.schmidt@hesge.ch>
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_misc.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_router_regbank is
+
+    generic (
+        C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
+        C_AXI4_RDATA_SIZE  : integer range 0 to 32 := 32;
+        C_AXI4_RRESP_SIZE  : integer range 0 to 2  := 2;
+        C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
+        C_AXI4_WDATA_SIZE  : integer range 0 to 32 := 32;
+        C_AXI4_WSTRB_SIZE  : integer range 0 to 4  := 4;
+        C_AXI4_BRESP_SIZE  : integer range 0 to 2  := 2;
+        C_AXI4_ADDR_SIZE   : integer range 0 to 32 := 12;
+        C_AXI4_DATA_SIZE   : integer range 0 to 32 := 32);
+
+    port (
+        -- Clock and reset
+        SAxiClkxCI              : in  std_ulogic;
+        SAxiRstxRANI            : in  std_ulogic;
+        -- AXI4 Lite
+        -- Read Channel
+        -- Read Address Channel
+        SAxiARAddrxDI           : in  std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
+        SAxiARValidxSI          : in  std_ulogic;
+        SAxiARReadyxSO          : out std_ulogic;
+        -- Read Data Channel
+        SAxiRDataxDO            : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
+        SAxiRRespxDO            : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
+        SAxiRValidxSO           : out std_ulogic;
+        SAxiRReadyxSI           : in  std_ulogic;
+        -- Write Channel
+        -- Write Address Channel
+        SAxiAWAddrxDI           : in  std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
+        SAxiAWValidxSI          : in  std_ulogic;
+        SAxiAWReadyxSO          : out std_ulogic;
+        -- Write Data Channel
+        SAxiWDataxDI            : in  std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
+        SAxiWStrbxDI            : in  std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
+        SAxiWValidxSI           : in  std_ulogic;
+        SAxiWReadyxSO           : out std_ulogic;
+        -- Write Response Channel
+        SAxiBRespxDO            : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
+        SAxiBValidxSO           : out std_ulogic;
+        SAxiBReadyxSI           : in  std_ulogic;
+        -- Registers list IO
+        ScalpPacketWriteDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        ScalpPacketReadDataxDI  : in  std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        ScalpPacketCtrlxDO      : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        ScalpPacketStatusxDI    : in  std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        TXWrDataCntxDI          : in  std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        TXRdDataCntxDI          : in  std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        RXWrDataCntxDI          : in  std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        RXRdDataCntxDI          : in  std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+        LocNetAddrxDO           : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
+
+end scalp_router_regbank;
+
+architecture behavioral of scalp_router_regbank is
+
+    -- Constants
+    constant C_AXI4_RRESP_OKAY   : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
+    constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
+    constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
+    constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
+    constant C_AXI4_BRESP_OKAY   : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
+    constant C_AXI4_BRESP_EXOKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
+    constant C_AXI4_BRESP_SLVERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
+    constant C_AXI4_BRESP_DECERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
+
+    -- Signals
+    -- Clock and reset
+    signal SAxiClkxC                   : std_ulogic                                         := '0';
+    signal SAxiRstxRAN                 : std_ulogic                                         := '0';
+    -- AXI4 Lite
+    signal SAxiARReadyxS               : std_ulogic                                         := '0';
+    signal SAxiRValidxS                : std_ulogic                                         := '0';
+    signal SAxiBValidxS                : std_ulogic                                         := '0';
+    signal SAxiWReadyxS                : std_ulogic                                         := '0';
+    signal SAxiAWReadyxS               : std_ulogic                                         := '0';
+    signal WrAddrxDN                   : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+    signal WrAddrxDP                   : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+    -- Signals of access to the register bank
+    signal RdAddrxD                    : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+    signal RdDataxD                    : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    signal RdValidxS                   : std_ulogic                                         := '0';
+    signal WrAddrxD                    : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+    signal WrDataxD                    : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    signal WrValidxS                   : std_ulogic                                         := '0';
+    -- Registers list
+    signal ScalpPacketWriteDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketWriteDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketReadDataPortxDN  : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketReadDataPortxDP  : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketCtrlPortxDN      : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketCtrlPortxDP      : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketStatusPortxDN    : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal ScalpPacketStatusPortxDP    : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal TXWrDataCntPortxDN          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal TXWrDataCntPortxDP          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal TXRdDataCntPortxDN          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal TXRdDataCntPortxDP          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal RXWrDataCntPortxDN          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal RXWrDataCntPortxDP          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal RXRdDataCntPortxDN          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal RXRdDataCntPortxDP          : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal LocNetAddrPortxDN           : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+    signal LocNetAddrPortxDP           : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+
+begin
+
+    assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
+        report "RDATA and DATA vectors must be the same" severity failure;
+
+    assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
+        report "ARADDR and ADDR vectors must be the same" severity failure;
+
+    assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
+        report "WDATA and DATA vectors must be the same" severity failure;
+
+    assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
+        report "AWADDR and ADDR vectors must be the same" severity failure;
+
+    EntityIOxB : block is
+    begin  -- block EntityIOxB
+
+        -- Clock and reset
+        SAxiClkxAS     : SAxiClkxC                                  <= SAxiClkxCI;
+        SAxiRstxAS     : SAxiRstxRAN                                <= SAxiRstxRANI;
+        -- Read Channel
+        SAxiARReadyxAS : SAxiARReadyxSO                             <= SAxiARReadyxS;
+        SAxiRValidxAS  : SAxiRValidxSO                              <= SAxiRValidxS;
+        SAxiRDataxAS   : SAxiRDataxDO                               <= RdDataxD;
+        RdValidxAS     : RdValidxS                                  <= SAxiARValidxSI;
+        RdAddrxAS      : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0)  <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
+        SAxiRRespxAS   : SAxiRRespxDO                               <= C_AXI4_RRESP_OKAY;
+        -- Write Channel
+        SAxiBRespxAS   : SAxiBRespxDO                               <= C_AXI4_BRESP_OKAY;
+        SAxiBValidxAS  : SAxiBValidxSO                              <= SAxiBValidxS;
+        SAxiWReadyxAS  : SAxiWReadyxSO                              <= SAxiWReadyxS;
+        SAxiAWReadyxAS : SAxiAWReadyxSO                             <= SAxiAWReadyxS;
+        WrValidxAS     : WrValidxS                                  <= SAxiWValidxSI;
+        WrDataxAS      : WrDataxD                                   <= SAxiWDataxDI;
+        WrAddrOutxAS   : WrAddrxD                                   <= WrAddrxDP;
+        WrAddrxAS      : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
+                                                                  SAxiAWValidxSI = '1' else
+                                                                  WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
+
+    end block EntityIOxB;
+
+    AXI4LitexB : block is
+    begin  -- block AXI4LitexB
+
+        ReadChannelxB : block is
+        begin  -- block ReadChannelxB
+
+            ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+
+                variable StateAfterResetxS : boolean := true;
+
+            begin  -- process ReadAddrChanxP
+                if SAxiRstxRAN = '0' then
+                    SAxiARReadyxS     <= '0';
+                    StateAfterResetxS := true;
+                elsif rising_edge(SAxiClkxC) then
+                    if StateAfterResetxS = true then
+                        SAxiARReadyxS     <= '1';
+                        StateAfterResetxS := false;
+                    else
+                        SAxiARReadyxS <= SAxiARReadyxS;
+                    end if;
+
+                    if SAxiARValidxSI = '1' then
+                        SAxiARReadyxS <= '0';
+                    end if;
+
+                    if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
+                        SAxiARReadyxS <= '1';
+                    end if;
+                end if;
+            end process ReadAddrChanxP;
+
+            ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+            begin  -- process ReadDataChanxP
+                if SAxiRstxRAN = '0' then
+                    SAxiRValidxS <= '0';
+                elsif rising_edge(SAxiClkxC) then
+                    SAxiRValidxS <= SAxiRValidxS;
+
+                    if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
+                        SAxiRValidxS <= '1';
+                    end if;
+
+                    if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
+                        SAxiRValidxS <= '0';
+                    end if;
+                end if;
+            end process ReadDataChanxP;
+
+        end block ReadChannelxB;
+
+        WriteChannelxB : block is
+        begin  --block WriteChannelxB        
+
+            WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is
+            begin  -- process WrAddrRegxP
+                if SAxiRstxRAN = '0' then
+                    WrAddrxDP <= (others => '0');
+                elsif rising_edge(SAxiClkxC) then
+                    WrAddrxDP <= WrAddrxDN;
+                end if;
+            end process WrAddrRegxP;
+
+            WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+
+                variable StateAfterResetxS : boolean := true;
+
+            begin  -- process WriteAddrChanxP
+                if SAxiRstxRAN = '0' then
+                    SAxiAWReadyxS     <= '0';
+                    StateAfterResetxS := true;
+                elsif rising_edge(SAxiClkxC) then
+                    if StateAfterResetxS = true then
+                        SAxiAWReadyxS     <= '1';
+                        StateAfterResetxS := false;
+                    else
+                        SAxiAWReadyxS <= SAxiAWReadyxS;
+                    end if;
+
+                    if SAxiAWValidxSI = '1' then
+                        SAxiAWReadyxS <= '0';
+                    end if;
+
+                    if SAxiWValidxSI = '1' then
+                        SAxiAWReadyxS <= '1';
+                    end if;
+                end if;
+            end process WriteAddrChanxP;
+
+            WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+            begin  -- process WriteDataChanxP
+                if SAxiRstxRAN = '0' then
+                    SAxiWReadyxS <= '0';
+                elsif rising_edge(SAxiClkxC) then
+                    SAxiWReadyxS <= SAxiWReadyxS;
+
+                    if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
+                        SAxiWReadyxS <= '1';
+                    end if;
+
+                    if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
+                        SAxiWReadyxS <= '0';
+                    end if;
+                end if;
+            end process WriteDataChanxP;
+
+            WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+            begin  -- process WriteRespChanxP
+                if SAxiRstxRAN = '0' then
+                    SAxiBValidxS <= '0';
+                elsif rising_edge(SAxiClkxC) then
+                    SAxiBValidxS <= SAxiBValidxS;
+
+                    if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
+                        SAxiBValidxS <= '1';
+                    end if;
+
+                    if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
+                        SAxiBValidxS <= '0';
+                    end if;
+                end if;
+            end process WriteRespChanxP;
+
+        end block WriteChannelxB;
+
+    end block AXI4LitexB;
+
+    ScalpRouterRegBankxB : block is
+    begin  -- block ScalpRouterRegBankxB
+
+        WriteRegPortxP : process (LocNetAddrPortxDP, RXRdDataCntxDI,
+                                  RXWrDataCntxDI, ScalpPacketCtrlPortxDP,
+                                  ScalpPacketReadDataxDI, ScalpPacketStatusxDI,
+                                  ScalpPacketWriteDataPortxDP, TXRdDataCntxDI,
+                                  TXWrDataCntxDI, WrAddrxD, WrDataxD,
+                                  WrValidxS) is
+        begin  -- process WriteRegPortxP
+            ScalpPacketWriteDataPortxDN <= ScalpPacketWriteDataPortxDP;
+            ScalpPacketReadDataPortxDN  <= ScalpPacketReadDataxDI;
+            ScalpPacketCtrlPortxDN      <= ScalpPacketCtrlPortxDP;
+            ScalpPacketStatusPortxDN    <= ScalpPacketStatusxDI;
+            TXWrDataCntPortxDN          <= TXWrDataCntxDI;
+            TXRdDataCntPortxDN          <= TXRdDataCntxDI;
+            RXWrDataCntPortxDN          <= RXWrDataCntxDI;
+            RXRdDataCntPortxDN          <= RXRdDataCntxDI;
+            LocNetAddrPortxDN           <= LocNetAddrPortxDP;
+
+            if WrValidxS = '1' then
+                case WrAddrxD is
+                    when x"000" => ScalpPacketWriteDataPortxDN <= WrDataxD;
+                    when x"008" => ScalpPacketCtrlPortxDN      <= WrDataxD;
+                    when x"00C" => ScalpPacketCtrlPortxDN      <= ScalpPacketCtrlPortxDP or WrDataxD;
+                    when x"010" => ScalpPacketCtrlPortxDN      <= ScalpPacketCtrlPortxDP and not WrDataxD;
+                    when x"028" => LocNetAddrPortxDN           <= WrDataxD;
+
+                    when others => null;
+                end case;
+            end if;
+        end process WriteRegPortxP;
+
+        ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
+        begin  -- process ReadRegPortxP
+            if SAxiRstxRAN = '0' then
+                RdDataxD <= (others => '0');
+            elsif rising_edge(SAxiClkxC) then
+                RdDataxD <= (others => '0');
+
+                if RdValidxS = '1' then
+                    case RdAddrxD is
+                        when x"000" => RdDataxD <= ScalpPacketWriteDataPortxDP;
+                        when x"004" => RdDataxD <= ScalpPacketReadDataPortxDP;
+                        when x"014" => RdDataxD <= ScalpPacketStatusPortxDP;
+                        when x"018" => RdDataxD <= TXWrDataCntPortxDP;
+                        when x"01C" => RdDataxD <= TXRdDataCntPortxDP;
+                        when x"020" => RdDataxD <= RXWrDataCntPortxDP;
+                        when x"024" => RdDataxD <= RXRdDataCntPortxDP;
+                        when x"028" => RdDataxD <= LocNetAddrPortxDP;
+
+                        when others => RdDataxD <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end process ReadRegPortxP;
+
+        UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is
+        begin  -- process UpdateRegBankxP
+            if SAxiRstxRAN = '0' then
+                ScalpPacketWriteDataPortxDP <= x"00000000";
+                ScalpPacketReadDataPortxDP  <= x"00000000";
+                ScalpPacketCtrlPortxDP      <= x"00000000";
+                ScalpPacketStatusPortxDP    <= x"00000000";
+                TXWrDataCntPortxDP          <= x"00000000";
+                TXRdDataCntPortxDP          <= x"00000000";
+                RXWrDataCntPortxDP          <= x"00000000";
+                RXRdDataCntPortxDP          <= x"00000000";
+                LocNetAddrPortxDP           <= x"00000000";
+
+            elsif rising_edge(SAxiClkxC) then
+                ScalpPacketWriteDataPortxDP <= ScalpPacketWriteDataPortxDN;
+                ScalpPacketReadDataPortxDP  <= ScalpPacketReadDataPortxDN;
+                ScalpPacketCtrlPortxDP      <= ScalpPacketCtrlPortxDN;
+                ScalpPacketStatusPortxDP    <= ScalpPacketStatusPortxDN;
+                TXWrDataCntPortxDP          <= TXWrDataCntPortxDN;
+                TXRdDataCntPortxDP          <= TXRdDataCntPortxDN;
+                RXWrDataCntPortxDP          <= RXWrDataCntPortxDN;
+                RXRdDataCntPortxDP          <= RXRdDataCntPortxDN;
+                LocNetAddrPortxDP           <= LocNetAddrPortxDN;
+
+            end if;
+        end process UpdateRegBankxP;
+
+    end block ScalpRouterRegBankxB;
+
+end behavioral;

ips/hw/scalp_router_regbank/src/sim/tb_scalp_router_regbank.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_router_regbank - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_router_regbank
+--
+-- Last update: 2021-05-20 11:02:08
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_router_regbank is
+end tb_scalp_router_regbank;
+
+
+architecture behavioral of tb_scalp_router_regbank is
+
+begin
+
+end behavioral;

ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_1.tcl

+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ARADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to validate C_AXI4_AWADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to validate C_AXI4_BRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to validate C_AXI4_DATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to validate C_AXI4_RDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to validate C_AXI4_RRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to validate C_AXI4_WDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to validate C_AXI4_WSTRB_SIZE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+

ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_2.tcl

+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ARADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to validate C_AXI4_AWADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to validate C_AXI4_BRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to validate C_AXI4_DATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to validate C_AXI4_RDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to validate C_AXI4_RRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to validate C_AXI4_WDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to validate C_AXI4_WSTRB_SIZE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+

ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_3.tcl

+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ARADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to validate C_AXI4_AWADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to validate C_AXI4_BRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to validate C_AXI4_DATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to validate C_AXI4_RDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to validate C_AXI4_RRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to validate C_AXI4_WDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to validate C_AXI4_WSTRB_SIZE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+

ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v1_0.tcl

+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to validate C_AXI4_ARADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to validate C_AXI4_AWADDR_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to validate C_AXI4_BRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to validate C_AXI4_DATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to validate C_AXI4_RDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to validate C_AXI4_RRESP_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to validate C_AXI4_WDATA_SIZE
+	return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to validate C_AXI4_WSTRB_SIZE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+