From 6c51bd78350f82868bccf96265ea07a4876b65ce Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Wed, 27 Oct 2021 08:11:05 +0200
Subject: [PATCH] Update templage_regbank.vhd
---
.gitignore | 10 ++++++++++
src/templates/hdl/template_regbank.vhd | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
create mode 100644 .gitignore
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..27745e4
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,10 @@
+#########
+# Ignore
+#########
+# Emacs
+#########
+*.*~
+*.*#
+################
+# Do NOT ingore
+################
diff --git a/src/templates/hdl/template_regbank.vhd b/src/templates/hdl/template_regbank.vhd
index fa97b19..4930988 100644
--- a/src/templates/hdl/template_regbank.vhd
+++ b/src/templates/hdl/template_regbank.vhd
@@ -129,7 +129,7 @@ begin
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
- WrValidxAS : WrValidxS <= SAxiWValidxSI;
+ WrValidxAS : WrValidxS <= SAxiWValidxSI and not SAxiAWValidxSI;;
WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
--
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