From 11b8273de6944009a493a9fb76a4a70ac69d0f52 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch>
Date: Sat, 22 Mar 2025 19:40:21 +0100
Subject: [PATCH] New periph address width is 8
So, any address received on AXI side greater than 255 will be see its
MSB truncated.
So, 256 will be 0, etc
---
.../sources_1/new/axi4lite_hog_build_info.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd b/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd
index 67aab0e..88d54ab 100644
--- a/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd
+++ b/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd
@@ -30,7 +30,7 @@ use IEEE.NUMERIC_STD.ALL;
entity axi4lite_hog_build_info is
generic (
- C_ADDR_WIDTH: integer := 32 -- Width of the addresses
+ C_ADDR_WIDTH: integer := 8 -- Width of the addresses
);
port (
s_axi_aclk : in std_logic;
--
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