From 25e0ca2e05be3ad1b252b1a6e4d23e6df66b76f2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch>
Date: Wed, 19 Mar 2025 18:47:21 +0100
Subject: [PATCH] Registers bank: Rename the reset input (and update test
bench)
---
.../sim_1/new/tb_hog_build_info_regs.vhd | 4 ++--
.../sources_1/new/hog_build_info_regs.vhd | 7 ++++---
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd b/hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd
index 98f0926..60b8813 100644
--- a/hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd
+++ b/hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd
@@ -38,7 +38,7 @@ architecture Behavioral of tb_hog_build_info_regs is
port (
clk_i : in std_logic; -- Clock in
- resetn : in std_logic; -- Reset in
+ resetn_i : in std_logic; -- Reset in
rd_valid_i : in std_logic; -- AXI4-lite R interface, validation
rd_addr_i : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
rd_data_o : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
@@ -130,7 +130,7 @@ begin
)
port map (
clk_i => clk_s,
- resetn => resetn_s,
+ resetn_i => resetn_s,
rd_valid_i => rd_valid_s,
rd_addr_i => rd_addr_s,
rd_data_o => rd_data_s,
diff --git a/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd b/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
index cae5022..134696d 100644
--- a/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
+++ b/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
@@ -25,12 +25,12 @@ use IEEE.numeric_std.all;
entity hog_build_info_regs is
generic (
- C_ADDR_WIDTH: integer := 32 -- Width of the addresses
+ C_ADDR_WIDTH: integer := 4 -- Width of the addresses
);
port (
clk_i : in std_logic; -- Clock in
- resetn : in std_logic; -- Reset in
+ resetn_i : in std_logic; -- Reset in
rd_valid_i : in std_logic; -- AXI4-lite R interface, validation
rd_addr_i : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
rd_data_o : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
@@ -76,6 +76,7 @@ architecture Behavioral of hog_build_info_regs is
-- Read address integer
signal rd_addr_s : integer := 0;
+
-- Read data
signal rd_data_s : std_logic_vector(31 downto 0);
@@ -88,7 +89,7 @@ begin
rd_regigters_proc: process(clk_i)
begin
if rising_edge(clk_i) then
- if resetn = '0' then
+ if resetn_i = '0' then
-- If reset, set data read to 0x00
rd_data_s <= (others => '0');
else
--
GitLab