diff --git a/Top/hog-build-info/list/xil_defaultlib.src b/Top/hog-build-info/list/xil_defaultlib.src index fd36ac475b66353055fdccb39bb0b854f999a90c..f59b45bcff08448902bbe6a1a56906ba65aeb4f9 100644 --- a/Top/hog-build-info/list/xil_defaultlib.src +++ b/Top/hog-build-info/list/xil_defaultlib.src @@ -1,4 +1,5 @@ -hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd top=hog_build_info_regs 93 +hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd top=axi4lite_hog_build_info 93 +hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd 93 hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_rd_channel_if.vhd 93 hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_wr_channel_if.vhd 93 hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_if.vhd 93 diff --git a/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd b/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd new file mode 100644 index 0000000000000000000000000000000000000000..cc6588cbab7c81ce765d8c4cb4064b25e31b741c --- /dev/null +++ b/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd @@ -0,0 +1,232 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03/19/2025 06:04:31 PM +-- Design Name: Hog build info AXI4-lite peripheral +-- Module Name: axi4lite_hog_build_info - Behavioral +-- Project Name: Hog build info +-- Target Devices: Microblaze +-- Tool Versions: +-- Description: The AXI4-lite peripheral that give access to Hog build infos +-- +-- Dependencies: +-- - axi4lite_if +-- - hog_build_info_regs +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +entity axi4lite_hog_build_info is + generic ( + C_ADDR_WIDTH: integer := 32 -- Width of the addresses + ); + port ( + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + -- AXI4-Lite Write interface + s_axi_awaddr : in std_logic_vector(31 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + -- AXI4-Lite Read interface + s_axi_araddr : in std_logic_vector(31 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + -- Write register interface + wr_valid_o : out std_logic; + wr_addr_o : out std_logic_vector((C_ADDR_WIDTH - 1) downto 0); + wr_data_o : out std_logic_vector(31 downto 0); + -- Read register interface + rd_valid_o : out std_logic; + rd_addr_o : out std_logic_vector((C_ADDR_WIDTH - 1) downto 0); + rd_data_i : in std_logic_vector(31 downto 0); + -- Hog build info interface + hog_global_date_i : in std_logic_vector(31 downto 0); -- Hog build global date + hog_global_time_i : in std_logic_vector(31 downto 0); -- Hog build global time + hog_global_ver_i : in std_logic_vector(31 downto 0); -- Hog build global version + hog_global_sha_i : in std_logic_vector(31 downto 0) -- Hog build global latest commit SHA + ); +end axi4lite_hog_build_info; + +architecture Behavioral of axi4lite_hog_build_info is + + -- Data width are fixed by Hog as 32 bits + constant C_DATA_WIDTH : integer := 32; + + -- Clock and reset signals + signal clk_s : std_logic; + signal resetn_s : std_logic; + + -- Signals to connect AXI4-lite if to registers bank + --- Write register interface + signal wr_valid_s : std_logic; + signal wr_addr_s : std_logic_vector((C_ADDR_WIDTH - 1) downto 0); + signal wr_data_s : std_logic_vector(31 downto 0); + --- Read register interface + signal rd_valid_o : std_logic; + signal rd_addr_o : std_logic_vector((C_ADDR_WIDTH - 1) downto 0); + signal rd_data_i : std_logic_vector(31 downto 0); + + -- Used components + --- Axi4-lite interface + component axi4lite_if + generic ( + C_DATA_WIDTH : integer := 32; + C_ADDR_WIDTH : integer := 4 + ); + port ( + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + -- AXI4-Lite Write interface + s_axi_awaddr : in std_logic_vector(31 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + -- AXI4-Lite Read interface + s_axi_araddr : in std_logic_vector(31 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + -- Write register interface + wr_valid_o : out std_logic; + wr_addr_o : out std_logic_vector((C_ADDR_WIDTH - 1) downto 0); + wr_data_o : out std_logic_vector((C_DATA_WIDTH - 1) downto 0); + -- Read register interface + rd_valid_o : out std_logic; + rd_addr_o : out std_logic_vector((C_ADDR_WIDTH - 1) downto 0); + rd_data_i : in std_logic_vector((C_DATA_WIDTH - 1) downto 0) + ); + end component axi4lite_if; + + --- Registers bank + component hog_build_info_regs + generic ( + C_ADDR_WIDTH: integer := 4 -- Width of the addresses + ); + + port ( + clk_i : in std_logic; + resetn_i : in std_logic; + -- Registry read interface + rd_valid_i : in std_logic; + rd_addr_i : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); + rd_data_o : out std_logic_vector(31 downto 0); + -- Registry write interface + wr_valid_i : in std_logic := '0'; + wr_addr_i : in std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); + wr_data_i : in std_logic_vector(31 downto 0) := (others => '0'); + -- Hog build info interface + hog_global_date_i : in std_logic_vector(31 downto 0); + hog_global_time_i : in std_logic_vector(31 downto 0); + hog_global_ver_i : in std_logic_vector(31 downto 0); + hog_global_sha_i : in std_logic_vector(31 downto 0) + ); + end component hog_build_info_regs; + +begin + + ----------------------------------------------------------------------------- + -- AXI4Lite interface + ----------------------------------------------------------------------------- + + axi4lite_if_inst : entity axi4lite_if + generic map ( + C_ADDR_WIDTH => C_ADDR_WIDTH, + C_DATA_WIDTH => C_DATA_WIDTH + ) + port map ( + s_axi_aclk => clk_s, + s_axi_aresetn => resetn_s, + -- AXI4-Lite Write interface + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_awready => s_axi_awready, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_bready => s_axi_bready + -- AXI4-Lite Read interface + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + -- Write register interface + wr_valid_o => wr_valid_s, + wr_addr_o => wr_addr_s, + wr_data_o => wr_data_s, + -- Read register interface + rd_valid_o => rd_valid_s, + rd_addr_o => rd_addr_s, + rd_data_i => rd_data_s, + ); + + + ----------------------------------------------------------------------------- + -- Register bank + ----------------------------------------------------------------------------- + + hog_build_info_regs_inst : entity hog_build_info_regs + generic map ( + C_ADDR_WIDTH => C_ADDR_WIDTH + ) + port map ( + clk_i => clk_s, + resetn_i => resetn_s, + -- Registry read interface + rd_valid_i => rd_valid_s, + rd_addr_i => rd_addr_s, + rd_data_o => rd_data_s, + -- Registry write interface + wr_valid_i => wr_valid_s, + wr_addr_i => wr_addr_s, + wr_data_i => wr_data_s, + -- Hog build info interface + hog_global_date_i => hog_global_date_i, + hog_global_time_i => hog_global_time_i, + hog_global_ver_i => hog_global_ver_i, + hog_global_sha_i => hog_global_sha_i, + ); + + ----------------------------------------------------------------------------- + -- Reset and clock signals + ----------------------------------------------------------------------------- + + clk_s <= s_axi_aclk; + resetn_i <= s_axi_aresetn; + +end Behavioral;