From 62b1b85b3df1327a97acf5cc497a9efd2b2851b7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch>
Date: Wed, 19 Mar 2025 19:03:07 +0100
Subject: [PATCH] axi4lite_hog_build_info entity: Fix typo

---
 .../sources_1/new/axi4lite_hog_build_info.vhd      | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd b/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd
index cc6588c..1693b61 100644
--- a/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd
+++ b/hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd
@@ -83,9 +83,9 @@ architecture Behavioral of axi4lite_hog_build_info is
   signal wr_addr_s : std_logic_vector((C_ADDR_WIDTH - 1) downto 0);
   signal wr_data_s : std_logic_vector(31 downto 0);
   --- Read register interface
-  signal rd_valid_o : std_logic;
-  signal rd_addr_o  : std_logic_vector((C_ADDR_WIDTH - 1) downto 0);
-  signal rd_data_i  : std_logic_vector(31 downto 0);
+  signal rd_valid_s : std_logic;
+  signal rd_addr_s  : std_logic_vector((C_ADDR_WIDTH - 1) downto 0);
+  signal rd_data_s  : std_logic_vector(31 downto 0);
 
   -- Used components
   --- Axi4-lite interface
@@ -158,7 +158,7 @@ begin
   -- AXI4Lite interface
   -----------------------------------------------------------------------------
 
-  axi4lite_if_inst : entity axi4lite_if
+  axi4lite_if_inst : entity work.axi4lite_if
     generic map (
       C_ADDR_WIDTH => C_ADDR_WIDTH,
       C_DATA_WIDTH => C_DATA_WIDTH
@@ -176,7 +176,7 @@ begin
       s_axi_wready  =>      s_axi_wready,
       s_axi_bresp   =>      s_axi_bresp,
       s_axi_bvalid  =>      s_axi_bvalid,
-      s_axi_bready  =>      s_axi_bready
+      s_axi_bready  =>      s_axi_bready,
       -- AXI4-Lite Read interface
       s_axi_araddr  =>      s_axi_araddr,
       s_axi_arvalid =>      s_axi_arvalid,
@@ -192,7 +192,7 @@ begin
       -- Read register interface
       rd_valid_o    =>      rd_valid_s,
       rd_addr_o     =>      rd_addr_s,
-      rd_data_i     =>      rd_data_s,
+      rd_data_i     =>      rd_data_s
       );
   
 
@@ -219,7 +219,7 @@ begin
       hog_global_date_i =>      hog_global_date_i,
       hog_global_time_i =>      hog_global_time_i,
       hog_global_ver_i  =>      hog_global_ver_i,
-      hog_global_sha_i  =>      hog_global_sha_i,
+      hog_global_sha_i  =>      hog_global_sha_i
       );
   
   -----------------------------------------------------------------------------
-- 
GitLab