From 93b8a638f0894f23b1a4635ae2daca3e7a3cd01b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch> Date: Fri, 14 Mar 2025 18:49:44 +0100 Subject: [PATCH] Bank register: Fix missing address for the 2nd register --- .../hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd b/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd index abf5252..4242fa2 100644 --- a/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd +++ b/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd @@ -48,14 +48,14 @@ architecture Behavioral of hog_build_info_regs is -- [31 - 0] Date in hexa, with digits in format: ddmmyyyy signal global_date_reg : std_logic_vector(31 downto 0) := (others => '0'); --- Global time register (GTR) @ 0x00 - R +-- Global time register (GTR) @ 0x04 - R -- Time of last commit when the project was modified. -- [31 - 0] Time in hexa, with digits in format: 00HHMMSS signal global_time_reg : std_logic_vector(31 downto 0) := (others => '0'); -- Registers addresses constant GDR_BASEADDR : integer := 0; -- Global date register - constant GTR_BASEADDR : integer := 0; -- Global time register + constant GTR_BASEADDR : integer := 4; -- Global time register -- Read address integer signal rd_addr_s : integer := 0; -- GitLab