From 977af9ddaa531878a19e5acc382a760fdaa0a14b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch>
Date: Thu, 20 Mar 2025 00:57:09 +0100
Subject: [PATCH] AXI4-lite periph: Set correct wait time between accesses and
bad step value
---
.../tb_axi4lite_hog_build_info.vhd | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd b/hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd
index 2e05e4d..2f1032b 100644
--- a/hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd
+++ b/hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd
@@ -221,28 +221,28 @@ begin
-- Request to read register 0
axi4lite_read(GDR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
- check_reg_0_data_s <= '0';
- wait for CLK_PERIOD;
+ check_reg_0_data_s <= '1';
+ wait for CLK_PERIOD * 2;
-- Request to read register 1
axi4lite_read(GTR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
- check_reg_1_data_s <= '0';
- wait for CLK_PERIOD;
+ check_reg_1_data_s <= '1';
+ wait for CLK_PERIOD * 2;
-- Request to read register 2
axi4lite_read(GVR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
- check_reg_2_data_s <= '0';
- wait for CLK_PERIOD;
+ check_reg_2_data_s <= '1';
+ wait for CLK_PERIOD * 2;
-- Request to read register 3
axi4lite_read(GSR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
- check_reg_3_data_s <= '0';
- wait for CLK_PERIOD;
+ check_reg_3_data_s <= '1';
+ wait for CLK_PERIOD * 2;
-- Request to read unknown register
axi4lite_read(UNK_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
- check_reg_unk_data_s <= '0';
- wait for CLK_PERIOD;
+ check_reg_unk_data_s <= '1';
+ wait for CLK_PERIOD * 2;
-- Wait endlessly
wait;
--
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