From a1cfa2cca0326a91acebf9c0846720e6a66d7636 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch>
Date: Sat, 15 Mar 2025 19:48:51 +0100
Subject: [PATCH] Register bank: Add input for write channel

---
 .../hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd  | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd b/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
index 4242fa2..ea303f8 100644
--- a/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
+++ b/hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
@@ -34,6 +34,9 @@ entity hog_build_info_regs is
     rd_valid_i        : in std_logic; -- AXI4-lite R interface, validation
     rd_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
     rd_data_o         : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
+    wr_valid_i        : in std_logic := '0'; -- AXI4-lite W interface, validation
+    wr_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- AXI4-lite W, address
+    wr_data_i         : in std_logic_vector(31 downto 0) := (others => '0'); -- AXI4-lite W, data
     hog_global_date_i : in std_logic_vector(31 downto 0); -- Hog build global date
     hog_global_time_i : in std_logic_vector(31 downto 0) -- Hog build global time
     );
-- 
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