From f8b97d0b0a9b1c4457e05175ce2f4b2a5e9b583c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Gendre?= <sebastien.gendre@etu.hesge.ch>
Date: Sun, 9 Mar 2025 17:41:52 +0100
Subject: [PATCH] Write a small simulation to print Hog build info

---
 .../sim_1/new/explore_build_info.vhd          | 22 ++++++++++---------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/hog-build-info/hog-build-info.srcs/sim_1/new/explore_build_info.vhd b/hog-build-info/hog-build-info.srcs/sim_1/new/explore_build_info.vhd
index abfef6a..841d45c 100644
--- a/hog-build-info/hog-build-info.srcs/sim_1/new/explore_build_info.vhd
+++ b/hog-build-info/hog-build-info.srcs/sim_1/new/explore_build_info.vhd
@@ -21,23 +21,25 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
+use ieee.numeric_std.all;
+use std.textio.all;
 
 entity explore_build_info is
---  Port ( );
+  Generic (
+    -- Global Generic Variables
+    GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
+    GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
+    GLOBAL_VER  : std_logic_vector(31 downto 0) := (others => '0');
+    GLOBAL_SHA  : std_logic_vector(31 downto 0) := (others => '0')
+    );
 end explore_build_info;
 
 architecture Behavioral of explore_build_info is
 
 begin
 
+  assert false
+    report "GLOBAL_DATE: " & to_hstring(to_bitvector(GLOBAL_DATE))
+    severity note;
 
 end Behavioral;
-- 
GitLab