diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/a9ad1272a4ff99ca.xci b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/a9ad1272a4ff99ca.xci
new file mode 100644
index 0000000000000000000000000000000000000000..64beed561ee399acbd84e956f92cc4bcbcb3c221
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/a9ad1272a4ff99ca.xci
@@ -0,0 +1,296 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>ipcache</spirit:library>
+ <spirit:name>a9ad1272a4ff99ca</spirit:name>
+ <spirit:version>0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>design_1_clk_wiz_0_1</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">400000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">90.074</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">87.180</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">400.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_clk_wiz_0_1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:nexys_video:part0:1.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">sbg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">e6a05ff8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">a9ad1272a4ff99ca</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">design_1_clk_wiz_0_1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 5145035 $</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">401ad827</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">14</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2024.1.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1.dcp b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..b552ddc956d45241bff043450f37b5d8fe9db026
Binary files /dev/null and b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1.dcp differ
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.v b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.v
new file mode 100755
index 0000000000000000000000000000000000000000..ced7afcd3fb3110c33015cd1734765841a1e7803
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.v
@@ -0,0 +1,220 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:27:01 2024
+// Host : hogtest running 64-bit unknown
+// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.v
+// Design : design_1_clk_wiz_0_1
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+ (clk_out1,
+ reset,
+ locked,
+ clk_in1);
+ output clk_out1;
+ input reset;
+ output locked;
+ input clk_in1;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire locked;
+ wire reset;
+
+ decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .locked(locked),
+ .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+ (clk_out1,
+ reset,
+ locked,
+ clk_in1);
+ output clk_out1;
+ input reset;
+ output locked;
+ input clk_in1;
+
+ wire clk_in1;
+ wire clk_in1_design_1_clk_wiz_0_1;
+ wire clk_out1;
+ wire clk_out1_design_1_clk_wiz_0_1;
+ wire clkfbout_buf_design_1_clk_wiz_0_1;
+ wire clkfbout_design_1_clk_wiz_0_1;
+ wire locked;
+ wire reset;
+ wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+ wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_design_1_clk_wiz_0_1),
+ .O(clkfbout_buf_design_1_clk_wiz_0_1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_design_1_clk_wiz_0_1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_design_1_clk_wiz_0_1),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ PLLE2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT(12),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE(3),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT1_DIVIDE(1),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT2_DIVIDE(1),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT3_DIVIDE(1),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .STARTUP_WAIT("FALSE"))
+ plle2_adv_inst
+ (.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_1),
+ .CLKFBOUT(clkfbout_design_1_clk_wiz_0_1),
+ .CLKIN1(clk_in1_design_1_clk_wiz_0_1),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKOUT0(clk_out1_design_1_clk_wiz_0_1),
+ .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+ .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+ .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+ .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(locked),
+ .PWRDWN(1'b0),
+ .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.vhdl b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..e1115bcd92063533b3a6f2e0e58a4be75474c2cd
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.vhdl
@@ -0,0 +1,151 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:27:01 2024
+-- Host : hogtest running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.vhdl
+-- Design : design_1_clk_wiz_0_1
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+ signal clk_in1_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal clk_out1_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal clkfbout_buf_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal clkfbout_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_design_1_clk_wiz_0_1,
+ O => clkfbout_buf_design_1_clk_wiz_0_1
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_design_1_clk_wiz_0_1
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_design_1_clk_wiz_0_1,
+ O => clk_out1
+ );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT => 12,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE => 3,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT1_DIVIDE => 1,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ STARTUP_WAIT => "FALSE"
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_1,
+ CLKFBOUT => clkfbout_design_1_clk_wiz_0_1,
+ CLKIN1 => clk_in1_design_1_clk_wiz_0_1,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKOUT0 => clk_out1_design_1_clk_wiz_0_1,
+ CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+ CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+ CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+ CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PWRDWN => '0',
+ RST => reset
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ locked => locked,
+ reset => reset
+ );
+end STRUCTURE;
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.v b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.v
new file mode 100755
index 0000000000000000000000000000000000000000..fd8f6f24d868eb63929cff72cf639ebdb069721c
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.v
@@ -0,0 +1,24 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:27:01 2024
+// Host : hogtest running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.v
+// Design : design_1_clk_wiz_0_1
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+ output clk_out1 /* synthesis syn_isclock = 1 */;
+ input reset;
+ output locked;
+ input clk_in1;
+endmodule
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.vhdl b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..a2a8207b4c3fe19748eecd70ed57ec3f1c0724d6
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.vhdl
@@ -0,0 +1,32 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:27:01 2024
+-- Host : hogtest running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.vhdl
+-- Design : design_1_clk_wiz_0_1
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/adff1593d44ebeb2.xci b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/adff1593d44ebeb2.xci
new file mode 100644
index 0000000000000000000000000000000000000000..d1bf710456af5d7fc76c04b84a4628bf6ef0baeb
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/adff1593d44ebeb2.xci
@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>ipcache</spirit:library>
+ <spirit:name>adff1593d44ebeb2</spirit:name>
+ <spirit:version>0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>design_1_clk_wiz_0_1</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">400000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">90.074</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">87.180</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">400.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">design_1_clk_wiz_0_1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z010i</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg225</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1L</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">I</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">e6a05ff8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">adff1593d44ebeb2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">design_1_clk_wiz_0_1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 5145035 $</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">401ad827</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">31</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">14</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2024.1.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1.dcp b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..5823dce89f7fb9ee7088d59c058ae60bb23d66cf
Binary files /dev/null and b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1.dcp differ
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.v b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.v
new file mode 100755
index 0000000000000000000000000000000000000000..cc6f7964ccfdb105816087506cfd0d7982963b5d
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.v
@@ -0,0 +1,220 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:19:53 2024
+// Host : hogtest running 64-bit unknown
+// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.v
+// Design : design_1_clk_wiz_0_1
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+ (clk_out1,
+ reset,
+ locked,
+ clk_in1);
+ output clk_out1;
+ input reset;
+ output locked;
+ input clk_in1;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire locked;
+ wire reset;
+
+ decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .locked(locked),
+ .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+ (clk_out1,
+ reset,
+ locked,
+ clk_in1);
+ output clk_out1;
+ input reset;
+ output locked;
+ input clk_in1;
+
+ wire clk_in1;
+ wire clk_in1_design_1_clk_wiz_0_1;
+ wire clk_out1;
+ wire clk_out1_design_1_clk_wiz_0_1;
+ wire clkfbout_buf_design_1_clk_wiz_0_1;
+ wire clkfbout_design_1_clk_wiz_0_1;
+ wire locked;
+ wire reset;
+ wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+ wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_design_1_clk_wiz_0_1),
+ .O(clkfbout_buf_design_1_clk_wiz_0_1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_design_1_clk_wiz_0_1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_design_1_clk_wiz_0_1),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ PLLE2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT(12),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE(3),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT1_DIVIDE(1),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT2_DIVIDE(1),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT3_DIVIDE(1),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .STARTUP_WAIT("FALSE"))
+ plle2_adv_inst
+ (.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_1),
+ .CLKFBOUT(clkfbout_design_1_clk_wiz_0_1),
+ .CLKIN1(clk_in1_design_1_clk_wiz_0_1),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKOUT0(clk_out1_design_1_clk_wiz_0_1),
+ .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+ .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+ .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+ .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(locked),
+ .PWRDWN(1'b0),
+ .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.vhdl b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..66ea0ebf27627a0badfb633ac94585783a634090
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.vhdl
@@ -0,0 +1,151 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:19:53 2024
+-- Host : hogtest running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.vhdl
+-- Design : design_1_clk_wiz_0_1
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+ signal clk_in1_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal clk_out1_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal clkfbout_buf_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal clkfbout_design_1_clk_wiz_0_1 : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_design_1_clk_wiz_0_1,
+ O => clkfbout_buf_design_1_clk_wiz_0_1
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_design_1_clk_wiz_0_1
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_design_1_clk_wiz_0_1,
+ O => clk_out1
+ );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT => 12,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE => 3,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT1_DIVIDE => 1,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ STARTUP_WAIT => "FALSE"
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_1,
+ CLKFBOUT => clkfbout_design_1_clk_wiz_0_1,
+ CLKIN1 => clk_in1_design_1_clk_wiz_0_1,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKOUT0 => clk_out1_design_1_clk_wiz_0_1,
+ CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+ CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+ CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+ CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PWRDWN => '0',
+ RST => reset
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ locked => locked,
+ reset => reset
+ );
+end STRUCTURE;
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.v b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.v
new file mode 100755
index 0000000000000000000000000000000000000000..c49e511f4e87aec8fde7e0bd386e4fe3f8062799
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.v
@@ -0,0 +1,24 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:19:53 2024
+// Host : hogtest running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.v
+// Design : design_1_clk_wiz_0_1
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+ output clk_out1 /* synthesis syn_isclock = 1 */;
+ input reset;
+ output locked;
+ input clk_in1;
+endmodule
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.vhdl b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..9f25c22c81b12c1b2b4b8be1a6011147026a2409
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.vhdl
@@ -0,0 +1,32 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:19:53 2024
+-- Host : hogtest running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.vhdl
+-- Design : design_1_clk_wiz_0_1
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ reset : in STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;
diff --git a/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/stats.txt b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/stats.txt
new file mode 100644
index 0000000000000000000000000000000000000000..de897a52970ccdfa571c09764734928ef2f6f6e3
--- /dev/null
+++ b/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/stats.txt
@@ -0,0 +1,2 @@
+NumberHits:1
+Timestamp: Thu Nov 28 15:23:35 UTC 2024
diff --git a/Vivado/labo1b/labo1b.cache/wt/project.wpc b/Vivado/labo1b/labo1b.cache/wt/project.wpc
index 314c46168995fd73df9d8aa2f38447c375d12778..27e386da621ca4b873f76933af137502843cdd6a 100644
--- a/Vivado/labo1b/labo1b.cache/wt/project.wpc
+++ b/Vivado/labo1b/labo1b.cache/wt/project.wpc
@@ -1,4 +1,4 @@
version:1
-57656254616c6b5472616e736d697373696f6e417474656d70746564:4
-6d6f64655f636f756e7465727c4755494d6f6465:4
+57656254616c6b5472616e736d697373696f6e417474656d70746564:5
+6d6f64655f636f756e7465727c4755494d6f6465:7
eof:
diff --git a/Vivado/labo1b/labo1b.cache/wt/synthesis.wdf b/Vivado/labo1b/labo1b.cache/wt/synthesis.wdf
index 6f52bc4c8761405fda8c5c5408ff0b563a896698..ebd368ff4e4f679ad4d22c67b5aff72522868d13 100644
--- a/Vivado/labo1b/labo1b.cache/wt/synthesis.wdf
+++ b/Vivado/labo1b/labo1b.cache/wt/synthesis.wdf
@@ -1,5 +1,5 @@
version:1
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a30313069636c673232352d314c:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030747362673438342d31:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:64657369676e5f315f77726170706572:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@@ -47,6 +47,6 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323073:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323531342e3733344d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3931352e3735304d42:00:00
-eof:1124083508
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323631312e3834304d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937382e3136344d42:00:00
+eof:3999145180
diff --git a/Vivado/labo1b/labo1b.cache/wt/webtalk_pa.xml b/Vivado/labo1b/labo1b.cache/wt/webtalk_pa.xml
index 24fc08684582fd98bb11a69970de6591175c0865..90cffe9a494aff3b07f5adc9500a816cb1467040 100644
--- a/Vivado/labo1b/labo1b.cache/wt/webtalk_pa.xml
+++ b/Vivado/labo1b/labo1b.cache/wt/webtalk_pa.xml
@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Thu Nov 14 13:37:09 2024">
+<application name="pa" timeStamp="Thu Nov 28 16:35:16 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="dcc085f9009542c0a2e6a53a6f205a35" type="ProjectID"/>
-<property name="ProjectIteration" value="15" type="ProjectIteration"/>
+<property name="ProjectIteration" value="22" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/design_1.bxml b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/design_1.bxml
index a10347bbfe38b8bb862fd57199b96acf9ccb2a43..6168ff4718d4228652303dbbdd8c83f30f3e87f2 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/design_1.bxml
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/design_1.bxml
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="43">
<CompositeFile CompositeFileTopName="design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1731557632"/>
- <Generation Name="SIMULATION" State="GENERATED" Timestamp="1731557632"/>
- <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1731557632"/>
- <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1731557632"/>
+ <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1732807583"/>
+ <Generation Name="SIMULATION" State="GENERATED" Timestamp="1732807583"/>
+ <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1732807583"/>
+ <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1732807583"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth/design_1.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
index 370371c2399fa36bf1004ca3284a17be828534d7..7960561f7409981c4bd7174f5ee66d69f46eb8fe 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
@@ -1,8 +1,8 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
-//Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-//Date : Thu Nov 14 05:13:51 2024
+//Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+//Date : Thu Nov 28 16:26:23 2024
//Host : hogtest running 64-bit unknown
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
index 239a836c461bbbd9a27b71bab76e1a3eb2d5eef7..8010f5e17983e13517942802e17c8b059d394cf8 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Nov 14 05:13:52 2024" VIVADOVERSION="2024.1">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Nov 28 16:26:23 2024" VIVADOVERSION="2024.1.2">
- <SYSTEMINFO ARCH="zynq" DEVICE="7z010i" NAME="design_1" PACKAGE="clg225" SPEEDGRADE="-1L"/>
+ <SYSTEMINFO ARCH="artix7" BOARD="digilentinc.com:nexys_video:part0:1.2" DEVICE="7a200t" NAME="design_1" PACKAGE="sbg484" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
<PORT DIR="I" NAME="btnC" SIGIS="data" SIGNAME="External_Ports_btnC">
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp
index d5f03d18e5bc4ef47e0f3fc1b4ee30427e23978f..6ece7ce8c3412b63b16c092ee644b417aba27c3e 100644
Binary files a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp and b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp differ
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xml b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xml
index 76e66e91e6e9eba4221284b021f9d9b81bbb0890..dee0f0b596a87ee1654d52c05063c11aa67ef929 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xml
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xml
@@ -1224,11 +1224,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:b371cbca</spirit:value>
+ <spirit:value>9:e6611a58</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1243,11 +1243,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:b371cbca</spirit:value>
+ <spirit:value>9:e6611a58</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1262,11 +1262,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:9213207a</spirit:value>
+ <spirit:value>9:9bcb93bd</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1281,11 +1281,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:9213207a</spirit:value>
+ <spirit:value>9:9bcb93bd</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1296,7 +1296,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:f5d765c9</spirit:value>
+ <spirit:value>9:c737c113</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1310,11 +1310,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:14:26 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:27:01 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:9213207a</spirit:value>
+ <spirit:value>9:9bcb93bd</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1328,11 +1328,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:9213207a</spirit:value>
+ <spirit:value>9:9bcb93bd</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1343,7 +1343,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:9213207a</spirit:value>
+ <spirit:value>9:9bcb93bd</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -3560,15 +3560,16 @@
<spirit:enumeration>HIGH</spirit:enumeration>
<spirit:enumeration>OPTIMIZED</spirit:enumeration>
</spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_ac75ef1e</spirit:name>
- <spirit:enumeration>Custom</spirit:enumeration>
- </spirit:choice>
<spirit:choice>
<spirit:name>choice_list_b9d38208</spirit:name>
<spirit:enumeration>CLKFBOUT</spirit:enumeration>
<spirit:enumeration>CLKOUT0</spirit:enumeration>
</spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_ce26ebdb</spirit:name>
+ <spirit:enumeration>Custom</spirit:enumeration>
+ <spirit:enumeration>reset</spirit:enumeration>
+ </spirit:choice>
<spirit:choice>
<spirit:name>choice_list_e099fe6c</spirit:name>
<spirit:enumeration>MMCM</spirit:enumeration>
@@ -3600,12 +3601,6 @@
<spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
<spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
</spirit:choice>
- <spirit:choice>
- <spirit:name>choice_pairs_340369e0</spirit:name>
- <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
- <spirit:enumeration spirit:text="sys clock">sys_clock</spirit:enumeration>
- <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
- </spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_3c2d3ec7</spirit:name>
<spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
@@ -3658,6 +3653,11 @@
<spirit:enumeration spirit:text="Units UI">Units_UI</spirit:enumeration>
<spirit:enumeration spirit:text="Units ps">Units_ps</spirit:enumeration>
</spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_c6542ce1</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys clock">sys_clock</spirit:enumeration>
+ </spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_e1c87518</spirit:name>
<spirit:enumeration spirit:text="Primary Clock">REL_PRIMARY</spirit:enumeration>
@@ -4776,11 +4776,11 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.8">Custom</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_c6542ce1" spirit:order="13.8">Custom</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.9">Custom</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_c6542ce1" spirit:order="13.9">Custom</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
@@ -4796,7 +4796,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ce26ebdb" spirit:order="21.4">Custom</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ENABLE_CDDC</spirit:name>
@@ -4952,7 +4952,7 @@
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+ <xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52494094"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f72112df"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="4f3d3737"/>
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v
index 210dadf61cf5f05bc3b068d98ce3fed89730bb4d..b18775e2d273b9f24628229c8ec5af217c74a992 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v
@@ -1,15 +1,15 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-// Date : Thu Nov 14 05:14:26 2024
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:27:01 2024
// Host : hogtest running 64-bit unknown
// Command : write_verilog -force -mode funcsim {/home/hogtest/Projets/Cours
// FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v}
// Design : design_1_clk_wiz_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z010iclg225-1L
+// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl
index 4354b7b9c3bffae7c60f9d51571302f6b7b85071..e9bdf9758ac2af5650d803f918cd172196cca0fc 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl
@@ -1,15 +1,15 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
--- Date : Thu Nov 14 05:14:26 2024
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:27:01 2024
-- Host : hogtest running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim {/home/hogtest/Projets/Cours
-- FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl}
-- Design : design_1_clk_wiz_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
--- Device : xc7z010iclg225-1L
+-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v
index 71e8b7a7e7ad13cc57bceb7b3aa2eae861ccfe91..2b93794008446e68807f45d213cde1c261252f61 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v
@@ -1,14 +1,14 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-// Date : Thu Nov 14 05:14:26 2024
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:27:01 2024
// Host : hogtest running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hogtest/Projets/Cours
// FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v}
// Design : design_1_clk_wiz_0_1
// Purpose : Stub declaration of top-level module interface
-// Device : xc7z010iclg225-1L
+// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl
index 8a75873874038253c25de78cc19040644b4532c9..3ed893e22184e7cde1b68bfac6b9251bc4f0dd11 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl
@@ -1,14 +1,14 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
--- Date : Thu Nov 14 05:14:26 2024
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:27:01 2024
-- Host : hogtest running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub {/home/hogtest/Projets/Cours
-- FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl}
-- Design : design_1_clk_wiz_0_1
-- Purpose : Stub declaration of top-level module interface
--- Device : xc7z010iclg225-1L
+-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp
index 9ede92cb91547980481333a5c7d31c42e7524a6e..6ec581282fc1093a7f0d442c7e5cb0dbfadc8585 100644
Binary files a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp and b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp differ
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xml b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xml
index a76736915717cc81b5f2b03983438a51f7df8f94..003f19a7b3c8dbe38dc4c109354ab4490b2be76e 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xml
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xml
@@ -106,7 +106,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:463e698b</spirit:value>
+ <spirit:value>9:106f1eff</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -118,7 +118,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:4b2d71c3</spirit:value>
+ <spirit:value>9:9f623fbb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -132,11 +132,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:14:27 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:27:01 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:4b2d71c3</spirit:value>
+ <spirit:value>9:9f623fbb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -147,7 +147,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:4b2d71c3</spirit:value>
+ <spirit:value>9:9f623fbb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -163,11 +163,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:463e698b</spirit:value>
+ <spirit:value>9:106f1eff</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -183,11 +183,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Thu Nov 14 04:13:52 UTC 2024</spirit:value>
+ <spirit:value>Thu Nov 28 15:26:23 UTC 2024</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:4b2d71c3</spirit:value>
+ <spirit:value>9:9f623fbb</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -341,7 +341,7 @@
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
+ <xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.v
index 0d245dd42962cdd06bf23ef40dc5b38e56cff607..ec6eb43349dec1016c8ac62f0735427ef804dd83 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.v
@@ -1,20 +1,20 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-// Date : Thu Nov 14 05:14:27 2024
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:27:01 2024
// Host : hogtest running 64-bit unknown
// Command : write_verilog -force -mode funcsim {/home/hogtest/Projets/Cours
// FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.v}
// Design : design_1_reg_decalage_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z010iclg225-1L
+// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_reg_decalage_0_0,reg_decalage,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *)
-(* X_CORE_INFO = "reg_decalage,Vivado 2024.1" *)
+(* X_CORE_INFO = "reg_decalage,Vivado 2024.1.2" *)
(* NotValidForBitStream *)
module design_1_reg_decalage_0_0
(clk,
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.vhdl b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.vhdl
index edda7f8947aecc23a626354ae0315d61f720da3e..0d22f9838ed9f03e7580995ea729d69c57ba9a84 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.vhdl
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.vhdl
@@ -1,15 +1,15 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
--- Date : Thu Nov 14 05:14:27 2024
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:27:01 2024
-- Host : hogtest running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim {/home/hogtest/Projets/Cours
-- FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_sim_netlist.vhdl}
-- Design : design_1_reg_decalage_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
--- Device : xc7z010iclg225-1L
+-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -294,7 +294,7 @@ entity design_1_reg_decalage_0_0 is
attribute IP_DEFINITION_SOURCE : string;
attribute IP_DEFINITION_SOURCE of design_1_reg_decalage_0_0 : entity is "module_ref";
attribute X_CORE_INFO : string;
- attribute X_CORE_INFO of design_1_reg_decalage_0_0 : entity is "reg_decalage,Vivado 2024.1";
+ attribute X_CORE_INFO of design_1_reg_decalage_0_0 : entity is "reg_decalage,Vivado 2024.1.2";
end design_1_reg_decalage_0_0;
architecture STRUCTURE of design_1_reg_decalage_0_0 is
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.v
index 7719f1cc09f3ca4cd0cda340007974b488a349a5..63bb8efcc7147db917663207a53a79470511e472 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.v
@@ -1,20 +1,20 @@
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-// Date : Thu Nov 14 05:14:27 2024
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Nov 28 16:27:01 2024
// Host : hogtest running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hogtest/Projets/Cours
// FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.v}
// Design : design_1_reg_decalage_0_0
// Purpose : Stub declaration of top-level module interface
-// Device : xc7z010iclg225-1L
+// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "reg_decalage,Vivado 2024.1" *)
+(* X_CORE_INFO = "reg_decalage,Vivado 2024.1.2" *)
module design_1_reg_decalage_0_0(clk, btnU, btnC, btnD, led)
/* synthesis syn_black_box black_box_pad_pin="btnU,btnC,btnD,led[7:0]" */
/* synthesis syn_force_seq_prim="clk" */;
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.vhdl b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.vhdl
index cd9d4c85c72e764fa2a3d9befee9cab0625046e5..58f52d7a548033f1717e9fddf46ee81667177563 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.vhdl
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.vhdl
@@ -1,14 +1,14 @@
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
--- Date : Thu Nov 14 05:14:27 2024
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Nov 28 16:27:01 2024
-- Host : hogtest running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub {/home/hogtest/Projets/Cours
-- FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0_stub.vhdl}
-- Design : design_1_reg_decalage_0_0
-- Purpose : Stub declaration of top-level module interface
--- Device : xc7z010iclg225-1L
+-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -30,6 +30,6 @@ attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,btnU,btnC,btnD,led[7:0]";
attribute X_CORE_INFO : string;
-attribute X_CORE_INFO of stub : architecture is "reg_decalage,Vivado 2024.1";
+attribute X_CORE_INFO of stub : architecture is "reg_decalage,Vivado 2024.1.2";
begin
end;
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/synth/design_1_reg_decalage_0_0.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/synth/design_1_reg_decalage_0_0.v
index e8ddc80cca75426518a618dff4d1be4201a05196..2a687900f38f09aec259049f923ca63f4268e1ba 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/synth/design_1_reg_decalage_0_0.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/synth/design_1_reg_decalage_0_0.v
@@ -50,9 +50,9 @@
// IP VLNV: xilinx.com:module_ref:reg_decalage:1.0
// IP Revision: 1
-(* X_CORE_INFO = "reg_decalage,Vivado 2024.1" *)
+(* X_CORE_INFO = "reg_decalage,Vivado 2024.1.2" *)
(* CHECK_LICENSE_TYPE = "design_1_reg_decalage_0_0,reg_decalage,{}" *)
-(* CORE_GENERATION_INFO = "design_1_reg_decalage_0_0,reg_decalage,{x_ipProduct=Vivado 2024.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_decalage,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
+(* CORE_GENERATION_INFO = "design_1_reg_decalage_0_0,reg_decalage,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=reg_decalage,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_reg_decalage_0_0 (
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/sim/design_1.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/sim/design_1.v
index 0f48b7590bed86dc60e49a4af81dbbd53dd61a2e..04fe6390cad98ff1d09cf7cc7e71cd8d40766654 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/sim/design_1.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/sim/design_1.v
@@ -1,8 +1,8 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
-//Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-//Date : Thu Nov 14 05:13:51 2024
+//Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+//Date : Thu Nov 28 16:26:23 2024
//Host : hogtest running 64-bit unknown
//Command : generate_target design_1.bd
//Design : design_1
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.hwdef b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.hwdef
index d57f5d3b38baf25264df78463f060df51bca781a..940b1b3754f59fc3b6b8fe50c5b1895d72295b0d 100644
Binary files a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.hwdef and b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.hwdef differ
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v
index 0f48b7590bed86dc60e49a4af81dbbd53dd61a2e..04fe6390cad98ff1d09cf7cc7e71cd8d40766654 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v
@@ -1,8 +1,8 @@
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
-//Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-//Date : Thu Nov 14 05:13:51 2024
+//Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+//Date : Thu Nov 28 16:26:23 2024
//Host : hogtest running 64-bit unknown
//Command : generate_target design_1.bd
//Design : design_1
diff --git a/Vivado/labo1b/labo1b.gen/sources_1/bd/mref/reg_decalage/component.xml b/Vivado/labo1b/labo1b.gen/sources_1/bd/mref/reg_decalage/component.xml
index 9ef0b3e8e9cb302b4149a6d76b4b005a07d990ca..e6108c1ba12725f3c904c5267f8d1d7135b92e59 100644
--- a/Vivado/labo1b/labo1b.gen/sources_1/bd/mref/reg_decalage/component.xml
+++ b/Vivado/labo1b/labo1b.gen/sources_1/bd/mref/reg_decalage/component.xml
@@ -152,7 +152,7 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
- <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
@@ -164,10 +164,10 @@
<xilinx:designToolContext>IPI</xilinx:designToolContext>
</xilinx:designToolContexts>
<xilinx:coreRevision>1</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2024-11-14T04:12:35Z</xilinx:coreCreationDateTime>
+ <xilinx:coreCreationDateTime>2024-11-28T15:26:09Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+ <xilinx:xilinxVersion>2024.1.2</xilinx:xilinxVersion>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/README.txt
index ccad536b9b384be31e913764941bb39f7b8d9333..2e8fbc531e244a0b2789f1d8a0a66341332b356b 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/README.txt
@@ -1,5 +1,5 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/reg_decalage.sh
index 8ad93f378342206e222643344dc51f69bd9618bc..46dfc7bb5265c2b1daf686f360915a8e9ccc2f55 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/activehdl/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -47,7 +47,7 @@
#**********************************************************************************************************
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/reg_decalage.sh
index 080cac567b558afd60f4dbb0ae2163c1a745239b..bf338e386eff591f991eb2e61fec59f4ad7112bb 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/modelsim/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -50,7 +50,7 @@
set -Eeuo pipefail
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/reg_decalage.sh
index 68ea1e1ef7da9c9d1dc014a93aa9413656e58ca1..476d6f7bdb5aa9e94da39f8853179f164081bc6c 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/questa/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -50,7 +50,7 @@
set -Eeuo pipefail
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/reg_decalage.sh
index 165e7bf101698b01b0d1b88cc6d9e1c51b8fa254..59d9e0e51b3b4908c707408d42b5d1c0cfa893a4 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/riviera/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -50,7 +50,7 @@
set -Eeuo pipefail
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/reg_decalage.sh
index 1987ffa33f1ca95d50801f1cb78f1786d09ee9e5..942a8f0066ee0ebc29fb91778285ba75162a0704 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/vcs/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -68,7 +68,7 @@ design_libs=(xpm xil_defaultlib)
sim_lib_dir="vcs_lib"
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/reg_decalage.sh
index b025b0e38277355162809ec32eb6d517c7c5cc2b..e1263c8e7e9db40346f774722a2446cffa67943d 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xcelium/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -71,7 +71,7 @@ design_libs=(simprims_ver xpm xil_defaultlib)
sim_lib_dir="xcelium_lib"
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/README.txt b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/README.txt
index 9300ddbbeaf35d88afaa9731306f86d75bdf6305..02bb1840c1284e555a160eebf3f9d70410e5b26c 100644
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/README.txt
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/README.txt
@@ -1,11 +1,11 @@
################################################################################
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
-# Generated by export_simulation on Thu Nov 14 05:13:52 CET 2024
+# Generated by export_simulation on Thu Nov 28 16:26:24 CET 2024
#
################################################################################
diff --git a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/reg_decalage.sh b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/reg_decalage.sh
index efa8fdf25dc9e3db4c83942424a86009efd9e5e3..a03b4925d030f56fe6f794c12b812564c073ee34 100755
--- a/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/reg_decalage.sh
+++ b/Vivado/labo1b/labo1b.ip_user_files/sim_scripts/xsim/reg_decalage.sh
@@ -1,9 +1,9 @@
#!/bin/bash -f
#**********************************************************************************************************
-# Vivado (TM) v2024.1 (64-bit)
+# Vivado (TM) v2024.1.2 (64-bit)
#
-# Script generated by Vivado on Thu Nov 14 05:13:52 CET 2024
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# Script generated by Vivado on Thu Nov 28 16:26:24 CET 2024
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
@@ -36,7 +36,7 @@ xvlog_opts="--incr --relax -L uvm"
xvhdl_opts="--incr --relax "
# script info
-echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1 (64-bit)-id)\n"
+echo -e "reg_decalage.sh - Script generated by export_simulation (Vivado v2024.1.2 (64-bit)-id)\n"
# main steps
run()
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_24.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_24.xml
new file mode 100644
index 0000000000000000000000000000000000000000..baa467bfd8fa9f2116914ac574b3ffa98f69c1cf
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_24.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_25.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_25.xml
new file mode 100644
index 0000000000000000000000000000000000000000..53c308b6db29a01a5aa44f8ed1d93fa7c9704eca
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_25.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_26.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_26.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2d61184323b724aef00aab9e81a9cc0a67d60f1a
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_26.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_27.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_27.xml
new file mode 100644
index 0000000000000000000000000000000000000000..baa467bfd8fa9f2116914ac574b3ffa98f69c1cf
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_27.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_28.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_28.xml
new file mode 100644
index 0000000000000000000000000000000000000000..53c308b6db29a01a5aa44f8ed1d93fa7c9704eca
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_28.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_29.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_29.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2d61184323b724aef00aab9e81a9cc0a67d60f1a
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_29.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_30.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_30.xml
new file mode 100644
index 0000000000000000000000000000000000000000..53b4033d4787da54ce833a06e3c60244d34a8370
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_30.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="design_1_clk_wiz_0_1_synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="design_1_reg_decalage_0_0_synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado">
+ <Parent Id="design_1_clk_wiz_0_1_synth_1"/>
+ <Parent Id="design_1_reg_decalage_0_0_synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_31.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_31.xml
new file mode 100644
index 0000000000000000000000000000000000000000..53c308b6db29a01a5aa44f8ed1d93fa7c9704eca
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_31.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_32.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_32.xml
new file mode 100644
index 0000000000000000000000000000000000000000..36eb48841298e44c153512e6bf47308502d130e7
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_32.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="design_1_clk_wiz_0_1_synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="design_1_reg_decalage_0_0_synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_33.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_33.xml
new file mode 100644
index 0000000000000000000000000000000000000000..baa467bfd8fa9f2116914ac574b3ffa98f69c1cf
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_33.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_34.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_34.xml
new file mode 100644
index 0000000000000000000000000000000000000000..53c308b6db29a01a5aa44f8ed1d93fa7c9704eca
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_34.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_35.xml b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_35.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2d61184323b724aef00aab9e81a9cc0a67d60f1a
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/.jobs/vrs_config_35.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ <Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
+ <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
+ </Parameters>
+ <ProductInfo Name="vivado"/>
+</Runs>
+
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/.vivado.begin.rst b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/.vivado.begin.rst
index 28afbc3218c9b25ccb3e8568d10b7709a21d294e..8c2495d6c398609b75c07c18a708ff18010d3349 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/.vivado.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="7733" HostCore="8" HostMemory="8102388">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="13921" HostCore="8" HostMemory="8102392">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.dcp b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.dcp
index d5f03d18e5bc4ef47e0f3fc1b4ee30427e23978f..6ece7ce8c3412b63b16c092ee644b417aba27c3e 100644
Binary files a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.dcp and b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.tcl b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.tcl
index b609928596c053d503ff2907ecfe836a71eddd28..fdede2da8f81411d76dad0b5458d504b7cb15953 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.tcl
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.tcl
@@ -58,10 +58,12 @@ if {$::dispatch::connected} {
OPTRACE "design_1_clk_wiz_0_1_synth_1" START { ROLLUP_AUTO }
set_param chipscope.maxJobs 2
set_param tcl.statsThreshold 360
+set_msg_config -string {{.*The IP file '.*' has been moved from its original location, as a result the outputs for this IP will now be generated in '.*'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands..*}} -suppress -regexp
+set_msg_config -string {{.*File '.*.xci' referenced by design '.*' could not be found..*}} -suppress -regexp
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
-create_project -in_memory -part xc7z010iclg225-1L
+create_project -in_memory -part xc7a200tsbg484-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
@@ -72,6 +74,7 @@ set_property parent.project_path {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado
set_property XPM_LIBRARIES XPM_CDC [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
+set_property board_part digilentinc.com:nexys_video:part0:1.2 [current_project]
set_property ip_output_repo {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.cache/ip} [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
@@ -102,7 +105,7 @@ if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
-synth_design -top design_1_clk_wiz_0_1 -part xc7z010iclg225-1L -incremental_mode off -mode out_of_context
+synth_design -top design_1_clk_wiz_0_1 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.vds b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.vds
index 325e04024e42ebb1988344b027a99cda32ff6bda..a046c5dacf71a3cd1a580a69c34386606bc8aef7 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.vds
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.vds
@@ -1,10 +1,10 @@
#-----------------------------------------------------------
-# Vivado v2024.1 (64-bit)
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
-# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
-# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Thu Nov 14 05:13:55 2024
-# Process ID: 7817
+# Vivado v2024.1.2 (64-bit)
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
+# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
+# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
+# Start of session at: Thu Nov 28 16:26:27 2024
+# Process ID: 14005
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1
# Command line: vivado -log design_1_clk_wiz_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_clk_wiz_0_1.tcl
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.vds
@@ -19,21 +19,21 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11968 MB
+# Available Virtual :12355 MB
#-----------------------------------------------------------
source design_1_clk_wiz_0_1.tcl -notrace
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: design_1_clk_wiz_0_1
-Command: synth_design -top design_1_clk_wiz_0_1 -part xc7z010iclg225-1L -incremental_mode off -mode out_of_context
+Command: synth_design -top design_1_clk_wiz_0_1 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010i'
-INFO: [Device 21-403] Loading part xc7z010iclg225-1L
-INFO: [Device 21-9227] Part: xc7z010iclg225-1L does not have CEAM library.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 7857
+INFO: [Synth 8-7075] Helper process launched with PID 14049
---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2338.617 ; gain = 410.832 ; free physical = 133 ; free virtual = 8533
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2432.051 ; gain = 412.746 ; free physical = 109 ; free virtual = 8763
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_1' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.v:65]
INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_1_clk_wiz' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_clk_wiz.v:65]
@@ -56,18 +56,18 @@ INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/home/hogtest/Xilinx
INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_1_clk_wiz' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_clk_wiz.v:65]
INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_1' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.v:65]
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2415.586 ; gain = 487.801 ; free physical = 118 ; free virtual = 8250
+Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2517.020 ; gain = 497.715 ; free physical = 103 ; free virtual = 8587
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2433.398 ; gain = 505.613 ; free physical = 117 ; free virtual = 8249
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2534.832 ; gain = 515.527 ; free physical = 99 ; free virtual = 8582
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2433.398 ; gain = 505.613 ; free physical = 117 ; free virtual = 8249
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2534.832 ; gain = 515.527 ; free physical = 99 ; free virtual = 8582
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2439.336 ; gain = 0.000 ; free physical = 107 ; free virtual = 8239
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2540.770 ; gain = 0.000 ; free physical = 87 ; free virtual = 8576
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
@@ -87,31 +87,31 @@ Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.r
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2506.336 ; gain = 0.000 ; free physical = 117 ; free virtual = 8219
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2607.770 ; gain = 0.000 ; free physical = 157 ; free virtual = 8554
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2506.336 ; gain = 0.000 ; free physical = 117 ; free virtual = 8219
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2607.770 ; gain = 0.000 ; free physical = 157 ; free virtual = 8554
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2506.336 ; gain = 578.551 ; free physical = 113 ; free virtual = 8220
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2607.770 ; gain = 588.465 ; free physical = 148 ; free virtual = 8551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
-Loading part: xc7z010iclg225-1L
+Loading part: xc7a200tsbg484-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 113 ; free virtual = 8220
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 149 ; free virtual = 8552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/dont_touch.xdc}, line 9).
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 113 ; free virtual = 8220
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 149 ; free virtual = 8553
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 110 ; free virtual = 8218
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 145 ; free virtual = 8551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -124,8 +124,8 @@ Finished RTL Component Statistics
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
-DSPs: 80 (col length:40)
-BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
@@ -134,25 +134,25 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 112 ; free virtual = 8220
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 139 ; free virtual = 8548
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 164 ; free virtual = 8215
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 127 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 164 ; free virtual = 8215
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 127 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 164 ; free virtual = 8215
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 127 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -170,37 +170,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 111 ; free virtual = 8541
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 111 ; free virtual = 8541
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 109 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 109 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 107 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 106 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -221,18 +221,18 @@ Report Cell Usage:
|3 |IBUF | 1|
+------+----------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.340 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.773 ; gain = 596.469 ; free physical = 103 ; free virtual = 8539
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.340 ; gain = 513.617 ; free physical = 151 ; free virtual = 8201
-Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2514.348 ; gain = 586.555 ; free physical = 151 ; free virtual = 8201
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2615.773 ; gain = 523.531 ; free physical = 174 ; free virtual = 8555
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2615.781 ; gain = 596.469 ; free physical = 174 ; free virtual = 8555
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.348 ; gain = 0.000 ; free physical = 151 ; free virtual = 8201
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2615.781 ; gain = 0.000 ; free physical = 174 ; free virtual = 8555
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.348 ; gain = 0.000 ; free physical = 776 ; free virtual = 8830
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2615.781 ; gain = 0.000 ; free physical = 791 ; free virtual = 9178
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
@@ -242,10 +242,10 @@ INFO: [Common 17-83] Releasing license: Synthesis
synth_design completed successfully
INFO: [Common 17-600] The following parameters have non-default value.
tcl.statsThreshold
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2538.352 ; gain = 0.000 ; free physical = 776 ; free virtual = 8831
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2639.785 ; gain = 0.000 ; free physical = 791 ; free virtual = 9178
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.dcp' has been generated.
-INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_clk_wiz_0_1, cache-ID = b7b409a4069369be
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2594.379 ; gain = 0.000 ; free physical = 773 ; free virtual = 8828
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_clk_wiz_0_1, cache-ID = a9ad1272a4ff99ca
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2695.812 ; gain = 0.000 ; free physical = 791 ; free virtual = 9177
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.dcp' has been generated.
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_clk_wiz_0_1_utilization_synth.rpt -pb design_1_clk_wiz_0_1_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 05:14:26 2024...
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:27:01 2024...
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.pb b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.pb
index 8a634eb059d5e1ca8b85376ddecedf8de932ff40..6e600eff21e0f4070d3fb01e6b2a5effb28143c3 100644
Binary files a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.pb and b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.rpt b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.rpt
index 62fd2a243f23effc34f619ba3bb21c53e3f1c2e0..a1c778090a357707d4a081acba88700ce65600cb 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.rpt
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1_utilization_synth.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Thu Nov 14 05:14:26 2024
+| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+| Date : Thu Nov 28 16:27:01 2024
| Host : hogtest running 64-bit unknown
| Command : report_utilization -file design_1_clk_wiz_0_1_utilization_synth.rpt -pb design_1_clk_wiz_0_1_utilization_synth.pb
| Design : design_1_clk_wiz_0_1
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -31,14 +31,14 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs* | 0 | 0 | 0 | 17600 | 0.00 |
-| LUT as Logic | 0 | 0 | 0 | 17600 | 0.00 |
-| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
-| Slice Registers | 0 | 0 | 0 | 35200 | 0.00 |
-| Register as Flip Flop | 0 | 0 | 0 | 35200 | 0.00 |
-| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
-| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
-| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
+| Slice LUTs* | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Logic | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Flip Flop | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@@ -70,9 +70,9 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -83,7 +83,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
-| DSPs | 0 | 0 | 0 | 80 | 0.00 |
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -93,20 +93,22 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB | 1 | 0 | 0 | 54 | 1.85 |
-| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
-| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
-| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
-| IBUFDS | 0 | 0 | 0 | 54 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
-| ILOGIC | 0 | 0 | 0 | 54 | 0.00 |
-| OLOGIC | 0 | 0 | 0 | 54 | 0.00 |
+| Bonded IOB | 1 | 0 | 0 | 285 | 0.35 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
@@ -117,12 +119,12 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
-| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
-| PLLE2_ADV | 1 | 0 | 0 | 2 | 50.00 |
-| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
-| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
-| BUFR | 0 | 0 | 0 | 8 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 1 | 0 | 0 | 10 | 10.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -138,6 +140,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/gen_run.xml b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/gen_run.xml
index 0b0560803f05d86735238ba05823e1923f2b7804..4d07e3fe6fe53ecf502a4163d2fcfdbef5d180bb 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/gen_run.xml
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/gen_run.xml
@@ -1,11 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="design_1_clk_wiz_0_1_synth_1" LaunchPart="xc7z010iclg225-1L" LaunchTime="1731557632">
+<GenRun Id="design_1_clk_wiz_0_1_synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1732807584">
+ <File Type="VDS-TIMINGSUMMARY" Name="design_1_clk_wiz_0_1_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="design_1_clk_wiz_0_1.dcp"/>
<File Type="RDS-UTIL-PB" Name="design_1_clk_wiz_0_1_utilization_synth.pb"/>
- <File Type="PA-TCL" Name="design_1_clk_wiz_0_1.tcl"/>
<File Type="RDS-UTIL" Name="design_1_clk_wiz_0_1_utilization_synth.rpt"/>
+ <File Type="VDS-TIMING-PB" Name="design_1_clk_wiz_0_1_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="design_1_clk_wiz_0_1.tcl"/>
<File Type="REPORTS-TCL" Name="design_1_clk_wiz_0_1_reports.tcl"/>
<File Type="RDS-RDS" Name="design_1_clk_wiz_0_1.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="design_1_clk_wiz_0_1_drc_synth.rpt"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_clk_wiz_0_1" RelGenDir="$PGENDIR/design_1_clk_wiz_0_1">
<File Path="$PSRCDIR/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xci">
<FileInfo>
@@ -13,7 +16,6 @@
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
</FileInfo>
</File>
<Config>
@@ -28,7 +30,6 @@
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
</FileInfo>
</File>
<Config>
@@ -43,7 +44,9 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/project.wdf b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/project.wdf
index 00cd5e5468dfb02ffebe80745d2ab71bf7531002..2b65bc2f3c63ce03554caed8e3793ce9b6340144 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/project.wdf
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/project.wdf
@@ -6,7 +6,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
@@ -22,12 +22,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3637386232343565313261393437313239656134373838363962396332363937:506172656e742050412070726f6a656374204944:00
-eof:2245874392
+eof:1425733881
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.jou b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.jou
index b28b4e891b47944322f1ec29bcb9b8ae58323149..8dc766152102bd439bb09ce957e7768e2c87f663 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.jou
+++ b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.jou
@@ -1,10 +1,10 @@
#-----------------------------------------------------------
-# Vivado v2024.1 (64-bit)
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
-# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
-# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Thu Nov 14 05:13:55 2024
-# Process ID: 7817
+# Vivado v2024.1.2 (64-bit)
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
+# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
+# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
+# Start of session at: Thu Nov 28 16:26:27 2024
+# Process ID: 14005
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1
# Command line: vivado -log design_1_clk_wiz_0_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_clk_wiz_0_1.tcl
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/design_1_clk_wiz_0_1.vds
@@ -19,6 +19,6 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11968 MB
+# Available Virtual :12355 MB
#-----------------------------------------------------------
source design_1_clk_wiz_0_1.tcl -notrace
diff --git a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.pb b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.pb
index ffed359c9941c8b22af160d3413f722a43f8e73d..6317b3753cb5ba8fdb98d3f2be805a2b1d27e4c4 100644
Binary files a/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.pb and b/Vivado/labo1b/labo1b.runs/design_1_clk_wiz_0_1_synth_1/vivado.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/.vivado.begin.rst b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/.vivado.begin.rst
index 5aa289d44c5892b7db040280ed258de57960ff9e..2d664af12e8481db87af2a66b1d181c533db2294 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/.vivado.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="7735" HostCore="8" HostMemory="8102388">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="13922" HostCore="8" HostMemory="8102392">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.dcp b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.dcp
index 9ede92cb91547980481333a5c7d31c42e7524a6e..6ec581282fc1093a7f0d442c7e5cb0dbfadc8585 100644
Binary files a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.dcp and b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.tcl b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.tcl
index 565ee156622b2da96ad418ab466d22aebb0a561e..5d3e52496a1130451e3b4db23532d6465fa3f1e8 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.tcl
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.tcl
@@ -58,10 +58,12 @@ if {$::dispatch::connected} {
OPTRACE "design_1_reg_decalage_0_0_synth_1" START { ROLLUP_AUTO }
set_param chipscope.maxJobs 2
set_param tcl.statsThreshold 360
+set_msg_config -string {{.*The IP file '.*' has been moved from its original location, as a result the outputs for this IP will now be generated in '.*'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands..*}} -suppress -regexp
+set_msg_config -string {{.*File '.*.xci' referenced by design '.*' could not be found..*}} -suppress -regexp
set_param project.vivado.isBlockSynthRun true
OPTRACE "Creating in-memory project" START { }
set_param ips.modRefOverrideMrefDirPath {{/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/mref}}
-create_project -in_memory -part xc7z010iclg225-1L
+create_project -in_memory -part xc7a200tsbg484-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
@@ -72,6 +74,7 @@ set_property parent.project_path {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado
set_property XPM_LIBRARIES XPM_CDC [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
+set_property board_part digilentinc.com:nexys_video:part0:1.2 [current_project]
update_ip_catalog
set_property ip_output_repo {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.cache/ip} [current_project]
set_property ip_cache_permissions {read write} [current_project]
@@ -96,7 +99,7 @@ set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
-synth_design -top design_1_reg_decalage_0_0 -part xc7z010iclg225-1L -incremental_mode off -mode out_of_context
+synth_design -top design_1_reg_decalage_0_0 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.vds b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.vds
index 0cab5af342a720f3deb4913e8401ba8a4e2196ae..909e0555e58af693408f15366577c87985fd3027 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.vds
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.vds
@@ -1,10 +1,10 @@
#-----------------------------------------------------------
-# Vivado v2024.1 (64-bit)
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
-# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
-# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Thu Nov 14 05:13:55 2024
-# Process ID: 7818
+# Vivado v2024.1.2 (64-bit)
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
+# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
+# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
+# Start of session at: Thu Nov 28 16:26:27 2024
+# Process ID: 14006
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1
# Command line: vivado -log design_1_reg_decalage_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_reg_decalage_0_0.tcl
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.vds
@@ -19,23 +19,23 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11968 MB
+# Available Virtual :12355 MB
#-----------------------------------------------------------
source design_1_reg_decalage_0_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hogtest/Xilinx/tools/Vivado/2024.1/data/ip'.
-Command: synth_design -top design_1_reg_decalage_0_0 -part xc7z010iclg225-1L -incremental_mode off -mode out_of_context
+Command: synth_design -top design_1_reg_decalage_0_0 -part xc7a200tsbg484-1 -incremental_mode off -mode out_of_context
Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010i'
-INFO: [Device 21-403] Loading part xc7z010iclg225-1L
-INFO: [Device 21-9227] Part: xc7z010iclg225-1L does not have CEAM library.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 7866
+INFO: [Synth 8-7075] Helper process launched with PID 14088
---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2336.625 ; gain = 411.746 ; free physical = 159 ; free virtual = 8412
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2430.270 ; gain = 412.715 ; free physical = 108 ; free virtual = 8762
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'design_1_reg_decalage_0_0' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/synth/design_1_reg_decalage_0_0.v:53]
INFO: [Synth 8-638] synthesizing module 'reg_decalage' [/home/hogtest/Projets/Cours FPGA/Labo1B/reg_decalage.vhd:14]
@@ -47,48 +47,48 @@ INFO: [Synth 8-256] done synthesizing module '\reg ' (0#1) [/home/hogtest/Projet
INFO: [Synth 8-256] done synthesizing module 'reg_decalage' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/reg_decalage.vhd:14]
INFO: [Synth 8-6155] done synthesizing module 'design_1_reg_decalage_0_0' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/synth/design_1_reg_decalage_0_0.v:53]
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2414.594 ; gain = 489.715 ; free physical = 138 ; free virtual = 8234
+Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2515.238 ; gain = 497.684 ; free physical = 103 ; free virtual = 8586
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2429.438 ; gain = 504.559 ; free physical = 138 ; free virtual = 8234
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2533.051 ; gain = 515.496 ; free physical = 90 ; free virtual = 8574
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2429.438 ; gain = 504.559 ; free physical = 138 ; free virtual = 8234
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2533.051 ; gain = 515.496 ; free physical = 90 ; free virtual = 8574
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2429.438 ; gain = 0.000 ; free physical = 138 ; free virtual = 8234
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2533.051 ; gain = 0.000 ; free physical = 91 ; free virtual = 8578
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2532.188 ; gain = 0.000 ; free physical = 116 ; free virtual = 8220
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2628.801 ; gain = 0.000 ; free physical = 173 ; free virtual = 8565
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2532.188 ; gain = 0.000 ; free physical = 116 ; free virtual = 8220
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2628.801 ; gain = 0.000 ; free physical = 173 ; free virtual = 8566
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2532.188 ; gain = 607.309 ; free physical = 110 ; free virtual = 8217
+Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2628.801 ; gain = 611.246 ; free physical = 149 ; free virtual = 8552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
-Loading part: xc7z010iclg225-1L
+Loading part: xc7a200tsbg484-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 110 ; free virtual = 8217
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 149 ; free virtual = 8552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 110 ; free virtual = 8217
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 149 ; free virtual = 8552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 110 ; free virtual = 8218
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 145 ; free virtual = 8551
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -106,8 +106,8 @@ Finished RTL Component Statistics
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
-DSPs: 80 (col length:40)
-BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
@@ -116,25 +116,25 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 104 ; free virtual = 8214
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 139 ; free virtual = 8548
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 164 ; free virtual = 8215
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 139 ; free virtual = 8552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 164 ; free virtual = 8215
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 139 ; free virtual = 8552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 149 ; free virtual = 8200
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 127 ; free virtual = 8540
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -152,37 +152,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -204,16 +204,16 @@ Report Cell Usage:
|4 |FDRE | 11|
+------+-----+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.191 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.805 ; gain = 619.250 ; free physical = 129 ; free virtual = 8543
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2540.191 ; gain = 512.562 ; free physical = 438 ; free virtual = 8489
-Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 2540.199 ; gain = 615.312 ; free physical = 438 ; free virtual = 8489
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2636.805 ; gain = 523.500 ; free physical = 129 ; free virtual = 8543
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2636.812 ; gain = 619.250 ; free physical = 130 ; free virtual = 8543
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2540.199 ; gain = 0.000 ; free physical = 438 ; free virtual = 8489
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2636.812 ; gain = 0.000 ; free physical = 110 ; free virtual = 8541
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.219 ; gain = 0.000 ; free physical = 774 ; free virtual = 8827
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2692.832 ; gain = 0.000 ; free physical = 791 ; free virtual = 9178
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
@@ -224,7 +224,7 @@ synth_design completed successfully
INFO: [Common 17-600] The following parameters have non-default value.
tcl.statsThreshold
INFO: [Coretcl 2-1174] Renamed 2 cell refs.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2620.230 ; gain = 0.000 ; free physical = 774 ; free virtual = 8827
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.844 ; gain = 0.000 ; free physical = 791 ; free virtual = 9179
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.dcp' has been generated.
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_reg_decalage_0_0_utilization_synth.rpt -pb design_1_reg_decalage_0_0_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 05:14:27 2024...
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:27:01 2024...
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.pb b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.pb
index 4ae54fd6432e1c369ca7eecb58837912711a0c87..edbb594b91f422934906b6c0df3eca629badf554 100644
Binary files a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.pb and b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.rpt b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.rpt
index 1b7ca4ad3863382dc3681a99ebdd5f7423a17708..5e0620b56e21165ad4c7fe5b5a703e0ecada8904 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.rpt
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0_utilization_synth.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
-| Date : Thu Nov 14 05:14:27 2024
+| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+| Date : Thu Nov 28 16:27:01 2024
| Host : hogtest running 64-bit unknown
| Command : report_utilization -file design_1_reg_decalage_0_0_utilization_synth.rpt -pb design_1_reg_decalage_0_0_utilization_synth.pb
| Design : design_1_reg_decalage_0_0
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -31,14 +31,14 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs* | 6 | 0 | 0 | 17600 | 0.03 |
-| LUT as Logic | 6 | 0 | 0 | 17600 | 0.03 |
-| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
-| Slice Registers | 11 | 0 | 0 | 35200 | 0.03 |
-| Register as Flip Flop | 11 | 0 | 0 | 35200 | 0.03 |
-| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
-| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
-| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
+| Slice LUTs* | 6 | 0 | 0 | 134600 | <0.01 |
+| LUT as Logic | 6 | 0 | 0 | 134600 | <0.01 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 11 | 0 | 0 | 269200 | <0.01 |
+| Register as Flip Flop | 11 | 0 | 0 | 269200 | <0.01 |
+| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@@ -70,9 +70,9 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -83,7 +83,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
-| DSPs | 0 | 0 | 0 | 80 | 0.00 |
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -93,20 +93,22 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB | 0 | 0 | 0 | 54 | 0.00 |
-| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
-| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
-| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
-| IBUFDS | 0 | 0 | 0 | 54 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
-| ILOGIC | 0 | 0 | 0 | 54 | 0.00 |
-| OLOGIC | 0 | 0 | 0 | 54 | 0.00 |
+| Bonded IOB | 0 | 0 | 0 | 285 | 0.00 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
@@ -117,12 +119,12 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
-| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
-| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
-| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
-| BUFR | 0 | 0 | 0 | 8 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -138,6 +140,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/gen_run.xml b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/gen_run.xml
index 74cba0f660f877e7215032009fc57772f4eb3729..54df7e70627cae999a6c32b375738fb301fd7aac 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/gen_run.xml
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/gen_run.xml
@@ -1,11 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="design_1_reg_decalage_0_0_synth_1" LaunchPart="xc7z010iclg225-1L" LaunchTime="1731557632">
+<GenRun Id="design_1_reg_decalage_0_0_synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1732807584">
+ <File Type="VDS-TIMINGSUMMARY" Name="design_1_reg_decalage_0_0_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="design_1_reg_decalage_0_0.dcp"/>
<File Type="RDS-UTIL-PB" Name="design_1_reg_decalage_0_0_utilization_synth.pb"/>
- <File Type="PA-TCL" Name="design_1_reg_decalage_0_0.tcl"/>
<File Type="RDS-UTIL" Name="design_1_reg_decalage_0_0_utilization_synth.rpt"/>
+ <File Type="VDS-TIMING-PB" Name="design_1_reg_decalage_0_0_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="design_1_reg_decalage_0_0.tcl"/>
<File Type="REPORTS-TCL" Name="design_1_reg_decalage_0_0_reports.tcl"/>
<File Type="RDS-RDS" Name="design_1_reg_decalage_0_0.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="design_1_reg_decalage_0_0_drc_synth.rpt"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/design_1_reg_decalage_0_0" RelGenDir="$PGENDIR/design_1_reg_decalage_0_0">
<File Path="$PSRCDIR/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xci">
<FileInfo>
@@ -13,7 +16,6 @@
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
</FileInfo>
</File>
<Config>
@@ -28,7 +30,6 @@
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
</FileInfo>
</File>
<Config>
@@ -43,7 +44,9 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/project.wdf b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/project.wdf
index 00cd5e5468dfb02ffebe80745d2ab71bf7531002..2b65bc2f3c63ce03554caed8e3793ce9b6340144 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/project.wdf
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/project.wdf
@@ -6,7 +6,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
@@ -22,12 +22,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3637386232343565313261393437313239656134373838363962396332363937:506172656e742050412070726f6a656374204944:00
-eof:2245874392
+eof:1425733881
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.jou b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.jou
index 7d3d69efd7d030cf097e5873ddb59989f7b827f9..3ebf48e245c6796f5819e72893163b226196dca0 100644
--- a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.jou
+++ b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.jou
@@ -1,10 +1,10 @@
#-----------------------------------------------------------
-# Vivado v2024.1 (64-bit)
-# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
-# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
-# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Thu Nov 14 05:13:55 2024
-# Process ID: 7818
+# Vivado v2024.1.2 (64-bit)
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
+# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
+# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
+# Start of session at: Thu Nov 28 16:26:27 2024
+# Process ID: 14006
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1
# Command line: vivado -log design_1_reg_decalage_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_reg_decalage_0_0.tcl
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/design_1_reg_decalage_0_0.vds
@@ -19,6 +19,6 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11968 MB
+# Available Virtual :12355 MB
#-----------------------------------------------------------
source design_1_reg_decalage_0_0.tcl -notrace
diff --git a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.pb b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.pb
index fa4f6e0e7473a4d56d8e867e174dce4f02445b14..e329962b9d1079a1c26224d8c78478dc19cb32de 100644
Binary files a/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.pb and b/Vivado/labo1b/labo1b.runs/design_1_reg_decalage_0_0_synth_1/vivado.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.init_design.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.init_design.begin.rst
index 286a41bb75431b65a7843132a70029f8d72523f7..5aa10244baef2fa264a2a9a6c88aa9121867cbac 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.init_design.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.init_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="7847">
+ <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="14663">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.opt_design.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.opt_design.begin.rst
index 286a41bb75431b65a7843132a70029f8d72523f7..5aa10244baef2fa264a2a9a6c88aa9121867cbac 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.opt_design.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.opt_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="7847">
+ <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="14663">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.phys_opt_design.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.phys_opt_design.begin.rst
index 286a41bb75431b65a7843132a70029f8d72523f7..5aa10244baef2fa264a2a9a6c88aa9121867cbac 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.phys_opt_design.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.phys_opt_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="7847">
+ <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="14663">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.place_design.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.place_design.begin.rst
index 286a41bb75431b65a7843132a70029f8d72523f7..5aa10244baef2fa264a2a9a6c88aa9121867cbac 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.place_design.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.place_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="7847">
+ <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="14663">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.route_design.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.route_design.begin.rst
index 286a41bb75431b65a7843132a70029f8d72523f7..5aa10244baef2fa264a2a9a6c88aa9121867cbac 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.route_design.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.route_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="7847">
+ <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="14663">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.vivado.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.vivado.begin.rst
index da7f850223af10f86092a7edc4e1620222410de9..1f77c638c2d0ad1913c3227fa16dff91bda67e2f 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.vivado.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.vivado.begin.rst
@@ -1,10 +1,25 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="7805" HostCore="8" HostMemory="8102396">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="11123" HostCore="8" HostMemory="8102392">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="9127" HostCore="8" HostMemory="8102396">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="12488" HostCore="8" HostMemory="8102392">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="13568" HostCore="8" HostMemory="8102392">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="14621" HostCore="8" HostMemory="8102392">
+ </Process>
+</ProcessHandle>
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="16444" HostCore="8" HostMemory="8102392">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.begin.rst b/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.begin.rst
index 983c1165de4d42dfc46cb7f861d143ebb78ff37e..68a38f4def3b549abe343c0792ca9507cdf34c82 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="9169">
+ <Process Command=".planAhead." Owner="hogtest" Host="hogtest" Pid="16486">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.vivado.error.rst b/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.end.rst
similarity index 100%
rename from Vivado/labo1b/labo1b.runs/impl_1/.vivado.error.rst
rename to Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.end.rst
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.error.rst b/Vivado/labo1b/labo1b.runs/impl_1/.write_bitstream.error.rst
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/clockInfo.txt b/Vivado/labo1b/labo1b.runs/impl_1/clockInfo.txt
index 329f48aa463bb3ced72a1667edfcccd70017d4ef..c984abb92dd56d1f7e75825b2c7ecd07feca8386 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/clockInfo.txt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/clockInfo.txt
@@ -1,9 +1,9 @@
-------------------------------------
| Tool Version : Vivado v.2024.1.2
-| Date : Thu Nov 14 13:36:52 2024
+| Date : Thu Nov 28 16:32:04 2024
| Host : hogtest
| Design : design_1
-| Device : xc7z010i-clg225-1L-I-
+| Device : xc7a200t-sbg484-1--
-------------------------------------
For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.bit b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.bit
new file mode 100644
index 0000000000000000000000000000000000000000..e707567f18715cb5a163d6ba7c15e694e7dda5fe
Binary files /dev/null and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.bit differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.tcl b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.tcl
index a04c9f1d70439f5b6a53d1baa80c1512a742544b..b5320505099d12a67b294193ba2e1e1929858355 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.tcl
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.tcl
@@ -97,6 +97,8 @@ proc step_failed { step } {
OPTRACE "impl_1" END { }
}
+set_msg_config -string {{.*The IP file '.*' has been moved from its original location, as a result the outputs for this IP will now be generated in '.*'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands..*}} -suppress -regexp
+set_msg_config -string {{.*File '.*.xci' referenced by design '.*' could not be found..*}} -suppress -regexp
OPTRACE "impl_1" START { ROLLUP_1 }
OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
@@ -106,6 +108,7 @@ set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
set_param chipscope.maxJobs 2
+ set_param tcl.statsThreshold 360
set_param runs.launchOptions { -jobs 4 }
open_checkpoint design_1_wrapper_routed.dcp
set_property webtalk.parent_dir {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.cache/wt} [current_project]
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
index 7ebcb82c45de2851f126348913abc2cd8479def8..7927226b2a6e6252e661d23e758791ec885946cd 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
@@ -3,8 +3,8 @@
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:36:33 2024
-# Process ID: 7847
+# Start of session at: Thu Nov 28 16:31:41 2024
+# Process ID: 14663
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
@@ -19,23 +19,23 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11470 MB
+# Available Virtual :12349 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hogtest/Xilinx/tools/Vivado/2024.1/data/ip'.
-Command: link_design -top design_1_wrapper -part xc7z010iclg225-1L
+Command: link_design -top design_1_wrapper -part xc7a200tsbg484-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
-INFO: [Device 21-403] Loading part xc7z010iclg225-1L
-INFO: [Device 21-9227] Part: xc7z010iclg225-1L does not have CEAM library.
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
INFO: [Project 1-454] Reading design checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp' for cell 'design_1_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp' for cell 'design_1_i/reg_decalage_0'
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1946.828 ; gain = 0.000 ; free physical = 902 ; free virtual = 10298
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2038.219 ; gain = 0.000 ; free physical = 1845 ; free virtual = 10861
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
-INFO: [Project 1-479] Netlist was created with Vivado 2024.1
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
@@ -44,29 +44,19 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/hogtest/Projets
INFO: [Timing 38-2] Deriving generated clocks [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc:54]
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc] for cell 'design_1_i/clk_wiz_0/inst'
Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc]
-CRITICAL WARNING: [Common 17-69] Command failed: 'R4' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:8]
-CRITICAL WARNING: [Common 17-69] Command failed: 'T14' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:22]
-CRITICAL WARNING: [Common 17-69] Command failed: 'T15' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:23]
-CRITICAL WARNING: [Common 17-69] Command failed: 'T16' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:24]
-CRITICAL WARNING: [Common 17-69] Command failed: 'U16' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:25]
-CRITICAL WARNING: [Common 17-69] Command failed: 'V15' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:26]
-CRITICAL WARNING: [Common 17-69] Command failed: 'W16' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:27]
-CRITICAL WARNING: [Common 17-69] Command failed: 'W15' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:28]
-CRITICAL WARNING: [Common 17-69] Command failed: 'Y13' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:29]
-CRITICAL WARNING: [Common 17-69] Command failed: 'B22' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:33]
-CRITICAL WARNING: [Common 17-69] Command failed: 'D22' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:34]
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2624.246 ; gain = 0.000 ; free physical = 353 ; free virtual = 9762
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2763.770 ; gain = 0.000 ; free physical = 1299 ; free virtual = 10336
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-15 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
+15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2624.246 ; gain = 991.535 ; free physical = 353 ; free virtual = 9762
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
Command: opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010i'
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command opt_design
Starting DRC Task
@@ -74,112 +64,112 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2688.277 ; gain = 64.031 ; free physical = 336 ; free virtual = 9745
+Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2827.801 ; gain = 64.031 ; free physical = 1311 ; free virtual = 10348
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 250df70fd
+Ending Cache Timing Information Task | Checksum: 256e02795
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2688.277 ; gain = 0.000 ; free physical = 335 ; free virtual = 9745
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2827.801 ; gain = 0.000 ; free physical = 1311 ; free virtual = 10348
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 250df70fd
+Phase 1.1 Core Generation And Design Setup | Checksum: 256e02795
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 115 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10042
Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 250df70fd
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 256e02795
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 115 ; free virtual = 9435
-Phase 1 Initialization | Checksum: 250df70fd
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10042
+Phase 1 Initialization | Checksum: 256e02795
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 115 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10042
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
-Phase 2.1 Timer Update | Checksum: 250df70fd
+Phase 2.1 Timer Update | Checksum: 256e02795
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10041
Phase 2.2 Timing Data Collection
-Phase 2.2 Timing Data Collection | Checksum: 250df70fd
+Phase 2.2 Timing Data Collection | Checksum: 256e02795
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Phase 2 Timer Update And Timing Data Collection | Checksum: 250df70fd
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10041
+Phase 2 Timer Update And Timing Data Collection | Checksum: 256e02795
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10041
Phase 3 Retarget
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 250df70fd
+Phase 3 Retarget | Checksum: 256e02795
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Retarget | Checksum: 250df70fd
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Retarget | Checksum: 256e02795
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 250df70fd
+Phase 4 Constant propagation | Checksum: 256e02795
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Constant propagation | Checksum: 250df70fd
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Constant propagation | Checksum: 256e02795
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
-Phase 5 Sweep | Checksum: 2690de14c
+Phase 5 Sweep | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Sweep | Checksum: 2690de14c
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Sweep | Checksum: 26f0e97e4
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 2690de14c
+Phase 6 BUFG optimization | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-BUFG optimization | Checksum: 2690de14c
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+BUFG optimization | Checksum: 26f0e97e4
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 2690de14c
+Phase 7 Shift Register Optimization | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Shift Register Optimization | Checksum: 2690de14c
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Shift Register Optimization | Checksum: 26f0e97e4
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 2690de14c
+Phase 8 Post Processing Netlist | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Post Processing Netlist | Checksum: 2690de14c
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Post Processing Netlist | Checksum: 26f0e97e4
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2690de14c
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 2690de14c
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Phase 9 Finalization | Checksum: 2690de14c
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Phase 9 Finalization | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
Opt_design Change Summary
=========================
@@ -196,29 +186,31 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
-Ending Logic Optimization Task | Checksum: 2690de14c
+Ending Logic Optimization Task | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 2690de14c
+Ending Power Optimization Task | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 2690de14c
+Ending Final Cleanup Task | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
-Ending Netlist Obfuscation Task | Checksum: 2690de14c
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Ending Netlist Obfuscation Task | Checksum: 26f0e97e4
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
INFO: [Common 17-83] Releasing license: Implementation
-34 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
+35 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -226,20 +218,20 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 146 ; free virtual = 9438
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 146 ; free virtual = 9438
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 146 ; free virtual = 9438
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10042
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10042
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10042
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
-Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10043
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10043
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10043
+Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10048
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
Command: place_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010i'
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
@@ -255,54 +247,54 @@ Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9436
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 230d9d08a
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 998 ; free virtual = 10042
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 236da8722
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9436
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9436
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 998 ; free virtual = 10042
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 998 ; free virtual = 10042
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ef0c3055
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1bc38e117
-Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 140 ; free virtual = 9432
+Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 984 ; free virtual = 10031
Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 24050593c
+Phase 1.3 Build Placer Netlist Model | Checksum: 1eb442b17
-Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 134 ; free virtual = 9429
+Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 984 ; free virtual = 10031
Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 24050593c
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1eb442b17
-Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9437
-Phase 1 Placer Initialization | Checksum: 24050593c
+Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 984 ; free virtual = 10031
+Phase 1 Placer Initialization | Checksum: 1eb442b17
-Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9437
+Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 983 ; free virtual = 10031
Phase 2 Global Placement
Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 2a6b39e8b
+Phase 2.1 Floorplanning | Checksum: 1c493d4b9
-Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9436
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 979 ; free virtual = 10027
Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2a217b8a6
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2495728f0
-Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9436
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 979 ; free virtual = 10027
Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2a217b8a6
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 2495728f0
-Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9436
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 979 ; free virtual = 10027
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
-Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 25c43c498
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 236cb21d7
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.26 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9438
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 943 ; free virtual = 9992
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
@@ -317,7 +309,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 147 ; free virtual = 9441
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 939 ; free virtual = 9991
Summary of Physical Synthesis Optimizations
============================================
@@ -339,55 +331,55 @@ Summary of Physical Synthesis Optimizations
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-Phase 2.4.2 Physical Synthesis In Placer | Checksum: 25c43c498
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 236cb21d7
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.54 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 147 ; free virtual = 9441
-Phase 2.4 Global Placement Core | Checksum: 22fb7f765
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+Phase 2.4 Global Placement Core | Checksum: 1ef8b2f73
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9446
-Phase 2 Global Placement | Checksum: 22fb7f765
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.88 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+Phase 2 Global Placement | Checksum: 1ef8b2f73
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9446
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.88 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 25ac10194
+Phase 3.1 Commit Multi Column Macros | Checksum: 1d486398a
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.69 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9445
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.9 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2278c4f69
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2966bbfaa
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 150 ; free virtual = 9444
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.92 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 2e6dac979
+Phase 3.3 Area Swap Optimization | Checksum: 1ff89d11b
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9445
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.93 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 2e4d933a3
+Phase 3.4 Pipeline Register Optimization | Checksum: 2376f352c
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9445
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.93 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 295821a43
+Phase 3.5 Small Shape Detail Placement | Checksum: 1e3efe8b9
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 295821a43
+Phase 3.6 Re-assign LUT pins | Checksum: 1e3efe8b9
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 274242b16
+Phase 3.7 Pipeline Register Optimization | Checksum: 21c0a8caa
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
-Phase 3 Detail Placement | Checksum: 274242b16
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 3 Detail Placement | Checksum: 21c0a8caa
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 4 Post Placement Optimization and Clean-Up
@@ -395,7 +387,7 @@ Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 28d31213d
+Post Placement Optimization Initialization | Checksum: 1f5099abb
Phase 4.1.1.1 BUFG Insertion
@@ -403,33 +395,33 @@ Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.670 | TNS=0.000 |
-Phase 1 Physical Synthesis Initialization | Checksum: 1b5106441
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.716 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 1654a0736
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 1e2cf2294
+Ending Physical Synthesis Task | Checksum: 19a6df91d
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
-Phase 4.1.1.1 BUFG Insertion | Checksum: 28d31213d
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1f5099abb
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.84 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=0.670. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e50d54a6
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.716. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1ef975e62
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
-Phase 4.1 Post Commit Optimization | Checksum: 1e50d54a6
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4.1 Post Commit Optimization | Checksum: 1ef975e62
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1e50d54a6
+Phase 4.2 Post Placement Cleanup | Checksum: 1ef975e62
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 4.3 Placer Reporting
@@ -448,72 +440,76 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
| West| 1x1| 1x1|
|___________|___________________|___________________|
-Phase 4.3.1 Print Estimated Congestion | Checksum: 1e50d54a6
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1ef975e62
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
-Phase 4.3 Placer Reporting | Checksum: 1e50d54a6
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4.3 Placer Reporting | Checksum: 1ef975e62
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ab14c66f
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b59ed02b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
-Ending Placer Task | Checksum: 170a2839b
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Ending Placer Task | Checksum: 128415a24
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.86 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
-68 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+70 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
Running report generation with 3 threads.
INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9432
+report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9432
-Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9432
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9431
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 136 ; free virtual = 9431
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 136 ; free virtual = 9431
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 135 ; free virtual = 9431
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 134 ; free virtual = 9430
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
Command: phys_opt_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010i'
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Starting Initial Update Timing Task
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
-INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.670 | TNS= 0.000 |
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.716 | TNS= 0.000 |
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
-79 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
+82 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
-Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 124 ; free virtual = 9420
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 124 ; free virtual = 9420
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 124 ; free virtual = 9420
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 123 ; free virtual = 9419
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 921 ; free virtual = 9974
+Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 921 ; free virtual = 9974
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated.
Command: route_design
-Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010i'
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
@@ -524,30 +520,30 @@ Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
-Checksum: PlaceDB: a6bc7693 ConstDB: 0 ShapeSum: 604db5dd RouteDB: 6998572b
-Post Restoration Checksum: NetGraph: 6eb65909 | NumContArr: b80e0518 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 2ac16535b
+Checksum: PlaceDB: 2fd8b8e3 ConstDB: 0 ShapeSum: 604db5dd RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: e7093645 | NumContArr: 7eee71f2 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2eb499d71
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3069.891 ; gain = 1.984 ; free physical = 124 ; free virtual = 9335
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3380.086 ; gain = 166.945 ; free physical = 691 ; free virtual = 9755
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 2ac16535b
+Phase 2.1 Fix Topology Constraints | Checksum: 2eb499d71
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3069.891 ; gain = 1.984 ; free physical = 116 ; free virtual = 9327
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3380.086 ; gain = 166.945 ; free physical = 689 ; free virtual = 9755
Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 2ac16535b
+Phase 2.2 Pre Route Cleanup | Checksum: 2eb499d71
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3069.891 ; gain = 1.984 ; free physical = 116 ; free virtual = 9327
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3380.086 ; gain = 166.945 ; free physical = 689 ; free virtual = 9755
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 254d5c1cf
+Phase 2.3 Update Timing | Checksum: 1ef724d83
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 117 ; free virtual = 9312
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.554 | TNS=0.000 | WHS=-0.081 | THS=-0.315 |
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 3447.844 ; gain = 234.703 ; free physical = 616 ; free virtual = 9684
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.651 | TNS=0.000 | WHS=-0.121 | THS=-0.525 |
Router Utilization Summary
@@ -562,78 +558,71 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
-Phase 2 Router Initialization | Checksum: 2831a6c13
+Phase 2 Router Initialization | Checksum: 27c63ec9c
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 2831a6c13
+Phase 3 Global Routing | Checksum: 27c63ec9c
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
Phase 4 Initial Routing
Phase 4.1 Initial Net Routing Pass
-Phase 4.1 Initial Net Routing Pass | Checksum: 302d7982a
+Phase 4.1 Initial Net Routing Pass | Checksum: 2a761ba40
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
-Phase 4 Initial Routing | Checksum: 302d7982a
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+Phase 4 Initial Routing | Checksum: 2a761ba40
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
Phase 5 Rip-up And Reroute
Phase 5.1 Global Iteration 0
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.445 | TNS=0.000 | WHS=N/A | THS=N/A |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.634 | TNS=0.000 | WHS=N/A | THS=N/A |
-Phase 5.1 Global Iteration 0 | Checksum: 29e81f649
+Phase 5.1 Global Iteration 0 | Checksum: 2985bcbb7
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
-Phase 5 Rip-up And Reroute | Checksum: 29e81f649
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+Phase 5 Rip-up And Reroute | Checksum: 2985bcbb7
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
Phase 6 Delay and Skew Optimization
Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 2985bcbb7
-Phase 6.1.1 Update Timing
-Phase 6.1.1 Update Timing | Checksum: 2bae5a207
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.451 | TNS=0.000 | WHS=N/A | THS=N/A |
-
-Phase 6.1 Delay CleanUp | Checksum: 2bae5a207
-
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
Phase 6.2 Clock Skew Optimization
-Phase 6.2 Clock Skew Optimization | Checksum: 2bae5a207
+Phase 6.2 Clock Skew Optimization | Checksum: 2985bcbb7
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
-Phase 6 Delay and Skew Optimization | Checksum: 2bae5a207
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+Phase 6 Delay and Skew Optimization | Checksum: 2985bcbb7
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
Phase 7 Post Hold Fix
Phase 7.1 Hold Fix Iter
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.451 | TNS=0.000 | WHS=0.184 | THS=0.000 |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.735 | TNS=0.000 | WHS=0.182 | THS=0.000 |
-Phase 7.1 Hold Fix Iter | Checksum: 27bbfa417
+Phase 7.1 Hold Fix Iter | Checksum: 280f4f3e6
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
-Phase 7 Post Hold Fix | Checksum: 27bbfa417
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+Phase 7 Post Hold Fix | Checksum: 280f4f3e6
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
Phase 8 Route finalize
Router Utilization Summary
- Global Vertical Routing Utilization = 0.0250563 %
- Global Horizontal Routing Utilization = 0.0066636 %
+ Global Vertical Routing Utilization = 0.0172892 %
+ Global Horizontal Routing Utilization = 0.00115664 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -643,50 +632,51 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
-Phase 8 Route finalize | Checksum: 27bbfa417
+Phase 8 Route finalize | Checksum: 280f4f3e6
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
Phase 9 Verifying routed nets
Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 27bbfa417
+Phase 9 Verifying routed nets | Checksum: 280f4f3e6
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 1ecfb1d61
+Phase 10 Depositing Routes | Checksum: 26c826477
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 1ecfb1d61
+Phase 11 Post Process Routing | Checksum: 26c826477
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
Phase 12 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=0.451 | TNS=0.000 | WHS=0.184 | THS=0.000 |
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.735 | TNS=0.000 | WHS=0.182 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 12 Post Router Timing | Checksum: 1ecfb1d61
+Phase 12 Post Router Timing | Checksum: 26c826477
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
-Total Elapsed time in route_design: 5.99 secs
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+Total Elapsed time in route_design: 29.29 secs
Phase 13 Post-Route Event Processing
-Phase 13 Post-Route Event Processing | Checksum: d68495c0
+Phase 13 Post-Route Event Processing | Checksum: 123c604a5
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 132 ; free virtual = 9315
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: d68495c0
+Ending Routing Task | Checksum: 123c604a5
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 132 ; free virtual = 9315
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
-94 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
+97 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 76.961 ; free physical = 132 ; free virtual = 9315
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -701,46 +691,46 @@ INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ho
report_methodology completed successfully
INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
Running report generation with 3 threads.
-INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
-114 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
+118 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
WARNING: [Device 21-2174] Failed to initialize Virtual grid.
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9266
-Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9266
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9266
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9267
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9267
-Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 160 ; free virtual = 9266
-Write Physdb Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 160 ; free virtual = 9266
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Write Physdb Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
-INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 13:37:01 2024...
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:32:37 2024...
#-----------------------------------------------------------
# Vivado v2024.1.2 (64-bit)
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:37:11 2024
-# Process ID: 9169
+# Start of session at: Thu Nov 28 16:35:19 2024
+# Process ID: 16486
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
@@ -755,62 +745,64 @@ INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 13:37:01 2024...
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11482 MB
+# Available Virtual :12272 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
Command: open_checkpoint design_1_wrapper_routed.dcp
Starting open_checkpoint Task
-Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1571.242 ; gain = 0.000 ; free physical = 1525 ; free virtual = 10623
-INFO: [Device 21-403] Loading part xc7z010iclg225-1L
-INFO: [Device 21-9227] Part: xc7z010iclg225-1L does not have CEAM library.
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1922.414 ; gain = 0.000 ; free physical = 1198 ; free virtual = 10305
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1634.656 ; gain = 0.000 ; free physical = 2212 ; free virtual = 11300
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2012.367 ; gain = 0.000 ; free physical = 1859 ; free virtual = 10956
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2024.1.2
INFO: [Project 1-570] Preparing netlist for logic optimization
-Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1985.258 ; gain = 1.000 ; free physical = 1114 ; free virtual = 10220
+Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2080.148 ; gain = 0.000 ; free physical = 1772 ; free virtual = 10869
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
INFO: [Designutils 20-5722] Start Reading Physical Databases.
Reading placement.
-Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
+Read Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
Reading placer database...
-Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
-Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
-Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
+Read Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
+Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
+Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
Reading routing.
-Read RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
-Read Physdb Files: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
-Restored from archive | CPU: 0.050000 secs | Memory: 1.109970 MB |
-Finished XDEF File Restore: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2549.773 ; gain = 5.938 ; free physical = 630 ; free virtual = 9737
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2549.773 ; gain = 0.000 ; free physical = 630 ; free virtual = 9737
+Read RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
+Read Physdb Files: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
+Restored from archive | CPU: 0.050000 secs | Memory: 1.109596 MB |
+Finished XDEF File Restore: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2689.500 ; gain = 6.938 ; free physical = 1253 ; free virtual = 10350
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2689.500 ; gain = 0.000 ; free physical = 1253 ; free virtual = 10350
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Project 1-604] Checkpoint was created with Vivado v2024.1.2 (64-bit) build 5164865
-open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 2556.742 ; gain = 985.500 ; free physical = 630 ; free virtual = 9737
Command: write_bitstream -force design_1_wrapper.bit
-Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010i'
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hogtest/Xilinx/tools/Vivado/2024.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
-ERROR: [DRC NSTD-1] Unspecified I/O Standard: 11 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, btnD, btnC, and led[7:0].
-ERROR: [DRC UCIO-1] Unconstrained Logical Port: 11 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, btnD, btnC, and led[7:0].
-WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
-INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings
+INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
-ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./design_1_wrapper.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
-21 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.
-write_bitstream failed
-write_bitstream: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 2803.207 ; gain = 246.465 ; free physical = 540 ; free virtual = 9648
-ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.
-
-INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 13:37:38 2024...
+24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:35:55 2024...
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_7847.backup.vdi b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_11165.backup.vdi
similarity index 69%
rename from Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_7847.backup.vdi
rename to Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_11165.backup.vdi
index b45f2bc1f8bbdffd13c5a8de5dc1a7d8b230dbdb..ce929408a77507541dc29801d5a8479641cb227d 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_7847.backup.vdi
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_11165.backup.vdi
@@ -3,8 +3,8 @@
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:36:33 2024
-# Process ID: 7847
+# Start of session at: Thu Nov 28 16:16:03 2024
+# Process ID: 11165
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
@@ -19,9 +19,10 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11470 MB
+# Available Virtual :13191 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
+create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1629.680 ; gain = 0.023 ; free physical = 1353 ; free virtual = 12216
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hogtest/Xilinx/tools/Vivado/2024.1/data/ip'.
@@ -32,7 +33,7 @@ INFO: [Device 21-403] Loading part xc7z010iclg225-1L
INFO: [Device 21-9227] Part: xc7z010iclg225-1L does not have CEAM library.
INFO: [Project 1-454] Reading design checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp' for cell 'design_1_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp' for cell 'design_1_i/reg_decalage_0'
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1946.828 ; gain = 0.000 ; free physical = 902 ; free virtual = 10298
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1983.734 ; gain = 0.000 ; free physical = 1024 ; free virtual = 11888
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2024.1
@@ -42,6 +43,7 @@ Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b
Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc] for cell 'design_1_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc:54]
INFO: [Timing 38-2] Deriving generated clocks [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc:54]
+get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2663.152 ; gain = 533.766 ; free physical = 598 ; free virtual = 11462
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc] for cell 'design_1_i/clk_wiz_0/inst'
Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc]
CRITICAL WARNING: [Common 17-69] Command failed: 'R4' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:8]
@@ -57,13 +59,13 @@ CRITICAL WARNING: [Common 17-69] Command failed: 'B22' is not a valid site or pa
CRITICAL WARNING: [Common 17-69] Command failed: 'D22' is not a valid site or package pin name. [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc:34]
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2624.246 ; gain = 0.000 ; free physical = 353 ; free virtual = 9762
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2663.152 ; gain = 0.000 ; free physical = 597 ; free virtual = 11461
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
15 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2624.246 ; gain = 991.535 ; free physical = 353 ; free virtual = 9762
+link_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2663.152 ; gain = 1024.566 ; free physical = 597 ; free virtual = 11461
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010i'
@@ -74,13 +76,13 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2688.277 ; gain = 64.031 ; free physical = 336 ; free virtual = 9745
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2727.184 ; gain = 64.031 ; free physical = 587 ; free virtual = 11451
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 250df70fd
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2688.277 ; gain = 0.000 ; free physical = 335 ; free virtual = 9745
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2727.184 ; gain = 0.000 ; free physical = 587 ; free virtual = 11451
Starting Logic Optimization Task
@@ -89,30 +91,30 @@ Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 250df70fd
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 115 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11148
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 250df70fd
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 115 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11148
Phase 1 Initialization | Checksum: 250df70fd
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 115 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11148
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 250df70fd
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 250df70fd
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Phase 2 Timer Update And Timing Data Collection | Checksum: 250df70fd
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Phase 3 Retarget
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
@@ -120,7 +122,7 @@ INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 250df70fd
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Retarget | Checksum: 250df70fd
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
@@ -129,21 +131,21 @@ Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 250df70fd
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Constant propagation | Checksum: 250df70fd
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Sweep | Checksum: 2690de14c
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
BUFG optimization | Checksum: 2690de14c
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
@@ -151,14 +153,14 @@ Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Shift Register Optimization | Checksum: 2690de14c
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Post Processing Netlist | Checksum: 2690de14c
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
@@ -167,19 +169,19 @@ Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Phase 9.2 Verifying Netlist Connectivity | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Phase 9 Finalization | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Opt_design Change Summary
=========================
@@ -198,24 +200,24 @@ Opt_design Change Summary
Ending Logic Optimization Task | Checksum: 2690de14c
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 2690de14c
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 2690de14c
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
Ending Netlist Obfuscation Task | Checksum: 2690de14c
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2979.973 ; gain = 0.000 ; free physical = 114 ; free virtual = 9435
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3017.910 ; gain = 0.000 ; free physical = 285 ; free virtual = 11149
INFO: [Common 17-83] Releasing license: Implementation
34 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
@@ -226,16 +228,16 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 146 ; free virtual = 9438
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 146 ; free virtual = 9438
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 146 ; free virtual = 9438
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11145
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11145
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11145
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
-Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 144 ; free virtual = 9436
+Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11145
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11145
+Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11146
+Write Physdb Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 281 ; free virtual = 11146
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
@@ -255,54 +257,54 @@ Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9436
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 283 ; free virtual = 11147
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 230d9d08a
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9436
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9436
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 283 ; free virtual = 11147
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 283 ; free virtual = 11147
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ef0c3055
-Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 140 ; free virtual = 9432
+Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 283 ; free virtual = 11147
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 24050593c
-Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 134 ; free virtual = 9429
+Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 282 ; free virtual = 11147
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 24050593c
-Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9437
+Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 282 ; free virtual = 11147
Phase 1 Placer Initialization | Checksum: 24050593c
-Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9437
+Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 282 ; free virtual = 11147
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 2a6b39e8b
-Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9436
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 280 ; free virtual = 11145
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2a217b8a6
-Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9436
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 280 ; free virtual = 11145
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 2a217b8a6
-Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 142 ; free virtual = 9436
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 280 ; free virtual = 11145
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 25c43c498
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.26 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 143 ; free virtual = 9438
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.55 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11142
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
@@ -317,7 +319,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 147 ; free virtual = 9441
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Summary of Physical Synthesis Optimizations
============================================
@@ -341,53 +343,53 @@ Summary of Physical Synthesis Optimizations
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 25c43c498
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.54 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 147 ; free virtual = 9441
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 2.4 Global Placement Core | Checksum: 22fb7f765
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9446
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 2 Global Placement | Checksum: 22fb7f765
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.68 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9446
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11142
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 25ac10194
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.69 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9445
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 277 ; free virtual = 11142
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2278c4f69
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 150 ; free virtual = 9444
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 277 ; free virtual = 11142
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2e6dac979
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9445
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 277 ; free virtual = 11142
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 2e4d933a3
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.71 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 151 ; free virtual = 9445
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 277 ; free virtual = 11142
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 295821a43
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.78 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 295821a43
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 274242b16
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 3 Detail Placement | Checksum: 274242b16
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4 Post Placement Optimization and Clean-Up
@@ -406,30 +408,30 @@ INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximu
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.670 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1b5106441
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1e2cf2294
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.1.1.1 BUFG Insertion | Checksum: 28d31213d
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.84 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9440
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.670. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e50d54a6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.1 Post Commit Optimization | Checksum: 1e50d54a6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1e50d54a6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.3 Placer Reporting
@@ -450,41 +452,41 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
Phase 4.3.1 Print Estimated Congestion | Checksum: 1e50d54a6
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.3 Placer Reporting | Checksum: 1e50d54a6
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ab14c66f
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.85 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
Ending Placer Task | Checksum: 170a2839b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.86 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
68 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
Running report generation with 3 threads.
INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 145 ; free virtual = 9439
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 278 ; free virtual = 11143
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9432
+report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 275 ; free virtual = 11139
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9432
-Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9432
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 137 ; free virtual = 9431
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11139
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11139
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11139
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 136 ; free virtual = 9431
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 136 ; free virtual = 9431
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 135 ; free virtual = 9431
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 134 ; free virtual = 9430
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11139
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11139
+Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11140
+Write Physdb Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 274 ; free virtual = 11140
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
@@ -492,7 +494,7 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc
Starting Initial Update Timing Task
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 266 ; free virtual = 11131
INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.670 | TNS= 0.000 |
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
@@ -500,16 +502,16 @@ INFO: [Common 17-83] Releasing license: Implementation
79 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
-Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 126 ; free virtual = 9421
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 266 ; free virtual = 11131
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 266 ; free virtual = 11131
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 266 ; free virtual = 11131
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 124 ; free virtual = 9420
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 124 ; free virtual = 9420
-Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 124 ; free virtual = 9420
-Write Physdb Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3019.992 ; gain = 0.000 ; free physical = 123 ; free virtual = 9419
+Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 258 ; free virtual = 11123
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 258 ; free virtual = 11123
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 257 ; free virtual = 11123
+Write Physdb Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3057.930 ; gain = 0.000 ; free physical = 257 ; free virtual = 11123
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010i'
@@ -528,25 +530,25 @@ Checksum: PlaceDB: a6bc7693 ConstDB: 0 ShapeSum: 604db5dd RouteDB: 6998572b
Post Restoration Checksum: NetGraph: 6eb65909 | NumContArr: b80e0518 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2ac16535b
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3069.891 ; gain = 1.984 ; free physical = 124 ; free virtual = 9335
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3108.414 ; gain = 2.984 ; free physical = 159 ; free virtual = 11024
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2ac16535b
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3069.891 ; gain = 1.984 ; free physical = 116 ; free virtual = 9327
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3108.414 ; gain = 2.984 ; free physical = 159 ; free virtual = 11024
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2ac16535b
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3069.891 ; gain = 1.984 ; free physical = 116 ; free virtual = 9327
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3108.414 ; gain = 2.984 ; free physical = 159 ; free virtual = 11024
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 254d5c1cf
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 117 ; free virtual = 9312
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.554 | TNS=0.000 | WHS=-0.081 | THS=-0.315 |
@@ -564,22 +566,22 @@ Router Utilization Summary
Phase 2 Router Initialization | Checksum: 2831a6c13
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 3 Global Routing
Phase 3 Global Routing | Checksum: 2831a6c13
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 4 Initial Routing
Phase 4.1 Initial Net Routing Pass
Phase 4.1 Initial Net Routing Pass | Checksum: 302d7982a
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 4 Initial Routing | Checksum: 302d7982a
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 5 Rip-up And Reroute
@@ -590,10 +592,10 @@ INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.445 | TNS=0.000 | WHS
Phase 5.1 Global Iteration 0 | Checksum: 29e81f649
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 5 Rip-up And Reroute | Checksum: 29e81f649
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 6 Delay and Skew Optimization
@@ -602,20 +604,20 @@ Phase 6.1 Delay CleanUp
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2bae5a207
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.451 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 6.1 Delay CleanUp | Checksum: 2bae5a207
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 6.2 Clock Skew Optimization
Phase 6.2 Clock Skew Optimization | Checksum: 2bae5a207
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 6 Delay and Skew Optimization | Checksum: 2bae5a207
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 129 ; free virtual = 9312
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 7 Post Hold Fix
@@ -624,10 +626,10 @@ INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.451 | TNS=0.000 | WHS
Phase 7.1 Hold Fix Iter | Checksum: 27bbfa417
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 7 Post Hold Fix | Checksum: 27bbfa417
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 8 Route finalize
@@ -645,24 +647,24 @@ Router Utilization Summary
Phase 8 Route finalize | Checksum: 27bbfa417
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 9 Verifying routed nets
Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 27bbfa417
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 1ecfb1d61
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 11 Post Process Routing
Phase 11 Post Process Routing | Checksum: 1ecfb1d61
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Phase 12 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.451 | TNS=0.000 | WHS=0.184 | THS=0.000 |
@@ -670,23 +672,23 @@ INFO: [Route 35-57] Estimated Timing Summary | WNS=0.451 | TNS=0.000 | WHS=0.1
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 12 Post Router Timing | Checksum: 1ecfb1d61
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 128 ; free virtual = 9311
-Total Elapsed time in route_design: 5.99 secs
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
+Total Elapsed time in route_design: 10.29 secs
Phase 13 Post-Route Event Processing
Phase 13 Post-Route Event Processing | Checksum: d68495c0
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 132 ; free virtual = 9315
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
INFO: [Route 35-16] Router Completed Successfully
Ending Routing Task | Checksum: d68495c0
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 29.047 ; free physical = 132 ; free virtual = 9315
+Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 3135.477 ; gain = 30.047 ; free physical = 147 ; free virtual = 11012
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
94 Infos, 0 Warnings, 11 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.953 ; gain = 76.961 ; free physical = 132 ; free virtual = 9315
+route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3135.477 ; gain = 77.547 ; free physical = 147 ; free virtual = 11012
INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -705,9 +707,9 @@ INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
Running report generation with 3 threads.
-INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
@@ -722,15 +724,15 @@ INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file desig
WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
WARNING: [Device 21-2174] Failed to initialize Virtual grid.
INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9266
-Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9266
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9266
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 217 ; free virtual = 10971
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 217 ; free virtual = 10971
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 217 ; free virtual = 10971
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9267
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 162 ; free virtual = 9267
-Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 160 ; free virtual = 9266
-Write Physdb Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3199.871 ; gain = 0.000 ; free physical = 160 ; free virtual = 9266
+Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 216 ; free virtual = 10971
+Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 216 ; free virtual = 10971
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 215 ; free virtual = 10970
+Write Physdb Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3240.363 ; gain = 0.000 ; free physical = 215 ; free virtual = 10970
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
-INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 13:37:01 2024...
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:16:50 2024...
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_14663.backup.vdi b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_14663.backup.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..c9a5e26d1fe31d2c1a1ee239f2bd49f98c245ce1
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_14663.backup.vdi
@@ -0,0 +1,726 @@
+#-----------------------------------------------------------
+# Vivado v2024.1.2 (64-bit)
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
+# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
+# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
+# Start of session at: Thu Nov 28 16:31:41 2024
+# Process ID: 14663
+# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
+# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
+# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
+# Journal file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/vivado.jou
+# Running On :hogtest
+# Platform :unknown
+# Operating System :unknown
+# Processor Detail :11th Gen Intel(R) Core(TM) i5-1140G7 @ 1.10GHz
+# CPU Frequency :1804.800 MHz
+# CPU Physical cores:4
+# CPU Logical cores :8
+# Host memory :8296 MB
+# Swap memory :8296 MB
+# Total Virtual :16593 MB
+# Available Virtual :12349 MB
+#-----------------------------------------------------------
+source design_1_wrapper.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hogtest/Xilinx/tools/Vivado/2024.1/data/ip'.
+Command: link_design -top design_1_wrapper -part xc7a200tsbg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
+INFO: [Project 1-454] Reading design checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp' for cell 'design_1_i/clk_wiz_0'
+INFO: [Project 1-454] Reading design checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.dcp' for cell 'design_1_i/reg_decalage_0'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2038.219 ; gain = 0.000 ; free physical = 1845 ; free virtual = 10861
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2024.1.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
+Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_board.xdc] for cell 'design_1_i/clk_wiz_0/inst'
+Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc] for cell 'design_1_i/clk_wiz_0/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc:54]
+INFO: [Timing 38-2] Deriving generated clocks [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc:54]
+Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc] for cell 'design_1_i/clk_wiz_0/inst'
+Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc]
+Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Nexys-Video-Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2763.770 ; gain = 0.000 ; free physical = 1299 ; free virtual = 10336
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+15 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2827.801 ; gain = 64.031 ; free physical = 1311 ; free virtual = 10348
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2827.801 ; gain = 0.000 ; free physical = 1311 ; free virtual = 10348
+
+Starting Logic Optimization Task
+
+Phase 1 Initialization
+
+Phase 1.1 Core Generation And Design Setup
+Phase 1.1 Core Generation And Design Setup | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10042
+
+Phase 1.2 Setup Constraints And Sort Netlist
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10042
+Phase 1 Initialization | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10042
+
+Phase 2 Timer Update And Timing Data Collection
+
+Phase 2.1 Timer Update
+Phase 2.1 Timer Update | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10041
+
+Phase 2.2 Timing Data Collection
+Phase 2.2 Timing Data Collection | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10041
+Phase 2 Timer Update And Timing Data Collection | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10041
+
+Phase 3 Retarget
+INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 3 Retarget | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Retarget | Checksum: 256e02795
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 4 Constant propagation | Checksum: 256e02795
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Constant propagation | Checksum: 256e02795
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 5 Sweep
+Phase 5 Sweep | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Sweep | Checksum: 26f0e97e4
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 6 BUFG optimization
+Phase 6 BUFG optimization | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+BUFG optimization | Checksum: 26f0e97e4
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 7 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 7 Shift Register Optimization | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Shift Register Optimization | Checksum: 26f0e97e4
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 8 Post Processing Netlist
+Phase 8 Post Processing Netlist | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Post Processing Netlist | Checksum: 26f0e97e4
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+
+Phase 9 Finalization
+
+Phase 9.1 Finalizing Design Cores and Updating Shapes
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+
+Phase 9.2 Verifying Netlist Connectivity
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Phase 9 Finalization | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 0 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 0 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+Ending Logic Optimization Task | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+Ending Netlist Obfuscation Task | Checksum: 26f0e97e4
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3118.496 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10043
+INFO: [Common 17-83] Releasing license: Implementation
+35 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
+INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
+Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10042
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10042
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10042
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10043
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10043
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 999 ; free virtual = 10043
+Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 1004 ; free virtual = 10048
+INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-83] Releasing license: Implementation
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Starting Placer Task
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 998 ; free virtual = 10042
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 236da8722
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 998 ; free virtual = 10042
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 998 ; free virtual = 10042
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1bc38e117
+
+Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 984 ; free virtual = 10031
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 1eb442b17
+
+Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 984 ; free virtual = 10031
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 1eb442b17
+
+Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:00.29 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 984 ; free virtual = 10031
+Phase 1 Placer Initialization | Checksum: 1eb442b17
+
+Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 983 ; free virtual = 10031
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1c493d4b9
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 979 ; free virtual = 10027
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2495728f0
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 979 ; free virtual = 10027
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 2495728f0
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.34 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 979 ; free virtual = 10027
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 236cb21d7
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 943 ; free virtual = 9992
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 0 net or LUT. Breaked 0 LUT, combined 0 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 939 ; free virtual = 9991
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 0 | 0 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 236cb21d7
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+Phase 2.4 Global Placement Core | Checksum: 1ef8b2f73
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.88 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+Phase 2 Global Placement | Checksum: 1ef8b2f73
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.88 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 1d486398a
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.9 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2966bbfaa
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.92 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1ff89d11b
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.93 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2376f352c
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.93 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 938 ; free virtual = 9990
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1e3efe8b9
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1e3efe8b9
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 21c0a8caa
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 3 Detail Placement | Checksum: 21c0a8caa
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 1f5099abb
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.716 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 1654a0736
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 19a6df91d
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1f5099abb
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.716. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1ef975e62
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4.1 Post Commit Optimization | Checksum: 1ef975e62
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1ef975e62
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1ef975e62
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4.3 Placer Reporting | Checksum: 1ef975e62
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b59ed02b
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Ending Placer Task | Checksum: 128415a24
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+70 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
+INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
+INFO: [Vivado 12-24828] Executing command : report_io -file design_1_wrapper_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.716 | TNS= 0.000 |
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+82 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PlaceDB: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 929 ; free virtual = 9981
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 921 ; free virtual = 9974
+Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3206.539 ; gain = 0.000 ; free physical = 921 ; free virtual = 9974
+INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 2fd8b8e3 ConstDB: 0 ShapeSum: 604db5dd RouteDB: 981aeb64
+Post Restoration Checksum: NetGraph: e7093645 | NumContArr: 7eee71f2 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Phase 1 Build RT Design | Checksum: 2eb499d71
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3380.086 ; gain = 166.945 ; free physical = 691 ; free virtual = 9755
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 2eb499d71
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3380.086 ; gain = 166.945 ; free physical = 689 ; free virtual = 9755
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 2eb499d71
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:28 . Memory (MB): peak = 3380.086 ; gain = 166.945 ; free physical = 689 ; free virtual = 9755
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1ef724d83
+
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 3447.844 ; gain = 234.703 ; free physical = 616 ; free virtual = 9684
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.651 | TNS=0.000 | WHS=-0.121 | THS=-0.525 |
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 15
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 15
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 27c63ec9c
+
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+
+Phase 3 Global Routing
+Phase 3 Global Routing | Checksum: 27c63ec9c
+
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+
+Phase 4 Initial Routing
+
+Phase 4.1 Initial Net Routing Pass
+Phase 4.1 Initial Net Routing Pass | Checksum: 2a761ba40
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+Phase 4 Initial Routing | Checksum: 2a761ba40
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+
+Phase 5 Rip-up And Reroute
+
+Phase 5.1 Global Iteration 0
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.634 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Global Iteration 0 | Checksum: 2985bcbb7
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+Phase 5 Rip-up And Reroute | Checksum: 2985bcbb7
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+
+Phase 6 Delay and Skew Optimization
+
+Phase 6.1 Delay CleanUp
+Phase 6.1 Delay CleanUp | Checksum: 2985bcbb7
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+
+Phase 6.2 Clock Skew Optimization
+Phase 6.2 Clock Skew Optimization | Checksum: 2985bcbb7
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+Phase 6 Delay and Skew Optimization | Checksum: 2985bcbb7
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9681
+
+Phase 7 Post Hold Fix
+
+Phase 7.1 Hold Fix Iter
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.735 | TNS=0.000 | WHS=0.182 | THS=0.000 |
+
+Phase 7.1 Hold Fix Iter | Checksum: 280f4f3e6
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+Phase 7 Post Hold Fix | Checksum: 280f4f3e6
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+
+Phase 8 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0172892 %
+ Global Horizontal Routing Utilization = 0.00115664 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 8 Route finalize | Checksum: 280f4f3e6
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 613 ; free virtual = 9681
+
+Phase 9 Verifying routed nets
+
+ Verification completed successfully
+Phase 9 Verifying routed nets | Checksum: 280f4f3e6
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+
+Phase 10 Depositing Routes
+Phase 10 Depositing Routes | Checksum: 26c826477
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+
+Phase 11 Post Process Routing
+Phase 11 Post Process Routing | Checksum: 26c826477
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+
+Phase 12 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.735 | TNS=0.000 | WHS=0.182 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 12 Post Router Timing | Checksum: 26c826477
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+Total Elapsed time in route_design: 29.29 secs
+
+Phase 13 Post-Route Event Processing
+Phase 13 Post-Route Event Processing | Checksum: 123c604a5
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+INFO: [Route 35-16] Router Completed Successfully
+Ending Routing Task | Checksum: 123c604a5
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 3455.234 ; gain = 242.094 ; free physical = 612 ; free virtual = 9680
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+97 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
+INFO: [Vivado 12-24828] Executing command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
+Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpt.
+report_drc completed successfully
+INFO: [Vivado 12-24828] Executing command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
+Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
+Running report generation with 3 threads.
+INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [Vivado 12-24828] Executing command : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
+INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Vivado 12-24828] Executing command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
+Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+118 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
+WARNING: [Device 21-9320] Failed to find the Oracle tile group with name 'HSR_BOUNDARY_TOP'. This is required for Clock regions and Virtual grid.
+WARNING: [Device 21-2174] Failed to initialize Virtual grid.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+Write Physdb Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3543.277 ; gain = 0.000 ; free physical = 614 ; free virtual = 9683
+INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:32:37 2024...
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt
index e1dbd00a46e33d7cddd96202697efdd7c9bdee44..7a43862aac32cb6a32d2ecb71d134eb66944fd22 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:37:00 2024
+| Date : Thu Nov 28 16:32:36 2024
| Host : hogtest running 64-bit unknown
| Command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
| Design : design_1_wrapper
-| Device : 7z010i-clg225
-| Speed File : -1L PRODUCTION 1.12 2019-11-22
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx
index acbced8a8ff0941943cbdc3133ebb47580d968c0..eec61b99012c1ebf0c84877402a8d421f199d22c 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_bus_skew_routed.rpx differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt
index 38d42dfd1c0ba25ef7b3120bedcc70b212dc0bcf..401a6be05dc71daf82c9037985646d97492a992b 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt
@@ -1,15 +1,14 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:37:01 2024
-| Host : hogtest running 64-bit unknown
-| Command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
-| Design : design_1_wrapper
-| Device : 7z010i-clg225
-| Speed File : -1L PRODUCTION 1.12 2019-11-22
-| Temperature Grade : I
-| Design State : Routed
---------------------------------------------------------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+| Date : Thu Nov 28 16:32:37 2024
+| Host : hogtest running 64-bit unknown
+| Command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
+| Design : design_1_wrapper
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
Clock Utilization Report
@@ -22,7 +21,8 @@ Table of Contents
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Device Cell Placement Summary for Global Clock g1
-8. Clock Region Cell Placement per Global Clock: Region X1Y0
+8. Clock Region Cell Placement per Global Clock: Region X0Y1
+9. Clock Region Cell Placement per Global Clock: Region X1Y2
1. Clock Primitive Utilization
------------------------------
@@ -31,12 +31,12 @@ Table of Contents
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
-| BUFH | 0 | 48 | 0 | 0 | 0 |
-| BUFIO | 0 | 8 | 0 | 0 | 0 |
-| BUFMR | 0 | 4 | 0 | 0 | 0 |
-| BUFR | 0 | 8 | 0 | 0 | 0 |
-| MMCM | 0 | 2 | 0 | 0 | 0 |
-| PLL | 1 | 2 | 0 | 0 | 0 |
+| BUFH | 0 | 120 | 0 | 0 | 0 |
+| BUFIO | 0 | 40 | 0 | 0 | 0 |
+| BUFMR | 0 | 20 | 0 | 0 | 0 |
+| BUFR | 0 | 40 | 0 | 0 | 0 |
+| MMCM | 0 | 10 | 0 | 0 | 0 |
+| PLL | 1 | 10 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
@@ -59,8 +59,8 @@ Table of Contents
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------------+
-| src0 | g0 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X0Y0 | X1Y0 | 1 | 0 | 2.500 | clk_out1_design_1_clk_wiz_0_1 | design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0 | design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1 |
-| src1 | g1 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X0Y0 | X1Y0 | 1 | 0 | 10.000 | clkfbout_design_1_clk_wiz_0_1 | design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT | design_1_i/clk_wiz_0/inst/clkfbout_design_1_clk_wiz_0_1 |
+| src0 | g0 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X1Y2 | X1Y2 | 1 | 0 | 2.500 | clk_out1_design_1_clk_wiz_0_1 | design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0 | design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1 |
+| src1 | g1 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | clkfbout_design_1_clk_wiz_0_1 | design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT | design_1_i/clk_wiz_0/inst/clkfbout_design_1_clk_wiz_0_1 |
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+-------------------------------+---------------------------------------------------+---------------------------------------------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -74,10 +74,16 @@ Table of Contents
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
-| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
-| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 11 | 1100 | 11 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
-| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
-| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 800 | 0 | 60 | 0 | 30 | 0 | 60 |
+| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 11 | 4200 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3600 | 0 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
+| X1Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4000 | 0 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
+| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 0 | 2550 | 0 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
+| X1Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
@@ -89,6 +95,9 @@ All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
+| Y4 | 0 | 0 |
+| Y3 | 0 | 0 |
+| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 0 | 0 |
+----+----+----+
@@ -108,12 +117,15 @@ All Modules
**** GT Loads column represents load cell count of GT types
-+----+----+-----+-----------------------+
-| | X0 | X1 | HORIZONTAL PROG DELAY |
-+----+----+-----+-----------------------+
-| Y1 | 0 | 0 | - |
-| Y0 | 0 | 11 | 0 |
-+----+----+-----+-----------------------+
++----+-----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+-----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 0 | - |
+| Y1 | 11 | 0 | 0 |
+| Y0 | 0 | 0 | - |
++----+-----+----+-----------------------+
7. Device Cell Placement Summary for Global Clock g1
@@ -133,18 +145,33 @@ All Modules
+----+----+----+-----------------------+
| | X0 | X1 | HORIZONTAL PROG DELAY |
+----+----+----+-----------------------+
+| Y4 | 0 | 0 | - |
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
| Y1 | 0 | 0 | - |
-| Y0 | 0 | 1 | 0 |
+| Y0 | 0 | 0 | - |
+----+----+----+-----------------------+
-8. Clock Region Cell Placement per Global Clock: Region X1Y0
+8. Clock Region Cell Placement per Global Clock: Region X0Y1
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+------------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+------------------------------------+
+| g0 | n/a | BUFG/O | None | 11 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk_out1 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+------------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+9. Clock Region Cell Placement per Global Clock: Region X1Y2
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
-| g0 | n/a | BUFG/O | None | 11 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/clk_wiz_0/inst/clk_out1 |
| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | design_1_i/clk_wiz_0/inst/clkfbout_buf_design_1_clk_wiz_0_1 |
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
@@ -160,11 +187,11 @@ set_property LOC BUFGCTRL_X0Y0 [get_cells design_1_i/clk_wiz_0/inst/clkout1_buf]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
-set_property LOC IOB_X0Y28 [get_ports clk]
+set_property LOC IOB_X1Y124 [get_ports clk]
# Clock net "design_1_i/clk_wiz_0/inst/clk_out1" driven by instance "design_1_i/clk_wiz_0/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_design_1_i/clk_wiz_0/inst/clk_out1}
add_cells_to_pblock [get_pblocks {CLKAG_design_1_i/clk_wiz_0/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="design_1_i/clk_wiz_0/inst/clk_out1"}]]]
-resize_pblock [get_pblocks {CLKAG_design_1_i/clk_wiz_0/inst/clk_out1}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
+resize_pblock [get_pblocks {CLKAG_design_1_i/clk_wiz_0/inst/clk_out1}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}
#endgroup
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_control_sets_placed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_control_sets_placed.rpt
index bf6f5b49dc469063ce5a8571257824f9da0f0ae4..417d7ed756d3c2d02fefbd564917177cea430e80 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_control_sets_placed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_control_sets_placed.rpt
@@ -1,11 +1,11 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:36:53 2024
+| Date : Thu Nov 28 16:32:05 2024
| Host : hogtest running 64-bit unknown
| Command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
| Design : design_1_wrapper
-| Device : xc7z010i
+| Device : xc7a200t
---------------------------------------------------------------------------------------------------------------------------------------------
Control Set Information
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.pb b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.pb
index 0158a2ad826bcd75c8436a6a29252340aee67559..8ebaa788697aa1bbb8ab2b30bd329d93fcb4a328 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.pb and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt
index fbdcca330e30effcdf6cda9c2ba0c1bb03938ee4..727796790c5f459426ff79f9811217ba86c060c9 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:36:51 2024
+| Date : Thu Nov 28 16:32:02 2024
| Host : hogtest running 64-bit unknown
| Command : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
| Design : design_1_wrapper
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -24,30 +24,12 @@ Table of Contents
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
- Violations found: 3
-+--------+------------------+----------------------------+------------+
-| Rule | Severity | Description | Violations |
-+--------+------------------+----------------------------+------------+
-| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
-| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
-| ZPS7-1 | Warning | PS7 block required | 1 |
-+--------+------------------+----------------------------+------------+
+ Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
2. REPORT DETAILS
-----------------
-NSTD-1#1 Critical Warning
-Unspecified I/O Standard
-11 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btnC, btnD, clk, led[7:0].
-Related violations: <none>
-
-UCIO-1#1 Critical Warning
-Unconstrained Logical Port
-11 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btnC, btnD, clk, led[7:0].
-Related violations: <none>
-
-ZPS7-1#1 Warning
-PS7 block required
-The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
-Related violations: <none>
-
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpx b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpx
index 0d00fa0e1d8f41078489865417d58b7fee2b44a9..9b5e25b7109e6691ab1f0e6668ebd5d443d0d306 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpx and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_opted.rpx differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.pb b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.pb
index 0158a2ad826bcd75c8436a6a29252340aee67559..8ebaa788697aa1bbb8ab2b30bd329d93fcb4a328 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.pb and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpt
index fad725adc980b4d0c37f6194ebfdc299220b8679..fb47850eb23b0d68565b49894b7e9d418e89b10d 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:37:00 2024
+| Date : Thu Nov 28 16:32:35 2024
| Host : hogtest running 64-bit unknown
| Command : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
| Design : design_1_wrapper
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -24,30 +24,12 @@ Table of Contents
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
- Violations found: 3
-+--------+------------------+----------------------------+------------+
-| Rule | Severity | Description | Violations |
-+--------+------------------+----------------------------+------------+
-| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 |
-| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 |
-| ZPS7-1 | Warning | PS7 block required | 1 |
-+--------+------------------+----------------------------+------------+
+ Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
2. REPORT DETAILS
-----------------
-NSTD-1#1 Critical Warning
-Unspecified I/O Standard
-11 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btnC, btnD, clk, led[7:0].
-Related violations: <none>
-
-UCIO-1#1 Critical Warning
-Unconstrained Logical Port
-11 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: btnC, btnD, clk, led[7:0].
-Related violations: <none>
-
-ZPS7-1#1 Warning
-PS7 block required
-The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
-Related violations: <none>
-
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpx b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpx
index 34e6afbf76e39d0f481fb71a20e1c899783ff35f..ce02959879e232dd1fa66762e24c5f225df53f37 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpx and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_drc_routed.rpx differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_io_placed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_io_placed.rpt
index 0233ef690cd1c810035d35b0f0282e16d3ca08dc..e00756bcda2c1bc0dfb1e4bd3effcf78821c4279 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_io_placed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_io_placed.rpt
@@ -1,15 +1,15 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:36:53 2024
+| Date : Thu Nov 28 16:32:05 2024
| Host : hogtest running 64-bit unknown
| Command : report_io -file design_1_wrapper_io_placed.rpt
| Design : design_1_wrapper
-| Device : xc7z010i
-| Speed File : -1L
-| Package : clg225
-| Package Version : FINAL 2012-11-02
-| Package Pin Delay Version : VERS. 2.0 2012-11-02
+| Device : xc7a200t
+| Speed File : -1
+| Package : sbg484
+| Package Version : FINAL 2012-06-12
+| Package Pin Delay Version : VERS. 2.0 2012-06-12
----------------------------------------------------------------------------------------------------------------------------------------------------------
IO Information
@@ -32,235 +32,494 @@ Table of Contents
2. IO Assignments by Package Pin
--------------------------------
-+------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
-| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
-+------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
-| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| A2 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | | | |
-| A3 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | |
-| A4 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | | | |
-| A5 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | | | |
-| A6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
-| A7 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | | | |
-| A8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | | | |
-| A9 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | | | |
-| A10 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | | | |
-| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| A12 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | | | |
-| A13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | | | |
-| A14 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | | | |
-| A15 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | | | |
-| B1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | | | |
-| B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | | | |
-| B3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
-| B4 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | | | |
-| B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | | | |
-| B6 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | | | |
-| B7 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | | | |
-| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| B9 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | | | |
-| B10 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | | | |
-| B11 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | | | |
-| B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | | | |
-| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
-| B14 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | | | |
-| B15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | | | |
-| C1 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | | | |
-| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | | | |
-| C3 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | | | |
-| C4 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | | | |
-| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| C6 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | | | |
-| C7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | | | |
-| C8 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | | | |
-| C9 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | | | |
-| C10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
-| C11 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | |
-| C12 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | | | |
-| C13 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | | | |
-| C14 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | | | |
-| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| D1 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | | | |
-| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| D3 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | | | |
-| D4 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | | | |
-| D5 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
-| D6 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | | | |
-| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
-| D8 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | | | |
-| D9 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | | | |
-| D10 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | | | |
-| D11 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | | | |
-| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| D13 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | | | |
-| D14 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | | | |
-| D15 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | | | |
-| E1 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | | | |
-| E2 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | | | |
-| E3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | | | |
-| E4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
-| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| E6 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
-| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| E8 | | | RSVDGND | GND | | | | | | | | | | | | | | | |
-| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| E10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
-| E11 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | |
-| E12 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | |
-| E13 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | |
-| E14 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
-| E15 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | | | |
-| F1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
-| F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | | | |
-| F3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | | | |
-| F4 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | |
-| F5 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | |
-| F6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
-| F7 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
-| F8 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
-| F9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
-| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| F11 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.20 | | | | | | | | |
-| F12 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | |
-| F13 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | |
-| F14 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | |
-| F15 | btnU | High Range | IO_L5N_T0_AD9N_35 | INPUT | LVCMOS12 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
-| G1 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | | | |
-| G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | | | |
-| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| G4 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | |
-| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| G6 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
-| G7 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
-| G8 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
-| G9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
-| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
-| G11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| G12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| G14 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | |
-| G15 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | |
-| H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | | | |
-| H2 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | | | |
-| H3 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | | | |
-| H4 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | |
-| H5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
-| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| H7 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
-| H8 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
-| H9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
-| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| H11 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| H12 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| H13 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| H14 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
-| H15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.20 | | | | | | | | |
-| J1 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | | | |
-| J2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
-| J3 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | | | |
-| J4 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | |
-| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| J6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
-| J7 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
-| J8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
-| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
-| J11 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
-| J12 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | |
-| J13 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| J14 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| J15 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| K1 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | | | |
-| K2 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | | | |
-| K3 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | | | |
-| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| K5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
-| K6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
-| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| K8 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
-| K9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
-| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| K11 | clk | High Range | IO_L11P_T1_SRCC_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | |
-| K12 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
-| K13 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
-| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| K15 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| L2 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | | | |
-| L3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | | | |
-| L4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | | | |
-| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| L6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
-| L7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
-| L8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
-| L9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
-| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
-| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| L12 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
-| L13 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
-| L14 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
-| L15 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
-| M1 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | | | |
-| M2 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | | | |
-| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
-| M4 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | | | |
-| M5 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | | | |
-| M6 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | | | |
-| M7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
-| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| M9 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
-| M10 | led[5] | High Range | IO_L21P_T3_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| M11 | led[4] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| M12 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
-| M13 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | |
-| M14 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
-| M15 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
-| N1 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | | | |
-| N2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | | | |
-| N3 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | | | |
-| N4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | | | |
-| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| N6 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | | | |
-| N7 | led[3] | High Range | IO_L22P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| N8 | led[2] | High Range | IO_L22N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| N9 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
-| N10 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | |
-| N11 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
-| N12 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
-| N13 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
-| N14 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
-| N15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| P1 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | | | |
-| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| P3 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | | | |
-| P4 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | | | |
-| P5 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | | | |
-| P6 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | | | |
-| P7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | |
-| P8 | led[1] | High Range | IO_L23P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| P9 | led[0] | High Range | IO_L23N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| P10 | btnD | High Range | IO_L24P_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | |
-| P11 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
-| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| P13 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
-| P14 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
-| P15 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
-| R1 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | | | |
-| R2 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | | | |
-| R3 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | | | |
-| R4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
-| R5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | | | |
-| R6 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | | | |
-| R7 | led[7] | High Range | IO_L20P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| R8 | led[6] | High Range | IO_L20N_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
-| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| R10 | btnC | High Range | IO_L24N_T3_34 | INPUT | LVCMOS18* | 34 | | | | NONE | | UNFIXED | | | | NONE | | | |
-| R11 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
-| R12 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
-| R13 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
-| R14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | |
-| R15 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
-+------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
+| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
+| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.20 | | | | | | | | |
+| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA21 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
+| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
+| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.20 | | | | | | | | |
+| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B22 | btnC | High Range | IO_L20N_T3_16 | INPUT | LVCMOS12 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| C2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
+| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
+| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
+| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.20 | | | | | | | | |
+| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
+| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
+| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.20 | | | | | | | | |
+| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D22 | btnD | High Range | IO_L22N_T3_16 | INPUT | LVCMOS12 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
+| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.20 | | | | | | | | |
+| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
+| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
+| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
+| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F15 | btnU | High Range | IO_0_16 | INPUT | LVCMOS12 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
+| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
+| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 1.20 | | | | | | | | |
+| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
+| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
+| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
+| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
+| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
+| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
+| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
+| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| P19 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | clk | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
+| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | |
+| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| T14 | led[0] | High Range | IO_L15P_T2_DQS_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T15 | led[1] | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T16 | led[2] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T20 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | |
+| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U16 | led[3] | High Range | IO_L17N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U21 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V15 | led[4] | High Range | IO_L14N_T2_SRCC_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W15 | led[6] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W16 | led[5] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| W22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 2.50 | | | | | | | | |
+| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y13 | led[7] | High Range | IO_L5P_T0_13 | OUTPUT | LVCMOS25 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt
index d71bb8c272e67c082ff0ed23eb4e60be30028a09..1646f3a262e87cf25e5878f5ecb76ce758dfd820 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:37:00 2024
+| Date : Thu Nov 28 16:32:36 2024
| Host : hogtest running 64-bit unknown
| Command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
| Design : design_1_wrapper
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Fully Routed
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp
index 6d18e1f777d048584ab936361bc020e1ac37847e..b7fad007160f2be4db7032e85b3d10b13da99c1a 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_opt.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp
index 97494801eb6e9c500ad07b2f9a662255aa2867d7..ba07e8c183a39bcbbececd336016786087209202 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_physopt.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp
index 957be15beba8652c2aa836626143e386e2ddf61a..04728961c1574e82aa6bfb215e19a00b4f6b093c 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_placed.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpt
index eed11a9021dc5951992319dd9c59cdc9f88c3e66..196e7cf4c634c539ffebd3e578a05211761163a7 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpt
@@ -1,13 +1,13 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:37:00 2024
+| Date : Thu Nov 28 16:32:36 2024
| Host : hogtest running 64-bit unknown
| Command : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
| Design : design_1_wrapper
-| Device : xc7z010iclg225-1L
+| Device : xc7a200tsbg484-1
| Design State : routed
-| Grade : industrial
+| Grade : commercial
| Process : typical
| Characterization : Production
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
-| Total On-Chip Power (W) | 0.222 |
+| Total On-Chip Power (W) | 0.297 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
-| Dynamic (W) | 0.143 |
-| Device Static (W) | 0.079 |
-| Effective TJA (C/W) | 11.5 |
-| Max Ambient (C) | 97.4 |
-| Junction Temperature (C) | 27.6 |
+| Dynamic (W) | 0.161 |
+| Device Static (W) | 0.135 |
+| Effective TJA (C/W) | 3.3 |
+| Max Ambient (C) | 84.0 |
+| Junction Temperature (C) | 26.0 |
| Confidence Level | Medium |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,16 +52,16 @@ Table of Contents
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
-| Clocks | 0.002 | 5 | --- | --- |
+| Clocks | 0.004 | 5 | --- | --- |
| Slice Logic | <0.001 | 27 | --- | --- |
-| LUT as Logic | <0.001 | 6 | 17600 | 0.03 |
-| Register | <0.001 | 11 | 35200 | 0.03 |
+| LUT as Logic | <0.001 | 6 | 133800 | <0.01 |
+| Register | <0.001 | 11 | 267600 | <0.01 |
| Others | 0.000 | 7 | --- | --- |
| Signals | <0.001 | 15 | --- | --- |
-| PLL | 0.121 | 1 | 2 | 50.00 |
-| I/O | 0.019 | 12 | 54 | 22.22 |
-| Static Power | 0.079 | | | |
-| Total | 0.222 | | | |
+| PLL | 0.122 | 1 | 10 | 10.00 |
+| I/O | 0.034 | 12 | 285 | 4.21 |
+| Static Power | 0.135 | | | |
+| Total | 0.297 | | | |
+----------------+-----------+----------+-----------+-----------------+
@@ -71,26 +71,19 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Vccint | 0.950 | 0.018 | 0.015 | 0.002 | NA | Unspecified | NA |
-| Vccaux | 1.800 | 0.067 | 0.062 | 0.005 | NA | Unspecified | NA |
+| Vccint | 1.000 | 0.049 | 0.018 | 0.031 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.092 | 0.062 | 0.031 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vcco18 | 1.800 | 0.010 | 0.009 | 0.001 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.018 | 0.013 | 0.005 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vccbram | 0.950 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vccpint | 1.000 | 0.012 | 0.000 | 0.012 | NA | Unspecified | NA |
-| Vccpaux | 1.800 | 0.009 | 0.000 | 0.009 | NA | Unspecified | NA |
-| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA |
-| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
@@ -116,16 +109,16 @@ Table of Contents
2.1 Environment
---------------
-+-----------------------+------------------------+
-| Ambient Temp (C) | 25.0 |
-| ThetaJA (C/W) | 11.5 |
-| Airflow (LFM) | 250 |
-| Heat Sink | none |
-| ThetaSA (C/W) | 0.0 |
-| Board Selection | medium (10"x10") |
-| # of Board Layers | 8to11 (8 to 11 Layers) |
-| Board Temperature (C) | 25.0 |
-+-----------------------+------------------------+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 3.3 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
2.2 Clock Constraints
@@ -149,12 +142,12 @@ Table of Contents
+--------------------+-----------+
| Name | Power (W) |
+--------------------+-----------+
-| design_1_wrapper | 0.143 |
-| design_1_i | 0.123 |
-| clk_wiz_0 | 0.122 |
-| inst | 0.122 |
-| reg_decalage_0 | 0.002 |
-| inst | 0.002 |
+| design_1_wrapper | 0.161 |
+| design_1_i | 0.127 |
+| clk_wiz_0 | 0.123 |
+| inst | 0.123 |
+| reg_decalage_0 | 0.004 |
+| inst | 0.004 |
+--------------------+-----------+
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpx b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpx
index d1f974cccd203d006091f36bfdd94cccad5a8174..0c946a14257ad268cb4bcfc2f54a0c845dc25b6d 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpx and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_routed.rpx differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_summary_routed.pb b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_summary_routed.pb
index 9731b00def9d85872b747dc9e934ddf0153f7844..1a18971ee35c84cf12a96d71d691bb05423b87b2 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_summary_routed.pb and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_power_summary_routed.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp
index 34f34d62bb0851da48de07d527e33e0c65381988..87ac018221fe641f3ceb11a7772e0da69773ef6e 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_routed.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.pb b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.pb
index d1881bb04cf9702e7b3f9302245c0ff3c34c6fc4..d763a1db0b64229fab618413707f3e369e060576 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.pb and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt
index 0bb7e7eb025e0e98af18c3d6f22c6986daa586e9..c87471cae512b2a61fe29b9ae8cc10c00000186d 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:37:00 2024
+| Date : Thu Nov 28 16:32:36 2024
| Host : hogtest running 64-bit unknown
| Command : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design : design_1_wrapper
-| Device : 7z010i-clg225
-| Speed File : -1L PRODUCTION 1.12 2019-11-22
+| Device : 7a200t-sbg484
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -138,7 +138,7 @@ Table of Contents
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
- 0.477 0.000 0 22 0.201 0.000 0 22 0.345 0.000 0 17
+ 0.738 0.000 0 22 0.186 0.000 0 22 0.345 0.000 0 17
All user specified timing constraints are met.
@@ -164,7 +164,7 @@ clk {0.000 5.000} 10.000 100.000
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk 3.000 0.000 0 1
- clk_out1_design_1_clk_wiz_0_1 0.477 0.000 0 22 0.201 0.000 0 22 0.345 0.000 0 13
+ clk_out1_design_1_clk_wiz_0_1 0.738 0.000 0 22 0.186 0.000 0 22 0.345 0.000 0 13
clkfbout_design_1_clk_wiz_0_1 7.845 0.000 0 3
@@ -210,12 +210,12 @@ Period(ns): 10.000
Sources: { clk }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
-Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 10.000 8.751 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
-Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 10.000 42.633 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
-Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
-Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
-High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
-High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
+Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 10.000 8.751 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
+Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 10.000 42.633 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
+Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
+Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
+High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
+High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1
@@ -223,28 +223,28 @@ High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000
From Clock: clk_out1_design_1_clk_wiz_0_1
To Clock: clk_out1_design_1_clk_wiz_0_1
-Setup : 0 Failing Endpoints, Worst Slack 0.477ns, Total Violation 0.000ns
-Hold : 0 Failing Endpoints, Worst Slack 0.201ns, Total Violation 0.000ns
+Setup : 0 Failing Endpoints, Worst Slack 0.738ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.186ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.345ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
-Slack (MET) : 0.477ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 2.044ns (logic 0.773ns (37.811%) route 1.271ns (62.189%))
- Logic Levels: 1 (LUT3=1)
- Clock Path Skew: 0.000ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.276ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -254,59 +254,57 @@ Slack (MET) : 0.477ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y7 FDRE (Prop_fdre_C_Q) 0.478 -2.169 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/Q
- net (fo=3, routed) 1.271 -0.898 design_1_i/reg_decalage_0/inst/led[7]
- SLICE_X42Y7 LUT3 (Prop_lut3_I2_O) 0.295 -0.603 r design_1_i/reg_decalage_0/inst/Q[6]_i_1/O
- net (fo=1, routed) 0.000 -0.603 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/D
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
- clock pessimism -0.276 -0.147
- clock uncertainty -0.057 -0.204
- SLICE_X42Y7 FDRE (Setup_fdre_C_D) 0.079 -0.125 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
-------------------------------------------------------------------
- required time -0.125
- arrival time 0.603
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.477
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -316,59 +314,57 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/CE
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.600
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -378,59 +374,57 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/CE
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.600
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -440,59 +434,57 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/CE
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.600
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -502,59 +494,57 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/CE
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.600
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -564,59 +554,57 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/CE
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.600
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.738ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/R
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.253ns (logic 0.456ns (36.382%) route 0.797ns (63.618%))
+ Logic Levels: 0
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.315ns
+ Clock Pessimism Removal (CPR): -0.413ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -626,59 +614,57 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.011 -2.315 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y71 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/CE
+ SLICE_X1Y71 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
+ net (fo=8, routed) 0.797 -1.061 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/R
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/C
+ clock pessimism -0.413 0.163
+ clock uncertainty -0.057 0.106
+ SLICE_X0Y70 FDRE (Setup_fdre_C_R) -0.429 -0.323 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time -0.323
+ arrival time 1.061
-------------------------------------------------------------------
- slack 0.600
+ slack 0.738
-Slack (MET) : 0.600ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Slack (MET) : 0.882ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/CE
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.649ns (logic 0.642ns (38.942%) route 1.007ns (61.058%))
- Logic Levels: 1 (LUT1=1)
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.592ns (logic 0.715ns (44.924%) route 0.877ns (55.076%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.000ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.314ns
+ Clock Pessimism Removal (CPR): -0.390ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -688,59 +674,59 @@ Slack (MET) : 0.600ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.012 -2.314 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.518 -2.129 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
- net (fo=2, routed) 0.486 -1.642 design_1_i/reg_decalage_0/inst/btnD_r
- SLICE_X42Y8 LUT1 (Prop_lut1_I0_O) 0.124 -1.518 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
- net (fo=7, routed) 0.520 -0.998 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/CE
+ SLICE_X0Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.895 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/Q
+ net (fo=3, routed) 0.877 -1.018 design_1_i/reg_decalage_0/inst/led[4]
+ SLICE_X0Y70 LUT3 (Prop_lut3_I2_O) 0.296 -0.722 r design_1_i/reg_decalage_0/inst/Q[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.722 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_CE) -0.169 -0.398 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
+ clock pessimism -0.390 0.186
+ clock uncertainty -0.057 0.129
+ SLICE_X0Y70 FDRE (Setup_fdre_C_D) 0.031 0.160 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]
-------------------------------------------------------------------
- required time -0.398
- arrival time 0.998
+ required time 0.160
+ arrival time 0.722
-------------------------------------------------------------------
- slack 0.600
+ slack 0.882
-Slack (MET) : 0.698ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
+Slack (MET) : 0.896ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 1.863ns (logic 0.671ns (36.014%) route 1.192ns (63.986%))
+ Data Path Delay: 1.622ns (logic 0.745ns (45.943%) route 0.877ns (54.057%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.000ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.276ns
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.314ns
+ Clock Pessimism Removal (CPR): -0.390ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -750,59 +736,59 @@ Slack (MET) : 0.698ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.012 -2.314 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y7 FDRE (Prop_fdre_C_Q) 0.518 -2.129 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/Q
- net (fo=3, routed) 1.192 -0.937 design_1_i/reg_decalage_0/inst/led[6]
- SLICE_X42Y7 LUT3 (Prop_lut3_I2_O) 0.153 -0.784 r design_1_i/reg_decalage_0/inst/Q[5]_i_1/O
- net (fo=1, routed) 0.000 -0.784 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/D
+ SLICE_X0Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.895 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/Q
+ net (fo=3, routed) 0.877 -1.018 design_1_i/reg_decalage_0/inst/led[4]
+ SLICE_X0Y70 LUT3 (Prop_lut3_I0_O) 0.326 -0.692 r design_1_i/reg_decalage_0/inst/Q[5]_i_1/O
+ net (fo=1, routed) 0.000 -0.692 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
- clock pessimism -0.276 -0.147
- clock uncertainty -0.057 -0.204
- SLICE_X42Y7 FDRE (Setup_fdre_C_D) 0.118 -0.086 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
+ clock pessimism -0.390 0.186
+ clock uncertainty -0.057 0.129
+ SLICE_X0Y70 FDRE (Setup_fdre_C_D) 0.075 0.204 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]
-------------------------------------------------------------------
- required time -0.086
- arrival time 0.784
+ required time 0.204
+ arrival time 0.692
-------------------------------------------------------------------
- slack 0.698
+ slack 0.896
-Slack (MET) : 0.746ns (required time - arrival time)
- Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Slack (MET) : 0.950ns (required time - arrival time)
+ Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/R
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/CE
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (clk_out1_design_1_clk_wiz_0_1 rise@2.500ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.976ns (logic 0.478ns (48.955%) route 0.498ns (51.045%))
- Logic Levels: 0
- Clock Path Skew: -0.025ns (DCD - SCD + CPR)
- Destination Clock Delay (DCD): -2.371ns = ( 0.129 - 2.500 )
- Source Clock Delay (SCD): -2.647ns
- Clock Pessimism Removal (CPR): -0.301ns
+ Data Path Delay: 1.266ns (logic 0.718ns (56.723%) route 0.548ns (43.277%))
+ Logic Levels: 1 (LUT1=1)
+ Clock Path Skew: -0.022ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.924ns = ( 0.576 - 2.500 )
+ Source Clock Delay (SCD): -2.314ns
+ Clock Pessimism Removal (CPR): -0.412ns
Clock Uncertainty: 0.057ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.090ns
@@ -812,42 +798,44 @@ Slack (MET) : 0.746ns (required time - arrival time)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.972 0.972 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.306 2.278 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -8.533 -6.255 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.754 -4.501 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -4.400 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.753 -2.647 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.253 2.728 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.953 -6.225 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.802 -4.422 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -4.326 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 2.012 -2.314 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.478 -2.169 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
- net (fo=8, routed) 0.498 -1.670 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/R
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.895 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
+ net (fo=2, routed) 0.169 -1.726 design_1_i/reg_decalage_0/inst/btnD_r
+ SLICE_X1Y70 LUT1 (Prop_lut1_I0_O) 0.299 -1.427 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
+ net (fo=7, routed) 0.379 -1.048 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/CE
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
2.500 2.500 r
- K11 0.000 2.500 r clk (IN)
+ R4 0.000 2.500 r clk (IN)
net (fo=0) 0.000 2.500 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.838 3.338 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 1.181 4.519 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -7.650 -3.131 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 1.594 -1.537 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.446 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 1.575 0.129 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
- clock pessimism -0.301 -0.172
- clock uncertainty -0.057 -0.229
- SLICE_X42Y7 FDRE (Setup_fdre_C_R) -0.695 -0.924 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
+ R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.181 5.086 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -8.206 -3.120 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.718 -1.402 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -1.311 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 1.887 0.576 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+ clock pessimism -0.412 0.164
+ clock uncertainty -0.057 0.107
+ SLICE_X0Y70 FDRE (Setup_fdre_C_CE) -0.205 -0.098 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
-------------------------------------------------------------------
- required time -0.924
- arrival time 1.670
+ required time -0.098
+ arrival time 1.048
-------------------------------------------------------------------
- slack 0.746
+ slack 0.950
@@ -855,567 +843,575 @@ Slack (MET) : 0.746ns (required time - arrival time)
Min Delay Paths
--------------------------------------------------------------------------------------
-Slack (MET) : 0.201ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Slack (MET) : 0.186ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/btnU_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.321ns (logic 0.246ns (76.655%) route 0.075ns (23.345%))
- Logic Levels: 1 (LUT6=1)
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.238ns
+ Data Path Delay: 0.291ns (logic 0.186ns (63.933%) route 0.105ns (36.067%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnU_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.148 -0.332 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
- net (fo=8, routed) 0.075 -0.257 design_1_i/reg_decalage_0/inst/btnC_r
- SLICE_X42Y8 LUT6 (Prop_lut6_I0_O) 0.098 -0.159 r design_1_i/reg_decalage_0/inst/Q[0]_i_1/O
- net (fo=1, routed) 0.000 -0.159 design_1_i/reg_decalage_0/inst/exemple_1/D[0]
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/D
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/btnU_r_reg/Q
+ net (fo=8, routed) 0.105 -0.287 design_1_i/reg_decalage_0/inst/btnU_r
+ SLICE_X0Y70 LUT3 (Prop_lut3_I1_O) 0.045 -0.242 r design_1_i/reg_decalage_0/inst/Q[6]_i_1/O
+ net (fo=1, routed) 0.000 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
- clock pessimism -0.238 -0.480
- SLICE_X42Y8 FDRE (Hold_fdre_C_D) 0.120 -0.360 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.092 -0.428 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]
-------------------------------------------------------------------
- required time 0.360
- arrival time -0.159
+ required time 0.428
+ arrival time -0.242
-------------------------------------------------------------------
- slack 0.201
+ slack 0.186
-Slack (MET) : 0.243ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
+Slack (MET) : 0.190ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.374ns (logic 0.249ns (66.504%) route 0.125ns (33.496%))
+ Data Path Delay: 0.310ns (logic 0.189ns (60.928%) route 0.121ns (39.072%))
Logic Levels: 1 (LUT3=1)
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.238ns
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y7 FDRE (Prop_fdre_C_Q) 0.148 -0.332 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/Q
- net (fo=3, routed) 0.125 -0.207 design_1_i/reg_decalage_0/inst/led[5]
- SLICE_X42Y7 LUT3 (Prop_lut3_I2_O) 0.101 -0.106 r design_1_i/reg_decalage_0/inst/Q[4]_i_1/O
- net (fo=1, routed) 0.000 -0.106 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/D
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/Q
+ net (fo=4, routed) 0.121 -0.271 design_1_i/reg_decalage_0/inst/led[0]
+ SLICE_X0Y70 LUT3 (Prop_lut3_I2_O) 0.048 -0.223 r design_1_i/reg_decalage_0/inst/Q[7]_i_2/O
+ net (fo=1, routed) 0.000 -0.223 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_1
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
- clock pessimism -0.238 -0.480
- SLICE_X42Y7 FDRE (Hold_fdre_C_D) 0.131 -0.349 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.107 -0.413 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]
-------------------------------------------------------------------
- required time 0.349
- arrival time -0.106
+ required time 0.413
+ arrival time -0.223
-------------------------------------------------------------------
- slack 0.243
+ slack 0.190
-Slack (MET) : 0.254ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
+Slack (MET) : 0.191ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.375ns (logic 0.209ns (55.663%) route 0.166ns (44.337%))
- Logic Levels: 1 (LUT3=1)
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.238ns
+ Data Path Delay: 0.295ns (logic 0.186ns (63.068%) route 0.109ns (36.932%))
+ Logic Levels: 1 (LUT6=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y7 FDRE (Prop_fdre_C_Q) 0.164 -0.316 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/Q
- net (fo=3, routed) 0.166 -0.149 design_1_i/reg_decalage_0/inst/led[2]
- SLICE_X42Y7 LUT3 (Prop_lut3_I0_O) 0.045 -0.104 r design_1_i/reg_decalage_0/inst/Q[3]_i_1/O
- net (fo=1, routed) 0.000 -0.104 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/D
+ SLICE_X0Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/Q
+ net (fo=3, routed) 0.109 -0.283 design_1_i/reg_decalage_0/inst/led[1]
+ SLICE_X1Y70 LUT6 (Prop_lut6_I1_O) 0.045 -0.238 r design_1_i/reg_decalage_0/inst/Q[0]_i_1/O
+ net (fo=1, routed) 0.000 -0.238 design_1_i/reg_decalage_0/inst/exemple_1/D[0]
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
- clock pessimism -0.238 -0.480
- SLICE_X42Y7 FDRE (Hold_fdre_C_D) 0.121 -0.359 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X1Y70 FDRE (Hold_fdre_C_D) 0.091 -0.429 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]
-------------------------------------------------------------------
- required time 0.359
- arrival time -0.104
+ required time 0.429
+ arrival time -0.238
-------------------------------------------------------------------
- slack 0.254
+ slack 0.191
-Slack (MET) : 0.275ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+Slack (MET) : 0.203ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.396ns (logic 0.209ns (52.720%) route 0.187ns (47.280%))
+ Data Path Delay: 0.307ns (logic 0.186ns (60.547%) route 0.121ns (39.453%))
Logic Levels: 1 (LUT3=1)
- Clock Path Skew: 0.000ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.238ns
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y7 FDRE (Prop_fdre_C_Q) 0.164 -0.316 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/Q
- net (fo=3, routed) 0.187 -0.128 design_1_i/reg_decalage_0/inst/led[1]
- SLICE_X42Y7 LUT3 (Prop_lut3_I0_O) 0.045 -0.083 r design_1_i/reg_decalage_0/inst/Q[2]_i_1/O
- net (fo=1, routed) 0.000 -0.083 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/D
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/Q
+ net (fo=4, routed) 0.121 -0.271 design_1_i/reg_decalage_0/inst/led[0]
+ SLICE_X0Y70 LUT3 (Prop_lut3_I0_O) 0.045 -0.226 r design_1_i/reg_decalage_0/inst/Q[1]_i_1/O
+ net (fo=1, routed) 0.000 -0.226 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
- clock pessimism -0.238 -0.480
- SLICE_X42Y7 FDRE (Hold_fdre_C_D) 0.121 -0.359 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.091 -0.429 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
-------------------------------------------------------------------
- required time 0.359
- arrival time -0.083
+ required time 0.429
+ arrival time -0.226
-------------------------------------------------------------------
- slack 0.275
+ slack 0.203
-Slack (MET) : 0.285ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+Slack (MET) : 0.248ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/btnU_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.432ns (logic 0.210ns (48.651%) route 0.222ns (51.349%))
+ Data Path Delay: 0.368ns (logic 0.186ns (50.489%) route 0.182ns (49.511%))
Logic Levels: 1 (LUT3=1)
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.222ns
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnU_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.164 -0.316 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/Q
- net (fo=4, routed) 0.222 -0.094 design_1_i/reg_decalage_0/inst/led[0]
- SLICE_X42Y7 LUT3 (Prop_lut3_I2_O) 0.046 -0.048 r design_1_i/reg_decalage_0/inst/Q[7]_i_2/O
- net (fo=1, routed) 0.000 -0.048 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_1
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/D
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/btnU_r_reg/Q
+ net (fo=8, routed) 0.182 -0.210 design_1_i/reg_decalage_0/inst/btnU_r
+ SLICE_X0Y70 LUT3 (Prop_lut3_I1_O) 0.045 -0.165 r design_1_i/reg_decalage_0/inst/Q[4]_i_1/O
+ net (fo=1, routed) 0.000 -0.165 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]/C
- clock pessimism -0.222 -0.464
- SLICE_X42Y7 FDRE (Hold_fdre_C_D) 0.131 -0.333 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.107 -0.413 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]
-------------------------------------------------------------------
- required time 0.333
- arrival time -0.048
+ required time 0.413
+ arrival time -0.165
-------------------------------------------------------------------
- slack 0.285
+ slack 0.248
-Slack (MET) : 0.295ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+Slack (MET) : 0.252ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/D
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.431ns (logic 0.209ns (48.532%) route 0.222ns (51.468%))
+ Data Path Delay: 0.359ns (logic 0.183ns (50.988%) route 0.176ns (49.012%))
Logic Levels: 1 (LUT3=1)
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.222ns
+ Clock Path Skew: 0.000ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.229ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.164 -0.316 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/Q
- net (fo=4, routed) 0.222 -0.094 design_1_i/reg_decalage_0/inst/led[0]
- SLICE_X42Y7 LUT3 (Prop_lut3_I0_O) 0.045 -0.049 r design_1_i/reg_decalage_0/inst/Q[1]_i_1/O
- net (fo=1, routed) 0.000 -0.049 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]_0
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/D
+ SLICE_X0Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[6]/Q
+ net (fo=3, routed) 0.176 -0.216 design_1_i/reg_decalage_0/inst/led[6]
+ SLICE_X0Y70 LUT3 (Prop_lut3_I2_O) 0.042 -0.174 r design_1_i/reg_decalage_0/inst/Q[5]_i_1/O
+ net (fo=1, routed) 0.000 -0.174 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
- clock pessimism -0.222 -0.464
- SLICE_X42Y7 FDRE (Hold_fdre_C_D) 0.120 -0.344 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]/C
+ clock pessimism -0.229 -0.533
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.107 -0.426 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[5]
-------------------------------------------------------------------
- required time 0.344
- arrival time -0.049
+ required time 0.426
+ arrival time -0.174
-------------------------------------------------------------------
- slack 0.295
+ slack 0.252
-Slack (MET) : 0.368ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Slack (MET) : 0.263ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/btnU_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/R
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.340ns (logic 0.148ns (43.478%) route 0.192ns (56.522%))
- Logic Levels: 0
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.222ns
+ Data Path Delay: 0.368ns (logic 0.186ns (50.489%) route 0.182ns (49.511%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnU_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.148 -0.332 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
- net (fo=8, routed) 0.192 -0.140 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/R
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/btnU_r_reg/Q
+ net (fo=8, routed) 0.182 -0.210 design_1_i/reg_decalage_0/inst/btnU_r
+ SLICE_X0Y70 LUT3 (Prop_lut3_I1_O) 0.045 -0.165 r design_1_i/reg_decalage_0/inst/Q[2]_i_1/O
+ net (fo=1, routed) 0.000 -0.165 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
- clock pessimism -0.222 -0.464
- SLICE_X42Y7 FDRE (Hold_fdre_C_R) -0.044 -0.508 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.092 -0.428 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]
-------------------------------------------------------------------
- required time 0.508
- arrival time -0.140
+ required time 0.428
+ arrival time -0.165
-------------------------------------------------------------------
- slack 0.368
+ slack 0.263
-Slack (MET) : 0.368ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Slack (MET) : 0.278ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/btnU_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/R
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/D
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.340ns (logic 0.148ns (43.478%) route 0.192ns (56.522%))
- Logic Levels: 0
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.222ns
+ Data Path Delay: 0.383ns (logic 0.186ns (48.539%) route 0.197ns (51.461%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnU_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.148 -0.332 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
- net (fo=8, routed) 0.192 -0.140 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/R
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r design_1_i/reg_decalage_0/inst/btnU_r_reg/Q
+ net (fo=8, routed) 0.197 -0.195 design_1_i/reg_decalage_0/inst/btnU_r
+ SLICE_X0Y70 LUT3 (Prop_lut3_I1_O) 0.045 -0.150 r design_1_i/reg_decalage_0/inst/Q[3]_i_1/O
+ net (fo=1, routed) 0.000 -0.150 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/D
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
- clock pessimism -0.222 -0.464
- SLICE_X42Y7 FDRE (Hold_fdre_C_R) -0.044 -0.508 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_D) 0.092 -0.428 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]
-------------------------------------------------------------------
- required time 0.508
- arrival time -0.140
+ required time 0.428
+ arrival time -0.150
-------------------------------------------------------------------
- slack 0.368
+ slack 0.278
-Slack (MET) : 0.368ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Slack (MET) : 0.437ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/R
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/CE
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.340ns (logic 0.148ns (43.478%) route 0.192ns (56.522%))
- Logic Levels: 0
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.222ns
+ Data Path Delay: 0.411ns (logic 0.227ns (55.257%) route 0.184ns (44.743%))
+ Logic Levels: 1 (LUT1=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.148 -0.332 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
- net (fo=8, routed) 0.192 -0.140 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/R
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.128 -0.405 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
+ net (fo=2, routed) 0.068 -0.337 design_1_i/reg_decalage_0/inst/btnD_r
+ SLICE_X1Y70 LUT1 (Prop_lut1_I0_O) 0.099 -0.238 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
+ net (fo=7, routed) 0.116 -0.122 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/CE
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
- clock pessimism -0.222 -0.464
- SLICE_X42Y7 FDRE (Hold_fdre_C_R) -0.044 -0.508 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_CE) -0.039 -0.559 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]
-------------------------------------------------------------------
- required time 0.508
- arrival time -0.140
+ required time 0.559
+ arrival time -0.122
-------------------------------------------------------------------
- slack 0.368
+ slack 0.437
-Slack (MET) : 0.368ns (arrival time - required time)
- Source: design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Slack (MET) : 0.437ns (arrival time - required time)
+ Source: design_1_i/reg_decalage_0/inst/btnD_r_reg/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
- Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/R
+ Destination: design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/CE
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_1 {rise@0.000ns fall@1.250ns period=2.500ns})
Path Group: clk_out1_design_1_clk_wiz_0_1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_out1_design_1_clk_wiz_0_1 rise@0.000ns - clk_out1_design_1_clk_wiz_0_1 rise@0.000ns)
- Data Path Delay: 0.340ns (logic 0.148ns (43.478%) route 0.192ns (56.522%))
- Logic Levels: 0
- Clock Path Skew: 0.016ns (DCD - SCD - CPR)
- Destination Clock Delay (DCD): -0.242ns
- Source Clock Delay (SCD): -0.480ns
- Clock Pessimism Removal (CPR): 0.222ns
+ Data Path Delay: 0.411ns (logic 0.227ns (55.257%) route 0.184ns (44.743%))
+ Logic Levels: 1 (LUT1=1)
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.304ns
+ Source Clock Delay (SCD): -0.533ns
+ Clock Pessimism Removal (CPR): 0.216ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.201 0.201 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.440 0.641 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.234 -1.593 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.497 -1.097 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.071 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.591 -0.480 design_1_i/reg_decalage_0/inst/clk
- SLICE_X42Y8 FDRE r design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+ R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.683 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.503 -1.819 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.546 -1.273 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.247 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.714 -0.533 design_1_i/reg_decalage_0/inst/clk
+ SLICE_X1Y70 FDRE r design_1_i/reg_decalage_0/inst/btnD_r_reg/C
------------------------------------------------------------------- -------------------
- SLICE_X42Y8 FDRE (Prop_fdre_C_Q) 0.148 -0.332 r design_1_i/reg_decalage_0/inst/btnC_r_reg/Q
- net (fo=8, routed) 0.192 -0.140 design_1_i/reg_decalage_0/inst/exemple_1/btnC_r
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/R
+ SLICE_X1Y70 FDRE (Prop_fdre_C_Q) 0.128 -0.405 f design_1_i/reg_decalage_0/inst/btnD_r_reg/Q
+ net (fo=2, routed) 0.068 -0.337 design_1_i/reg_decalage_0/inst/btnD_r
+ SLICE_X1Y70 LUT1 (Prop_lut1_I0_O) 0.099 -0.238 r design_1_i/reg_decalage_0/inst/Q[7]_i_1/O
+ net (fo=7, routed) 0.116 -0.122 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[7]_0
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/CE
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_1 rise edge)
0.000 0.000 r
- K11 0.000 0.000 r clk (IN)
+ R4 0.000 0.000 r clk (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clk_in1
- K11 IBUF (Prop_ibuf_I_O) 0.390 0.390 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
- net (fo=1, routed) 0.481 0.871 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
- PLLE2_ADV_X0Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
- -2.546 -1.675 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
- net (fo=1, routed) 0.544 -1.131 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
- BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.102 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
- net (fo=11, routed) 0.860 -0.242 design_1_i/reg_decalage_0/inst/exemple_1/clk
- SLICE_X42Y7 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
- clock pessimism -0.222 -0.464
- SLICE_X42Y7 FDRE (Hold_fdre_C_R) -0.044 -0.508 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]
+ R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r design_1_i/clk_wiz_0/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.481 0.912 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1
+ PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
+ -2.828 -1.916 r design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.595 -1.322 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_1
+ BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.293 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
+ net (fo=11, routed) 0.989 -0.304 design_1_i/reg_decalage_0/inst/exemple_1/clk
+ SLICE_X0Y70 FDRE r design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
+ clock pessimism -0.216 -0.520
+ SLICE_X0Y70 FDRE (Hold_fdre_C_CE) -0.039 -0.559 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]
-------------------------------------------------------------------
- required time 0.508
- arrival time -0.140
+ required time 0.559
+ arrival time -0.122
-------------------------------------------------------------------
- slack 0.368
+ slack 0.437
@@ -1430,36 +1426,36 @@ Sources: { design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 2.500 0.345 BUFGCTRL_X0Y0 design_1_i/clk_wiz_0/inst/clkout1_buf/I
-Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 2.500 1.251 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y9 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
-Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
-Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 2.500 157.500 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
-Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
-Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
-Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
-Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
-Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y9 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
-Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y9 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
-Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
-Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
-Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
-High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
-High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
-High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
-High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
-High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y9 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
-High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y9 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
-High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
-High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y8 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
-High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
-High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X42Y7 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 2.500 1.251 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X1Y71 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[2]/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[3]/C
+Min Period n/a FDRE/C n/a 1.000 2.500 1.500 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[4]/C
+Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 2.500 157.500 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKOUT0
+Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y71 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y71 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
+Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
+Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+Low Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+Low Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y71 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y71 design_1_i/reg_decalage_0/inst/btnC_r_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnD_r_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
+High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/btnU_r_reg/C
+High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X1Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[0]/C
+High Pulse Width Slow FDRE/C n/a 0.500 1.250 0.750 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
+High Pulse Width Fast FDRE/C n/a 0.500 1.250 0.750 SLICE_X0Y70 design_1_i/reg_decalage_0/inst/exemple_1/Q_reg[1]/C
@@ -1482,10 +1478,10 @@ Sources: { design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 design_1_i/clk_wiz_0/inst/clkf_buf/I
-Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT
-Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 10.000 8.751 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBIN
-Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 10.000 42.633 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBIN
-Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 10.000 150.000 PLLE2_ADV_X0Y0 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT
+Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT
+Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 10.000 8.751 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBIN
+Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 10.000 42.633 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBIN
+Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 10.000 150.000 PLLE2_ADV_X1Y2 design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKFBOUT
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx
index 64568e29ce16e1c3a692284a757319e74f20802e..ce29864638218ce92404e5df9ecb02a94620cf1b 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_timing_summary_routed.rpx differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.pb b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.pb
index 0cc5d1cb2cb0f8060142eb447dd6a2100ebc53d9..bc5d6d957ca00ea89941a40cd4df04a4c9681ec1 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.pb and b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.rpt b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.rpt
index 3129cf4aac9040670adf5f189f17af4b709edf05..3a7fe41582d14f9e84b43fffcaca5aedccffc735 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.rpt
+++ b/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper_utilization_placed.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:36:53 2024
+| Date : Thu Nov 28 16:32:05 2024
| Host : hogtest running 64-bit unknown
| Command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
| Design : design_1_wrapper
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -32,14 +32,14 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs | 6 | 0 | 0 | 17600 | 0.03 |
-| LUT as Logic | 6 | 0 | 0 | 17600 | 0.03 |
-| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
-| Slice Registers | 11 | 0 | 0 | 35200 | 0.03 |
-| Register as Flip Flop | 11 | 0 | 0 | 35200 | 0.03 |
-| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
-| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
-| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
+| Slice LUTs | 6 | 0 | 800 | 133800 | <0.01 |
+| LUT as Logic | 6 | 0 | 800 | 133800 | <0.01 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 11 | 0 | 1600 | 267600 | <0.01 |
+| Register as Flip Flop | 11 | 0 | 1600 | 267600 | <0.01 |
+| Register as Latch | 0 | 0 | 1600 | 267600 | 0.00 |
+| F7 Muxes | 0 | 0 | 400 | 66900 | 0.00 |
+| F8 Muxes | 0 | 0 | 200 | 33450 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
@@ -69,14 +69,14 @@ Table of Contents
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
-| Slice | 3 | 0 | 0 | 4400 | 0.07 |
-| SLICEL | 0 | 0 | | | |
-| SLICEM | 3 | 0 | | | |
-| LUT as Logic | 6 | 0 | 0 | 17600 | 0.03 |
+| Slice | 3 | 0 | 200 | 33450 | <0.01 |
+| SLICEL | 3 | 0 | | | |
+| SLICEM | 0 | 0 | | | |
+| LUT as Logic | 6 | 0 | 800 | 133800 | <0.01 |
| using O5 output only | 0 | | | | |
| using O6 output only | 3 | | | | |
| using O5 and O6 | 3 | | | | |
-| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | | |
| using O5 output only | 0 | | | | |
| using O6 output only | 0 | | | | |
@@ -85,12 +85,12 @@ Table of Contents
| using O5 output only | 0 | | | | |
| using O6 output only | 0 | | | | |
| using O5 and O6 | 0 | | | | |
-| Slice Registers | 11 | 0 | 0 | 35200 | 0.03 |
+| Slice Registers | 11 | 0 | 1600 | 267600 | <0.01 |
| Register driven from within the Slice | 8 | | | | |
| Register driven from outside the Slice | 3 | | | | |
| LUT in front of the register is unused | 1 | | | | |
| LUT in front of the register is used | 2 | | | | |
-| Unique Control Sets | 2 | | 0 | 4400 | 0.05 |
+| Unique Control Sets | 2 | | 200 | 33450 | <0.01 |
+--------------------------------------------+------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -101,9 +101,9 @@ Table of Contents
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -114,7 +114,7 @@ Table of Contents
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
-| DSPs | 0 | 0 | 0 | 80 | 0.00 |
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -124,22 +124,24 @@ Table of Contents
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB | 12 | 1 | 0 | 54 | 22.22 |
-| IOB Master Pads | 6 | | | | |
+| Bonded IOB | 12 | 12 | 0 | 285 | 4.21 |
+| IOB Master Pads | 5 | | | | |
| IOB Slave Pads | 6 | | | | |
-| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
-| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
-| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
-| IBUFDS | 0 | 0 | 0 | 54 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
-| ILOGIC | 0 | 0 | 0 | 54 | 0.00 |
-| OLOGIC | 0 | 0 | 0 | 54 | 0.00 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
@@ -150,12 +152,12 @@ Table of Contents
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
-| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
-| PLLE2_ADV | 1 | 0 | 0 | 2 | 50.00 |
-| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
-| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
-| BUFR | 0 | 0 | 0 | 8 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 1 | 0 | 0 | 10 | 10.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -171,6 +173,7 @@ Table of Contents
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/gen_run.xml b/Vivado/labo1b/labo1b.runs/impl_1/gen_run.xml
index 7c1319b95c7ac2b722c2f753058220706bbee7a9..4c951ca06a9b53dfbaccdb97c346c4e895f010bf 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/gen_run.xml
+++ b/Vivado/labo1b/labo1b.runs/impl_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="impl_1" LaunchPart="xc7z010iclg225-1L" LaunchTime="1731587790">
+<GenRun Id="impl_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1732807898">
<File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
<File Type="POSTROUTE-PHYSOPT-RQS" Name="design_1_wrapper_postroute_physopted.rqs"/>
<File Type="ROUTE-RQS" Name="design_1_wrapper_routed.rqs"/>
@@ -136,7 +136,9 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/init_design.pb b/Vivado/labo1b/labo1b.runs/impl_1/init_design.pb
index 1f3ebbe6ed4190110eed77e2add446732595cbbd..0991180f873244fde3d63f3642737e303fb12120 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/init_design.pb and b/Vivado/labo1b/labo1b.runs/impl_1/init_design.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/opt_design.pb b/Vivado/labo1b/labo1b.runs/impl_1/opt_design.pb
index a576f13ab492d48abf5903e163c1f68261d70a8f..94e8cf1589f6846d3c212bce172593a946c4f0c4 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/opt_design.pb and b/Vivado/labo1b/labo1b.runs/impl_1/opt_design.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/phys_opt_design.pb b/Vivado/labo1b/labo1b.runs/impl_1/phys_opt_design.pb
index 8b3cababda00bc44b82bea61676b1990aca2ae8f..313a74709500b906f76a48fc3489957727925e66 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/phys_opt_design.pb and b/Vivado/labo1b/labo1b.runs/impl_1/phys_opt_design.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/place_design.pb b/Vivado/labo1b/labo1b.runs/impl_1/place_design.pb
index b5d6754f159fad9fa3af6b81e448f679651885a1..b344f9176fd275e3fd0a193b2f0680816b177084 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/place_design.pb and b/Vivado/labo1b/labo1b.runs/impl_1/place_design.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/project.wdf b/Vivado/labo1b/labo1b.runs/impl_1/project.wdf
index 58be078adb6841069f59f0e82a5c6678f711515b..20510ce9dc8756dc3e7047842a7c311823933948 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/project.wdf
+++ b/Vivado/labo1b/labo1b.runs/impl_1/project.wdf
@@ -6,7 +6,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
@@ -22,12 +22,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:32:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3637386232343565313261393437313239656134373838363962396332363937:506172656e742050412070726f6a656374204944:00
-eof:188425586
+eof:480339526
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/route_design.pb b/Vivado/labo1b/labo1b.runs/impl_1/route_design.pb
index 19970e6c803e82c744c61e6f5cafd39b8985732a..c481ebcdbf9ea7fb2d86d4c2baa3b84b5752c4b4 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/route_design.pb and b/Vivado/labo1b/labo1b.runs/impl_1/route_design.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/vivado.jou b/Vivado/labo1b/labo1b.runs/impl_1/vivado.jou
index 1e07bb9c67498dc164463bbbc5945243c634af4c..7d38147222d01e8461cdfa81f1826fd92863d479 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/vivado.jou
+++ b/Vivado/labo1b/labo1b.runs/impl_1/vivado.jou
@@ -3,8 +3,8 @@
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:37:11 2024
-# Process ID: 9169
+# Start of session at: Thu Nov 28 16:35:19 2024
+# Process ID: 16486
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
@@ -19,6 +19,6 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11482 MB
+# Available Virtual :12272 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/vivado.pb b/Vivado/labo1b/labo1b.runs/impl_1/vivado.pb
index b155e40f06a230303a04d2a77f07560e35c5dc93..ba7d099e451ab5cd2205034350d13764104561db 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/vivado.pb and b/Vivado/labo1b/labo1b.runs/impl_1/vivado.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/vivado_7847.backup.jou b/Vivado/labo1b/labo1b.runs/impl_1/vivado_11165.backup.jou
similarity index 91%
rename from Vivado/labo1b/labo1b.runs/impl_1/vivado_7847.backup.jou
rename to Vivado/labo1b/labo1b.runs/impl_1/vivado_11165.backup.jou
index 50badba994799f62f04a8e7c78511b7670eeab8b..440caefc77db843f1c90220f079f51e57e05746a 100644
--- a/Vivado/labo1b/labo1b.runs/impl_1/vivado_7847.backup.jou
+++ b/Vivado/labo1b/labo1b.runs/impl_1/vivado_11165.backup.jou
@@ -3,8 +3,8 @@
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:36:33 2024
-# Process ID: 7847
+# Start of session at: Thu Nov 28 16:16:03 2024
+# Process ID: 11165
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
@@ -19,6 +19,6 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11470 MB
+# Available Virtual :13191 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/vivado_14663.backup.jou b/Vivado/labo1b/labo1b.runs/impl_1/vivado_14663.backup.jou
new file mode 100644
index 0000000000000000000000000000000000000000..d45c5d60e8768c712f29b53eb212eb71f34e1a02
--- /dev/null
+++ b/Vivado/labo1b/labo1b.runs/impl_1/vivado_14663.backup.jou
@@ -0,0 +1,24 @@
+#-----------------------------------------------------------
+# Vivado v2024.1.2 (64-bit)
+# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
+# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
+# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
+# Start of session at: Thu Nov 28 16:31:41 2024
+# Process ID: 14663
+# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1
+# Command line: vivado -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
+# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/design_1_wrapper.vdi
+# Journal file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/impl_1/vivado.jou
+# Running On :hogtest
+# Platform :unknown
+# Operating System :unknown
+# Processor Detail :11th Gen Intel(R) Core(TM) i5-1140G7 @ 1.10GHz
+# CPU Frequency :1804.800 MHz
+# CPU Physical cores:4
+# CPU Logical cores :8
+# Host memory :8296 MB
+# Swap memory :8296 MB
+# Total Virtual :16593 MB
+# Available Virtual :12349 MB
+#-----------------------------------------------------------
+source design_1_wrapper.tcl -notrace
diff --git a/Vivado/labo1b/labo1b.runs/impl_1/write_bitstream.pb b/Vivado/labo1b/labo1b.runs/impl_1/write_bitstream.pb
index 10224055f6722eff526effed5c2c69dc5b4ce8ea..cda15fecb4fad0845455b98805c76c0da0be53c3 100644
Binary files a/Vivado/labo1b/labo1b.runs/impl_1/write_bitstream.pb and b/Vivado/labo1b/labo1b.runs/impl_1/write_bitstream.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/.vivado.begin.rst b/Vivado/labo1b/labo1b.runs/synth_1/.vivado.begin.rst
index ded77f04968f057dedd8a37c1f81b1e136a98a08..845ea1348a31d106f91afa22406b0c24f096b394 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/.vivado.begin.rst
+++ b/Vivado/labo1b/labo1b.runs/synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="7594" HostCore="8" HostMemory="8102396">
+ <Process Command="vivado" Owner="hogtest" Host="hogtest" Pid="14309" HostCore="8" HostMemory="8102392">
</Process>
</ProcessHandle>
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.dcp b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.dcp
index e54e1f0e1aa3ffa5c83e8d0528ab0608159ef2de..494b6b37241a49b96c67e3b257a536e77a08a8aa 100644
Binary files a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.dcp and b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.dcp differ
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.tcl b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.tcl
index bce213a0339fa680d2f9e17d3f0c0482e2d6fcc9..93cde7ffa3317f794d1fdee66c1a803adfdae18e 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.tcl
+++ b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.tcl
@@ -56,8 +56,12 @@ if {$::dispatch::connected} {
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param chipscope.maxJobs 2
+set_param tcl.statsThreshold 360
+set_msg_config -string {{.*The IP file '.*' has been moved from its original location, as a result the outputs for this IP will now be generated in '.*'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands..*}} -suppress -regexp
+set_msg_config -string {{.*File '.*.xci' referenced by design '.*' could not be found..*}} -suppress -regexp
OPTRACE "Creating in-memory project" START { }
-create_project -in_memory -part xc7z010iclg225-1L
+create_project -in_memory -part xc7a200tsbg484-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
@@ -68,6 +72,7 @@ set_property parent.project_path {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado
set_property XPM_LIBRARIES XPM_CDC [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
+set_property board_part digilentinc.com:nexys_video:part0:1.2 [current_project]
set_property ip_output_repo {/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.cache/ip} [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
@@ -97,7 +102,7 @@ set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
-synth_design -top design_1_wrapper -part xc7z010iclg225-1L
+synth_design -top design_1_wrapper -part xc7a200tsbg484-1
OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.vds b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.vds
index dc3dc96d35f8b31d6883a8854522bad3f5968e19..1e37e9a7cdef54878978cac2929475112f35f69f 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.vds
+++ b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.vds
@@ -3,8 +3,8 @@
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:35:44 2024
-# Process ID: 7637
+# Start of session at: Thu Nov 28 16:29:20 2024
+# Process ID: 14351
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1
# Command line: vivado -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.vds
@@ -19,48 +19,47 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11461 MB
+# Available Virtual :12318 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
-create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.141 ; gain = 16.867 ; free physical = 200 ; free virtual = 10629
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/hogtest/Xilinx/tools/Vivado/2024.1/data/ip'.
-Command: synth_design -top design_1_wrapper -part xc7z010iclg225-1L
+Command: synth_design -top design_1_wrapper -part xc7a200tsbg484-1
Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010i'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010i'
-INFO: [Device 21-403] Loading part xc7z010iclg225-1L
-INFO: [Device 21-9227] Part: xc7z010iclg225-1L does not have CEAM library.
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tsbg484-1
+INFO: [Device 21-9227] Part: xc7a200tsbg484-1 does not have CEAM library.
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 7658
+INFO: [Synth 8-7075] Helper process launched with PID 14370
---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2340.973 ; gain = 411.715 ; free physical = 146 ; free virtual = 9611
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2430.078 ; gain = 411.715 ; free physical = 1755 ; free virtual = 10296
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13]
INFO: [Synth 8-6157] synthesizing module 'design_1' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v:13]
-INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_1' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-7637-hogtest/realtime/design_1_clk_wiz_0_1_stub.v:6]
-INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_1' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-7637-hogtest/realtime/design_1_clk_wiz_0_1_stub.v:6]
+INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_0_1' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-14351-hogtest/realtime/design_1_clk_wiz_0_1_stub.v:6]
+INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_0_1' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-14351-hogtest/realtime/design_1_clk_wiz_0_1_stub.v:6]
WARNING: [Synth 8-7071] port 'locked' of module 'design_1_clk_wiz_0_1' is unconnected for instance 'clk_wiz_0' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v:38]
WARNING: [Synth 8-7023] instance 'clk_wiz_0' of module 'design_1_clk_wiz_0_1' has 4 connections declared, but only 3 given [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v:38]
-INFO: [Synth 8-6157] synthesizing module 'design_1_reg_decalage_0_0' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-7637-hogtest/realtime/design_1_reg_decalage_0_0_stub.v:6]
-INFO: [Synth 8-6155] done synthesizing module 'design_1_reg_decalage_0_0' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-7637-hogtest/realtime/design_1_reg_decalage_0_0_stub.v:6]
+INFO: [Synth 8-6157] synthesizing module 'design_1_reg_decalage_0_0' [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-14351-hogtest/realtime/design_1_reg_decalage_0_0_stub.v:6]
+INFO: [Synth 8-6155] done synthesizing module 'design_1_reg_decalage_0_0' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/.Xil/Vivado-14351-hogtest/realtime/design_1_reg_decalage_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/synth/design_1.v:13]
INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13]
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2417.910 ; gain = 488.652 ; free physical = 110 ; free virtual = 9515
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2515.016 ; gain = 496.652 ; free physical = 1665 ; free virtual = 10206
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2435.723 ; gain = 506.465 ; free physical = 110 ; free virtual = 9515
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2529.859 ; gain = 511.496 ; free physical = 1661 ; free virtual = 10202
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2435.723 ; gain = 506.465 ; free physical = 110 ; free virtual = 9515
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2529.859 ; gain = 511.496 ; free physical = 1661 ; free virtual = 10202
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2439.723 ; gain = 0.000 ; free physical = 110 ; free virtual = 9515
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2533.859 ; gain = 0.000 ; free physical = 1661 ; free virtual = 10202
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -77,20 +76,20 @@ Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.r
Finished Parsing XDC File [/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2506.723 ; gain = 0.000 ; free physical = 86 ; free virtual = 9502
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2603.828 ; gain = 0.000 ; free physical = 1642 ; free virtual = 10186
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2506.723 ; gain = 0.000 ; free physical = 86 ; free virtual = 9502
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2603.828 ; gain = 0.000 ; free physical = 1642 ; free virtual = 10186
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2506.723 ; gain = 577.465 ; free physical = 103 ; free virtual = 9489
+Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2603.828 ; gain = 585.465 ; free physical = 1642 ; free virtual = 10186
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
-Loading part: xc7z010iclg225-1L
+Loading part: xc7a200tsbg484-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 103 ; free virtual = 9489
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10186
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
@@ -101,10 +100,10 @@ Applied set_property KEEP_HIERARCHY = SOFT for design_1_i. (constraint file aut
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/clk_wiz_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for design_1_i/reg_decalage_0. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 103 ; free virtual = 9489
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10186
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 104 ; free virtual = 9490
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10187
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -117,8 +116,8 @@ Finished RTL Component Statistics
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
-DSPs: 80 (col length:40)
-BRAMs: 120 (col length: RAMB18 40 RAMB36 20)
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
@@ -127,25 +126,25 @@ Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 107 ; free virtual = 9497
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 104 ; free virtual = 9502
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 104 ; free virtual = 9502
+Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 104 ; free virtual = 9502
+Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -163,37 +162,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -217,16 +216,16 @@ Report Cell Usage:
|4 |OBUF | 8|
+------+------------------------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.727 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.832 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2514.727 ; gain = 514.469 ; free physical = 113 ; free virtual = 9511
-Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2514.734 ; gain = 585.469 ; free physical = 113 ; free virtual = 9511
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2611.832 ; gain = 519.500 ; free physical = 1642 ; free virtual = 10191
+Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2611.840 ; gain = 593.469 ; free physical = 1642 ; free virtual = 10191
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.734 ; gain = 0.000 ; free physical = 113 ; free virtual = 9511
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2611.840 ; gain = 0.000 ; free physical = 1642 ; free virtual = 10191
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2514.734 ; gain = 0.000 ; free physical = 401 ; free virtual = 9799
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2611.840 ; gain = 0.000 ; free physical = 1978 ; free virtual = 10528
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
@@ -234,10 +233,9 @@ Synth Design complete | Checksum: 2dbfd8ea
INFO: [Common 17-83] Releasing license: Synthesis
25 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 2514.734 ; gain = 923.688 ; free physical = 401 ; free virtual = 9799
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1880.482; main = 1538.625; forked = 394.715
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4188.938; main = 2514.730; forked = 1674.207
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2538.738 ; gain = 0.000 ; free physical = 401 ; free virtual = 9799
+INFO: [Common 17-600] The following parameters have non-default value.
+tcl.statsThreshold
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2635.844 ; gain = 0.000 ; free physical = 1978 ; free virtual = 10528
INFO: [Common 17-1381] The checkpoint '/home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.dcp' has been generated.
INFO: [Vivado 12-24828] Executing command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Thu Nov 14 13:36:13 2024...
+INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 16:29:51 2024...
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.pb b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.pb
index e18f3725cfb8717644bc3776db39eb647ab1f3b2..a05696a0c65935b610ba2bf3adfaa31902105466 100644
Binary files a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.pb and b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.pb differ
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.rpt b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.rpt
index 5e33bf3cfda6d0cff4d3950d2ec2ee1ed6eee453..376805eb2147b231efadf6f9ae256cc525fa5e70 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.rpt
+++ b/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper_utilization_synth.rpt
@@ -1,12 +1,12 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-| Date : Thu Nov 14 13:36:13 2024
+| Date : Thu Nov 28 16:29:51 2024
| Host : hogtest running 64-bit unknown
| Command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb
| Design : design_1_wrapper
-| Device : xc7z010iclg225-1L
-| Speed File : -1L
+| Device : xc7a200tsbg484-1
+| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
@@ -31,14 +31,14 @@ Table of Contents
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs* | 0 | 0 | 0 | 17600 | 0.00 |
-| LUT as Logic | 0 | 0 | 0 | 17600 | 0.00 |
-| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
-| Slice Registers | 0 | 0 | 0 | 35200 | 0.00 |
-| Register as Flip Flop | 0 | 0 | 0 | 35200 | 0.00 |
-| Register as Latch | 0 | 0 | 0 | 35200 | 0.00 |
-| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
-| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
+| Slice LUTs* | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Logic | 0 | 0 | 0 | 134600 | 0.00 |
+| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
+| Slice Registers | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Flip Flop | 0 | 0 | 0 | 269200 | 0.00 |
+| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@@ -70,9 +70,9 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
-| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
+| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
@@ -83,7 +83,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
-| DSPs | 0 | 0 | 0 | 80 | 0.00 |
+| DSPs | 0 | 0 | 0 | 740 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
@@ -93,20 +93,22 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB | 11 | 0 | 0 | 54 | 20.37 |
-| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
-| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
-| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
-| IBUFDS | 0 | 0 | 0 | 54 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
-| ILOGIC | 0 | 0 | 0 | 54 | 0.00 |
-| OLOGIC | 0 | 0 | 0 | 54 | 0.00 |
+| Bonded IOB | 11 | 0 | 0 | 285 | 3.86 |
+| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
+| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
+| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
+| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
@@ -117,12 +119,12 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
-| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
-| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
-| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
-| BUFR | 0 | 0 | 0 | 8 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
+| BUFR | 0 | 0 | 0 | 40 | 0.00 |
+------------+------+-------+------------+-----------+-------+
@@ -138,6 +140,7 @@ Warning! For any ECO changes, please run place_design if there are unplaced inst
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/gen_run.xml b/Vivado/labo1b/labo1b.runs/synth_1/gen_run.xml
index 347635d9f414a5cd7363e9a4e202c77a5e83d2a3..c0b38aa9bc0a45e58f8825ea674cad3aa005c442 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/gen_run.xml
+++ b/Vivado/labo1b/labo1b.runs/synth_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7z010iclg225-1L" LaunchTime="1731587741">
+<GenRun Id="synth_1" LaunchPart="xc7a200tsbg484-1" LaunchTime="1732807758">
<File Type="VDS-TIMINGSUMMARY" Name="design_1_wrapper_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="design_1_wrapper.dcp"/>
<File Type="RDS-UTIL-PB" Name="design_1_wrapper_utilization_synth.pb"/>
@@ -61,7 +61,9 @@
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<BlockFileSet Type="BlockSrcs" Name="design_1_reg_decalage_0_0"/>
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/project.wdf b/Vivado/labo1b/labo1b.runs/synth_1/project.wdf
index 58be078adb6841069f59f0e82a5c6678f711515b..20510ce9dc8756dc3e7047842a7c311823933948 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/project.wdf
+++ b/Vivado/labo1b/labo1b.runs/synth_1/project.wdf
@@ -6,7 +6,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
@@ -22,12 +22,12 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:32:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3637386232343565313261393437313239656134373838363962396332363937:506172656e742050412070726f6a656374204944:00
-eof:188425586
+eof:480339526
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/vivado.jou b/Vivado/labo1b/labo1b.runs/synth_1/vivado.jou
index 1729903f3fa24dc4cc4285d0313b2568199b48fb..c4b7f54dab3a48f3d9df3d405b6cff8c39d3a5be 100644
--- a/Vivado/labo1b/labo1b.runs/synth_1/vivado.jou
+++ b/Vivado/labo1b/labo1b.runs/synth_1/vivado.jou
@@ -3,8 +3,8 @@
# SW Build 5164865 on Thu Sep 5 14:36:28 MDT 2024
# IP Build 5164407 on Fri Sep 6 08:18:11 MDT 2024
# SharedData Build 5164864 on Thu Sep 05 13:09:09 MDT 2024
-# Start of session at: Thu Nov 14 13:35:44 2024
-# Process ID: 7637
+# Start of session at: Thu Nov 28 16:29:20 2024
+# Process ID: 14351
# Current directory: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1
# Command line: vivado -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl
# Log file: /home/hogtest/Projets/Cours FPGA/Labo1B/Vivado/labo1b/labo1b.runs/synth_1/design_1_wrapper.vds
@@ -19,6 +19,6 @@
# Host memory :8296 MB
# Swap memory :8296 MB
# Total Virtual :16593 MB
-# Available Virtual :11461 MB
+# Available Virtual :12318 MB
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
diff --git a/Vivado/labo1b/labo1b.runs/synth_1/vivado.pb b/Vivado/labo1b/labo1b.runs/synth_1/vivado.pb
index d9088778de42c8bd4a72a2d6db653b8c29717f07..bbf89d97c6f8fd5eae6404a08f71b8084ffd818d 100644
Binary files a/Vivado/labo1b/labo1b.runs/synth_1/vivado.pb and b/Vivado/labo1b/labo1b.runs/synth_1/vivado.pb differ
diff --git a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/design_1.bd b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/design_1.bd
index b0cd19306127236deff391d9895f421bf36aa32f..3fa1e7a7269eab0c23c34cd9cf09d60c4d9fd5f2 100644
--- a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/design_1.bd
+++ b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/design_1.bd
@@ -2,12 +2,12 @@
"design": {
"design_info": {
"boundary_crc": "0x8A7B7C861B56AAC5",
- "device": "xc7z010iclg225-1L",
+ "device": "xc7a200tsbg484-1",
"gen_directory": "../../../../labo1b.gen/sources_1/bd/design_1",
"name": "design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
- "tool_version": "2024.1",
+ "tool_version": "2024.1.2",
"validated": "true"
},
"design_tree": {
diff --git a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xci b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xci
index eebeb7f1151a9c2ff765c1f8fb60bb3210e6d46f..377c8500db5b4dac7b156d7693e3eaaefe7d481b 100644
--- a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xci
+++ b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xci
@@ -584,18 +584,18 @@
"C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
},
"project_parameters": {
- "ARCHITECTURE": [ { "value": "zynq" } ],
- "BASE_BOARD_PART": [ { "value": "" } ],
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "digilentinc.com:nexys_video:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
- "DEVICE": [ { "value": "xc7z010i" } ],
+ "DEVICE": [ { "value": "xc7a200t" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
- "PACKAGE": [ { "value": "clg225" } ],
+ "PACKAGE": [ { "value": "sbg484" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
- "SPEEDGRADE": [ { "value": "-1L" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
- "TEMPERATURE_GRADE": [ { "value": "I" } ]
+ "TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
@@ -604,7 +604,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../labo1b.gen/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
- "SWVERSION": [ { "value": "2024.1" } ],
+ "SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
diff --git a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xci b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xci
index a805d0310c0eb344eb2f2a300c023f17e68bfc35..530661f6ff001a3c722204a610b54cd7cc090885 100644
--- a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xci
+++ b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0/design_1_reg_decalage_0_0.xci
@@ -11,18 +11,18 @@
"Component_Name": [ { "value": "design_1_reg_decalage_0_0", "resolve_type": "user", "usage": "all" } ]
},
"project_parameters": {
- "ARCHITECTURE": [ { "value": "zynq" } ],
- "BASE_BOARD_PART": [ { "value": "" } ],
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "digilentinc.com:nexys_video:part0:1.2" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
- "DEVICE": [ { "value": "xc7z010i" } ],
+ "DEVICE": [ { "value": "xc7a200t" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
- "PACKAGE": [ { "value": "clg225" } ],
+ "PACKAGE": [ { "value": "sbg484" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
- "SPEEDGRADE": [ { "value": "-1L" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
- "TEMPERATURE_GRADE": [ { "value": "I" } ]
+ "TEMPERATURE_GRADE": [ { "value": "" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
@@ -31,7 +31,7 @@
"OUTPUTDIR": [ { "value": "../../../../../../labo1b.gen/sources_1/bd/design_1/ip/design_1_reg_decalage_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
- "SWVERSION": [ { "value": "2024.1" } ],
+ "SWVERSION": [ { "value": "2024.1.2" } ],
"SYNTHESISFLOW": [ { "value": "OOC_HIERARCHICAL" } ]
}
},
diff --git a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
index 24b79ef444f9de4cd0e8487460059375aeafa7e2..71499b798d1267680c0a5e3b82779d0ac71ba4c6 100644
--- a/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
+++ b/Vivado/labo1b/labo1b.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
- "Default View_TopLeft":"-595,-488",
+ "Default View_TopLeft":"-596,-501",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
@@ -12,12 +12,12 @@ preplace port port-id_btnD -pg 1 -lvl 0 -x -220 -y -70 -defaultsOSRD
preplace portBus led -pg 1 -lvl 3 -x 230 -y -150 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 1 -x -100 -y -350 -defaultsOSRD
preplace inst reg_decalage_0 -pg 1 -lvl 2 -x 110 -y -150 -defaultsOSRD
-preplace netloc btnU_1 1 0 2 N -150 -10
preplace netloc btnC_1 1 0 2 N -100 -10
preplace netloc btnD_1 1 0 2 N -70 0
-preplace netloc reg_decalage_0_led 1 2 1 N -150
+preplace netloc btnU_1 1 0 2 N -150 -10
preplace netloc clk_1 1 0 1 N -340
preplace netloc clk_wiz_0_clk_out1 1 1 1 -10 -360n
+preplace netloc reg_decalage_0_led 1 2 1 N -150
levelinfo -pg 1 -220 -100 110 230
pagesize -pg 1 -db -bbox -sgen -310 -460 340 40
"
diff --git a/Vivado/labo1b/labo1b.xpr b/Vivado/labo1b/labo1b.xpr
index 4295750a7b1cf23c74bca4dc6674c8d18e57cbfc..14ed7d6da468c09fb163b1fc99fc4a762b8bd65c 100644
--- a/Vivado/labo1b/labo1b.xpr
+++ b/Vivado/labo1b/labo1b.xpr
@@ -8,7 +8,7 @@
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="678b245e12a947129ea478869b9c2697"/>
- <Option Name="Part" Val="xc7z010iclg225-1L"/>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -43,7 +43,7 @@
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
- <Option Name="BoardPart" Val=""/>
+ <Option Name="BoardPart" Val="digilentinc.com:nexys_video:part0:1.2"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
@@ -66,13 +66,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
- <Option Name="WTXSimExportSim" Val="1"/>
- <Option Name="WTModelSimExportSim" Val="1"/>
- <Option Name="WTQuestaExportSim" Val="1"/>
+ <Option Name="WTXSimExportSim" Val="2"/>
+ <Option Name="WTModelSimExportSim" Val="2"/>
+ <Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="0"/>
- <Option Name="WTVcsExportSim" Val="1"/>
- <Option Name="WTRivieraExportSim" Val="1"/>
- <Option Name="WTActivehdlExportSim" Val="1"/>
+ <Option Name="WTVcsExportSim" Val="2"/>
+ <Option Name="WTRivieraExportSim" Val="2"/>
+ <Option Name="WTActivehdlExportSim" Val="2"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -199,9 +199,11 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
- <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010iclg225-1L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -209,9 +211,32 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="design_1_clk_wiz_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_1" Part="xc7z010iclg225-1L" ConstrsSet="design_1_clk_wiz_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_wiz_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_synth_1" ParallelReportGen="true">
+ <Run Id="synth_1_copy_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1/synth_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1_copy_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019" CtrlBit="true">
+ <ReportConfig DisplayName="synthesis_report" Name="synth_1_copy_1_synth_synthesis_report_0" Spec="" RunStep="synth_design">
+ <ReportConfigOption Name="dummy_option" Type="string"/>
+ </ReportConfig>
+ <ReportConfig DisplayName="Utilization - Synth Design" Name="synth_1_copy_1_synth_report_utilization_0" Spec="report_utilization" RunStep="synth_design" Version="1" Minor="0">
+ <ReportConfigOption Name="dummy_option" Type="string"/>
+ <ReportConfigOutputOption Name="pb" Type="string" Value=""/>
+ </ReportConfig>
+ </ReportStrategy>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles>
+ <RQSFilePath/>
+ </RQSFiles>
+ </Run>
+ <Run Id="design_1_clk_wiz_0_1_synth_1" Type="Ft3:Synth" SrcSet="design_1_clk_wiz_0_1" Part="xc7a200tsbg484-1" ConstrsSet="design_1_clk_wiz_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_clk_wiz_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_synth_1" ParallelReportGen="true">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -219,9 +244,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="design_1_reg_decalage_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_reg_decalage_0_0" Part="xc7z010iclg225-1L" ConstrsSet="design_1_reg_decalage_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_reg_decalage_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_synth_1" ParallelReportGen="true">
+ <Run Id="design_1_reg_decalage_0_0_synth_1" Type="Ft3:Synth" SrcSet="design_1_reg_decalage_0_0" Part="xc7a200tsbg484-1" ConstrsSet="design_1_reg_decalage_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/design_1_reg_decalage_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -229,9 +256,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010iclg225-1L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -247,9 +276,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="design_1_clk_wiz_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7z010iclg225-1L" ConstrsSet="design_1_clk_wiz_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_wiz_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_impl_1" ParallelReportGen="true">
+ <Run Id="design_1_clk_wiz_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="design_1_clk_wiz_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_clk_wiz_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_clk_wiz_0_1_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -264,9 +295,11 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
- <Run Id="design_1_reg_decalage_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010iclg225-1L" ConstrsSet="design_1_reg_decalage_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_reg_decalage_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_impl_1" ParallelReportGen="true">
+ <Run Id="design_1_reg_decalage_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tsbg484-1" ConstrsSet="design_1_reg_decalage_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="design_1_reg_decalage_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/design_1_reg_decalage_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -282,7 +315,39 @@
<RQSFiles/>
</Run>
</Runs>
- <Board/>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val=""/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="1"/>
+ <MsgAttr Name="RuleId" Val="1"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ <MsgAttr Name="StringsToMatch" Val=".*The IP file '.*' has been moved from its original location, as a result the outputs for this IP will now be generated in '.*'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands..*"/>
+ </MsgRule>
+ <MsgRule>
+ <MsgAttr Name="RuleType" Val="0"/>
+ <MsgAttr Name="Limit" Val="-1"/>
+ <MsgAttr Name="NewSeverity" Val="ANY"/>
+ <MsgAttr Name="Id" Val=""/>
+ <MsgAttr Name="Severity" Val="ANY"/>
+ <MsgAttr Name="ShowRule" Val="1"/>
+ <MsgAttr Name="RuleSource" Val="2"/>
+ <MsgAttr Name="StringIsRegExp" Val="1"/>
+ <MsgAttr Name="RuleId" Val="2"/>
+ <MsgAttr Name="Note" Val=""/>
+ <MsgAttr Name="Author" Val=""/>
+ <MsgAttr Name="CreatedTimestamp" Val=""/>
+ <MsgAttr Name="StringsToMatch" Val=".*File '.*.xci' referenced by design '.*' could not be found..*"/>
+ </MsgRule>
+ <Board>
+ <Jumpers/>
+ </Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">