diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
index f724f3bacebb549d0144991047a8247d0c4f8040..10953fd7a5eb5b762581c9fb0fdccdc38be32e18 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
@@ -6078,7 +6078,7 @@
<xilinx:coreRevision>24</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ADDRESS_MODE" xilinx:valueSource="weak"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ADDRESS_MODE" xilinx:valueSource="weak" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xml
index c17691c0f7994043a2f7b41ea5637cb9f24b9300..8a8d645afcbee63bd743addaeefc886398a9d0b5 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xml
@@ -6078,7 +6078,7 @@
<xilinx:coreRevision>24</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MASTER_TYPE" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ADDRESS_MODE" xilinx:valueSource="weak"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ADDRESS_MODE" xilinx:valueSource="weak" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
index 2a1793bdb0e7afd5b29722ebb860c70f2189daaa..d7c47db44079fdd18d840b3d60e7793ecfb91df9 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
@@ -27511,7 +27511,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -27524,7 +27524,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -27541,7 +27541,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27568,7 +27568,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27588,7 +27588,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27615,7 +27615,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27642,7 +27642,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27669,7 +27669,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27696,7 +27696,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27723,7 +27723,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27743,7 +27743,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27770,7 +27770,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27797,7 +27797,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27824,7 +27824,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -27841,7 +27841,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27868,7 +27868,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27888,7 +27888,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27908,7 +27908,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27935,7 +27935,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27962,7 +27962,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27989,7 +27989,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28006,7 +28006,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28030,7 +28030,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28047,7 +28047,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28071,7 +28071,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28095,7 +28095,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28115,7 +28115,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28142,7 +28142,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28162,7 +28162,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28189,7 +28189,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28216,7 +28216,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28243,7 +28243,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28270,7 +28270,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28297,7 +28297,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28317,7 +28317,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28344,7 +28344,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28371,7 +28371,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28398,7 +28398,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28415,7 +28415,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28439,7 +28439,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28456,7 +28456,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28473,7 +28473,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28497,7 +28497,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28521,7 +28521,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28545,7 +28545,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28565,7 +28565,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28589,7 +28589,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28606,7 +28606,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28630,7 +28630,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28654,7 +28654,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28678,7 +28678,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28702,7 +28702,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28726,7 +28726,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28743,7 +28743,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28767,7 +28767,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28791,7 +28791,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28815,7 +28815,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28839,7 +28839,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28859,7 +28859,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28883,7 +28883,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28900,7 +28900,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28917,7 +28917,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28941,7 +28941,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28965,7 +28965,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28989,7 +28989,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29009,7 +29009,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29036,7 +29036,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29056,7 +29056,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29083,7 +29083,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29110,7 +29110,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29127,7 +29127,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29151,7 +29151,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29168,7 +29168,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29192,7 +29192,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29216,7 +29216,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29240,7 +29240,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29264,7 +29264,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29288,7 +29288,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29305,7 +29305,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29329,7 +29329,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29353,7 +29353,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29377,7 +29377,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29401,7 +29401,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29421,7 +29421,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29448,7 +29448,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29468,7 +29468,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29488,7 +29488,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29515,7 +29515,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29542,7 +29542,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29569,7 +29569,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -46659,6 +46659,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RSTIF.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RSTIF.TYPE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
index 03a4d053d86fb8bb73b9483f9ab01ef06568abe6..8aa7f486ff223621d23ec3f7b38d5eeb5a5e6c9a 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="43">
<CompositeFile CompositeFileTopName="mb_design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1741124056"/>
- <Generation Name="SIMULATION" State="GENERATED" Timestamp="1741124056"/>
- <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1741124056"/>
- <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1741124056"/>
+ <Generation Name="SYNTHESIS" State="STALE" Timestamp="1742483375"/>
+ <Generation Name="SIMULATION" State="STALE" Timestamp="1742483375"/>
+ <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1742483375"/>
+ <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1742483375"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth/mb_design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci
index 811ab5839a47b839465997ef92b889d506c07904..5f196d703bdede814f448019e318ac8a18898980 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci
@@ -155,7 +155,7 @@
"MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+ "MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "BRAM_Addr_A" } ],
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xci
index 6017dce02c183e57de5678204efefdf2a6106d0b..3372b0d35a4659c58158eda9a78520f0ae68bae3 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_1/mb_design_1_lmb_bram_if_cntlr_0_1.xci
@@ -155,7 +155,7 @@
"MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+ "MEM_ADDRESS_MODE": [ { "value": "", "value_src": "weak", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ADDR": [ { "physical_name": "BRAM_Addr_A" } ],
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci
index 23b3a59b28b2c30b70a1c8553eba8be6524e9b1a..5cf1d8a7d29e04b9d2f049ccfddab6db48b89887 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci
@@ -1316,7 +1316,7 @@
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
- "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+ "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "aresetn" } ]
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
index e2aa5830a4fe4c7294841dca3afff8257a68c6a2..f0f5e6f0d63fcb96af4eb5fb66dd31f323aa127d 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
@@ -7,8 +7,7 @@
"name": "mb_design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
- "tool_version": "2024.1.2",
- "validated": "true"
+ "tool_version": "2024.1.2"
},
"design_tree": {
"microblaze_0": "",
@@ -31,7 +30,8 @@
"axi_gpio_0": "",
"axi_timer_0": "",
"axi_intc_0": "",
- "xlconcat_0": ""
+ "xlconcat_0": "",
+ "axi4lite_hog_build_i_0": ""
},
"interface_ports": {
"GPIO_0": {
@@ -55,26 +55,6 @@
"parameters": {
"ASSOCIATED_RESET": {
"value": "reset"
- },
- "CLK_DOMAIN": {
- "value": "mb_design_1_clk_in1_0",
- "value_src": "default"
- },
- "FREQ_HZ": {
- "value": "100000000",
- "value_src": "default"
- },
- "FREQ_TOLERANCE_HZ": {
- "value": "0",
- "value_src": "default"
- },
- "INSERT_VIP": {
- "value": "0",
- "value_src": "default"
- },
- "PHASE": {
- "value": "0.0",
- "value_src": "default"
}
}
},
@@ -82,10 +62,6 @@
"type": "rst",
"direction": "I",
"parameters": {
- "INSERT_VIP": {
- "value": "0",
- "value_src": "default"
- },
"POLARITY": {
"value": "ACTIVE_HIGH"
}
@@ -894,6 +870,250 @@
"value": "1"
}
}
+ },
+ "axi4lite_hog_build_i_0": {
+ "vlnv": "xilinx.com:module_ref:axi4lite_hog_build_info:1.0",
+ "ip_revision": "1",
+ "xci_name": "mb_design_1_axi4lite_hog_build_i_0_0",
+ "xci_path": "ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci",
+ "inst_hier_path": "axi4lite_hog_build_i_0",
+ "reference_info": {
+ "ref_type": "hdl",
+ "ref_name": "axi4lite_hog_build_info",
+ "boundary_crc": "0x0"
+ },
+ "interface_ports": {
+ "s_axi": {
+ "mode": "Slave",
+ "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
+ "vlnv": "xilinx.com:interface:aximm_rtl:1.0",
+ "parameters": {
+ "DATA_WIDTH": {
+ "value": "32",
+ "value_src": "constant"
+ },
+ "PROTOCOL": {
+ "value": "AXI4LITE",
+ "value_src": "constant"
+ },
+ "ID_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "ADDR_WIDTH": {
+ "value": "32",
+ "value_src": "constant"
+ },
+ "AWUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "ARUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "WUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "RUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "BUSER_WIDTH": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "READ_WRITE_MODE": {
+ "value": "READ_WRITE",
+ "value_src": "constant"
+ },
+ "HAS_BURST": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_LOCK": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_PROT": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_CACHE": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_QOS": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_REGION": {
+ "value": "0",
+ "value_src": "constant"
+ },
+ "HAS_WSTRB": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_BRESP": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "HAS_RRESP": {
+ "value": "1",
+ "value_src": "constant"
+ },
+ "SUPPORTS_NARROW_BURST": {
+ "value": "0",
+ "value_src": "auto"
+ },
+ "NUM_READ_OUTSTANDING": {
+ "value": "1",
+ "value_src": "auto"
+ },
+ "NUM_WRITE_OUTSTANDING": {
+ "value": "1",
+ "value_src": "auto"
+ },
+ "MAX_BURST_LENGTH": {
+ "value": "1",
+ "value_src": "auto"
+ }
+ },
+ "memory_map_ref": "s_axi",
+ "port_maps": {
+ "AWADDR": {
+ "physical_name": "s_axi_awaddr",
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ },
+ "AWVALID": {
+ "physical_name": "s_axi_awvalid",
+ "direction": "I"
+ },
+ "AWREADY": {
+ "physical_name": "s_axi_awready",
+ "direction": "O"
+ },
+ "WDATA": {
+ "physical_name": "s_axi_wdata",
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ },
+ "WSTRB": {
+ "physical_name": "s_axi_wstrb",
+ "direction": "I",
+ "left": "3",
+ "right": "0"
+ },
+ "WVALID": {
+ "physical_name": "s_axi_wvalid",
+ "direction": "I"
+ },
+ "WREADY": {
+ "physical_name": "s_axi_wready",
+ "direction": "O"
+ },
+ "BRESP": {
+ "physical_name": "s_axi_bresp",
+ "direction": "O",
+ "left": "1",
+ "right": "0"
+ },
+ "BVALID": {
+ "physical_name": "s_axi_bvalid",
+ "direction": "O"
+ },
+ "BREADY": {
+ "physical_name": "s_axi_bready",
+ "direction": "I"
+ },
+ "ARADDR": {
+ "physical_name": "s_axi_araddr",
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ },
+ "ARVALID": {
+ "physical_name": "s_axi_arvalid",
+ "direction": "I"
+ },
+ "ARREADY": {
+ "physical_name": "s_axi_arready",
+ "direction": "O"
+ },
+ "RDATA": {
+ "physical_name": "s_axi_rdata",
+ "direction": "O",
+ "left": "31",
+ "right": "0"
+ },
+ "RRESP": {
+ "physical_name": "s_axi_rresp",
+ "direction": "O",
+ "left": "1",
+ "right": "0"
+ },
+ "RVALID": {
+ "physical_name": "s_axi_rvalid",
+ "direction": "O"
+ },
+ "RREADY": {
+ "physical_name": "s_axi_rready",
+ "direction": "I"
+ }
+ }
+ }
+ },
+ "ports": {
+ "s_axi_aclk": {
+ "type": "clk",
+ "direction": "I",
+ "parameters": {
+ "ASSOCIATED_BUSIF": {
+ "value": "s_axi",
+ "value_src": "constant"
+ },
+ "ASSOCIATED_RESET": {
+ "value": "s_axi_aresetn",
+ "value_src": "constant"
+ }
+ }
+ },
+ "s_axi_aresetn": {
+ "type": "rst",
+ "direction": "I",
+ "parameters": {
+ "POLARITY": {
+ "value": "ACTIVE_LOW",
+ "value_src": "constant"
+ }
+ }
+ },
+ "hog_global_date_i": {
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ },
+ "hog_global_time_i": {
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ },
+ "hog_global_ver_i": {
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ },
+ "hog_global_sha_i": {
+ "direction": "I",
+ "left": "31",
+ "right": "0"
+ }
+ }
}
},
"interface_nets": {
@@ -929,8 +1149,8 @@
},
"axi_interconnect_0_M00_AXI": {
"interface_ports": [
- "axi_interconnect_0/M00_AXI",
- "mdm_0/S_AXI"
+ "mdm_0/S_AXI",
+ "axi_interconnect_0/M00_AXI"
]
},
"axi_interconnect_0_M01_AXI": {
@@ -941,10 +1161,16 @@
},
"axi_interconnect_0_M02_AXI": {
"interface_ports": [
- "axi_intc_0/s_axi",
+ "axi_timer_0/S_AXI",
"axi_interconnect_0/M02_AXI"
]
},
+ "axi_interconnect_0_M03_AXI": {
+ "interface_ports": [
+ "axi_intc_0/s_axi",
+ "axi_interconnect_0/M03_AXI"
+ ]
+ },
"dlmb_bram_if_cntlr_0_BRAM_PORT": {
"interface_ports": [
"dlmb_bram_if_cntlr_0/BRAM_PORT",
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui
index 51a02381740f7d4062ba272ac43485dc1f6c7ac3..cb4d878972cabaaa3c30806bc00d9bf928e4f018 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
- "Default View_ScaleFactor":"0.625",
- "Default View_TopLeft":"672,-230",
+ "Default View_ScaleFactor":"1.16629",
+ "Default View_TopLeft":"1567,175",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
@@ -15,39 +15,41 @@ preplace inst ilmb_v10_0 -pg 1 -lvl 4 -x 1720 -y -110 -defaultsOSRD
preplace inst dlmb_v10_0 -pg 1 -lvl 4 -x 1720 -y 110 -defaultsOSRD
preplace inst dlmb_bram_if_cntlr_0 -pg 1 -lvl 5 -x 2010 -y 130 -defaultsOSRD
preplace inst ilmb_bram_if_cntlr_0 -pg 1 -lvl 5 -x 2010 -y -90 -defaultsOSRD
-preplace inst blk_mem_gen_0 -pg 1 -lvl 6 -x 2310 -y -80 -defaultsOSRD
+preplace inst blk_mem_gen_0 -pg 1 -lvl 6 -x 2320 -y -80 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 4 -x 1720 -y 380 -defaultsOSRD
-preplace inst mdm_0 -pg 1 -lvl 6 -x 2310 -y 310 -defaultsOSRD
-preplace inst axi_gpio_0 -pg 1 -lvl 6 -x 2310 -y 470 -defaultsOSRD
-preplace inst axi_timer_0 -pg 1 -lvl 6 -x 2310 -y 650 -defaultsOSRD
-preplace inst axi_intc_0 -pg 1 -lvl 6 -x 2310 -y 860 -defaultsOSRD
+preplace inst mdm_0 -pg 1 -lvl 6 -x 2320 -y 310 -defaultsOSRD
+preplace inst axi_gpio_0 -pg 1 -lvl 6 -x 2320 -y 470 -defaultsOSRD
+preplace inst axi_timer_0 -pg 1 -lvl 6 -x 2320 -y 650 -defaultsOSRD
+preplace inst axi_intc_0 -pg 1 -lvl 6 -x 2320 -y 860 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 5 -x 2010 -y 890 -defaultsOSRD
-preplace netloc clk_wiz_0_clk_100mhz 1 1 5 400 40 790 -10 1550 200 1880 210 2140
+preplace inst axi4lite_hog_build_i_0 -pg 1 -lvl 6 -x 2320 -y 1090 -defaultsOSRD
+preplace netloc axi_timer_0_interrupt 1 4 3 1890J 400 2170J 390 2470
preplace netloc clk_in1_0_1 1 0 1 N 0
-preplace netloc reset_0_1 1 0 2 20 -80 N
-preplace netloc proc_sys_reset_0_mb_reset 1 2 1 N -100
-preplace netloc clk_wiz_0_locked 1 1 1 N -20
-preplace netloc proc_sys_reset_0_bus_struct_reset 1 2 3 800J -40 1570 0 1890
+preplace netloc clk_wiz_0_clk_100mhz 1 1 5 390 -160 780 -230 1550 190 1880 210 2160
+preplace netloc clk_wiz_0_locked 1 1 1 400 -20n
+preplace netloc mdm_0_Debug_SYS_Rst 1 1 6 410 40 770J 30 NJ 30 NJ 30 NJ 30 2460
+preplace netloc proc_sys_reset_0_bus_struct_reset 1 2 3 780J -40 1570 0 1890
preplace netloc proc_sys_reset_0_interconnect_aresetn 1 2 2 770J -30 1530
-preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 4 NJ -20 1520 570 N 570 2160
-preplace netloc mdm_0_Debug_SYS_Rst 1 1 6 410 190 NJ 190 NJ 190 1870J 220 NJ 220 2450
-preplace netloc axi_timer_0_interrupt 1 4 3 1890J 770 NJ 770 2450
+preplace netloc proc_sys_reset_0_mb_reset 1 2 1 N -100
+preplace netloc proc_sys_reset_0_peripheral_aresetn 1 2 4 NJ -20 1520 200 1870 300 2140
+preplace netloc reset_0_1 1 0 2 20 -80 N
preplace netloc xlconcat_0_dout 1 5 1 N 890
-preplace netloc microblaze_0_ILMB 1 3 1 N -130
preplace netloc Conn 1 4 1 N -110
-preplace netloc ilmb_bram_if_cntlr_0_BRAM_PORT 1 5 1 N -90
-preplace netloc microblaze_0_DLMB 1 3 1 1560 -150n
preplace netloc Conn1 1 4 1 N 110
-preplace netloc dlmb_bram_if_cntlr_0_BRAM_PORT 1 5 1 2130 -70n
preplace netloc S00_AXI_1 1 3 1 1540 -110n
-preplace netloc mdm_0_MBDEBUG_0 1 2 5 810 560 N 560 N 560 2170 390 2460
-preplace netloc axi_interconnect_0_M00_AXI 1 4 2 1890 290 N
-preplace netloc axi_interconnect_0_M01_AXI 1 4 2 1870 380 2150J
preplace netloc axi_gpio_0_GPIO 1 6 1 N 470
-preplace netloc axi_interconnect_0_M02_AXI 1 4 2 NJ 390 2130
-preplace netloc axi_intc_0_interrupt 1 2 5 810 -220 NJ -220 NJ -220 NJ -220 2470
-levelinfo -pg 1 -390 120 590 1040 1720 2010 2310 2500
-pagesize -pg 1 -db -bbox -sgen -490 -540 2600 1020
+preplace netloc axi_intc_0_interrupt 1 2 5 810 760 NJ 760 NJ 760 NJ 760 2460
+preplace netloc dlmb_bram_if_cntlr_0_BRAM_PORT 1 5 1 2180 -70n
+preplace netloc ilmb_bram_if_cntlr_0_BRAM_PORT 1 5 1 N -90
+preplace netloc mdm_0_MBDEBUG_0 1 2 5 800 -220 N -220 N -220 N -220 2470
+preplace netloc microblaze_0_DLMB 1 3 1 1560 -150n
+preplace netloc microblaze_0_ILMB 1 3 1 N -130
+preplace netloc axi_interconnect_0_M00_AXI 1 4 2 1890 290 NJ
+preplace netloc axi_interconnect_0_M01_AXI 1 4 2 NJ 370 2180
+preplace netloc axi_interconnect_0_M02_AXI 1 4 2 NJ 390 2150
+preplace netloc axi_interconnect_0_M03_AXI 1 4 2 NJ 410 2130
+levelinfo -pg 1 -390 120 590 1040 1720 2010 2320 2500
+pagesize -pg 1 -db -bbox -sgen -490 -540 2600 1210
"
}
-
+0