diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
index 138254d821a81d62532ec5cc9fc2969b32308211..f1234cf9446ff968cf7fda64803ccecdd443c113 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
@@ -2,7 +2,7 @@
 --Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
---Date        : Thu Mar 20 18:24:28 2025
+--Date        : Sun Mar 23 23:26:53 2025
 --Host        : hogtest running 64-bit unknown
 --Command     : generate_target mb_design_1_wrapper.bd
 --Design      : mb_design_1_wrapper
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh
new file mode 100644
index 0000000000000000000000000000000000000000..9db39f9c396a060ee382033f2c72cc19be1a852c
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh
@@ -0,0 +1,7337 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Mar 23 23:26:53 2025" VIVADOVERSION="2024.1.2">
+
+  <SYSTEMINFO ARCH="artix7" BOARD="digilentinc.com:nexys_video:part0:1.2" DEVICE="7a200t" NAME="mb_design_1" PACKAGE="sbg484" SPEEDGRADE="-1"/>
+
+  <EXTERNALPORTS>
+    <PORT DIR="O" LEFT="7" NAME="GPIO_0_tri_o" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_gpio_io_o">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="axi_gpio_0" PORT="gpio_io_o"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk_in1" SIGIS="clk" SIGNAME="External_Ports_clk_in1">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_in1"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" LEFT="31" NAME="hog_global_date_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_date_i_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_date_i"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" LEFT="31" NAME="hog_global_sha_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_sha_i_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_sha_i"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" LEFT="31" NAME="hog_global_time_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_time_i_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_time_i"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" LEFT="31" NAME="hog_global_ver_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_ver_i_0">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_ver_i"/>
+      </CONNECTIONS>
+    </PORT>
+    <PORT DIR="I" NAME="reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="External_Ports_reset">
+      <CONNECTIONS>
+        <CONNECTION INSTANCE="clk_wiz_0" PORT="reset"/>
+        <CONNECTION INSTANCE="proc_sys_reset_0" PORT="ext_reset_in"/>
+      </CONNECTIONS>
+    </PORT>
+  </EXTERNALPORTS>
+
+  <EXTERNALINTERFACES>
+    <BUSINTERFACE BUSNAME="axi_gpio_0_GPIO" NAME="GPIO_0" TYPE="INITIATOR">
+      <PORTMAPS>
+        <PORTMAP LOGICAL="TRI_O" PHYSICAL="GPIO_0_tri_o"/>
+      </PORTMAPS>
+    </BUSINTERFACE>
+  </EXTERNALINTERFACES>
+
+  <MODULES>
+    <MODULE COREREVISION="1" FULLNAME="/axi4lite_hog_build_i_0" HWVERSION="1.0" INSTANCE="axi4lite_hog_build_i_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi4lite_hog_build_info" VLNV="xilinx.com:module_ref:axi4lite_hog_build_info:1.0">
+      <DOCUMENTS/>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="0x100000000" USAGE="register"/>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ADDR_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_axi4lite_hog_build_i_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x8000007F"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="31" NAME="hog_global_date_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_date_i_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="hog_global_date_i_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="hog_global_sha_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_sha_i_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="hog_global_sha_i_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="hog_global_time_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_time_i_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="hog_global_time_i_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="hog_global_ver_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_ver_i_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="hog_global_ver_i_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M04_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.0"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="34" FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="4096" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="GPIO_DATA">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Channel-1 AXI GPIO Data register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="CH1_DATA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO Data Register.&#xA;For each I/O bit programmed as input&#xA;  R - Reads value on the input pin.&#xA;  W - No effect.&#xA;For each I/O bit programmed as output&#xA;  R - Reads value on GPIO_O pins&#xA;  W - Writes value to the corresponding AXI GPIO &#xA;      data register bit and output pin&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="GPIO_TRI">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Channel-1 AXI GPIO 3-State Control register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="CH1_TRI">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO 3-State Control Register&#xA;Each I/O pin of the AXI GPIO is individually programmable as an input or output   For each of the bits     0 - I/O pin configured as output     1 - I/O pin configured as input&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="GPIO2_DATA">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Channel-2 AXI GPIO Data register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="CH2_DATA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO Data Register.&#xA;For each I/O bit programmed as input&#xA;  R - Reads value on the input pin.&#xA;  W - No effect.&#xA;For each I/O bit programmed as output&#xA;  R - Reads value on GPIO_O pins&#xA;  W - Writes value to the corresponding AXI GPIO &#xA;      data register bit and output pin&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="GPIO2_TRI">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Channel-2 AXI GPIO 3-State Control register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0xC"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="CH2_TRI">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI GPIO 3-State Control Register&#xA;Each I/O pin of the AXI GPIO is individually programmable as an input or output   For each of the bits     0 - I/O pin configured as output     1 - I/O pin configured as input&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="GIER">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Global_Interrupt_Enable register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x11C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT_EN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Master enable for the device interrupt output&#xA;  0 - Disabled&#xA;  1 - Enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IP_IER">
+              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x128"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="CH1_INT_EN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Channel 1 Interrupt&#xA;  0 - Disabled (masked)&#xA;  1 - Enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CH2_INT_EN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Channel 2 Interrupt&#xA;  0 - Disabled (masked)&#xA;  1 - Enabled&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IP_ISR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x120"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="CH1_INT_S">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Channel 1 Interrupt Status&#xA;  0 - No Channel 1 input interrupt&#xA;  1 - Channel 1 input interrupt&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CH2_INT_S">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Channel 2 Interrupt Status&#xA;  0 - No Channel 2 input interrupt&#xA;  1 - Channel 2 input interrupt&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ALL_INPUTS" VALUE="0"/>
+        <PARAMETER NAME="C_ALL_INPUTS_2" VALUE="0"/>
+        <PARAMETER NAME="C_ALL_OUTPUTS" VALUE="1"/>
+        <PARAMETER NAME="C_ALL_OUTPUTS_2" VALUE="0"/>
+        <PARAMETER NAME="C_DOUT_DEFAULT" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_DOUT_DEFAULT_2" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_GPIO2_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_GPIO_WIDTH" VALUE="8"/>
+        <PARAMETER NAME="C_INTERRUPT_PRESENT" VALUE="0"/>
+        <PARAMETER NAME="C_IS_DUAL" VALUE="0"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_TRI_DEFAULT" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="C_TRI_DEFAULT_2" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_axi_gpio_0_0"/>
+        <PARAMETER NAME="GPIO2_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x40000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x4000FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="7" NAME="gpio_io_o" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_gpio_io_o">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mb_design_1_imp" PORT="GPIO_0_tri_o"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M01_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="9"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.0"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_gpio_0_GPIO" NAME="GPIO" TYPE="INITIATOR" VLNV="xilinx.com:interface:gpio:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="TRI_O" PHYSICAL="gpio_io_o"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="19" FULLNAME="/axi_intc_0" HWVERSION="4.1" INSTANCE="axi_intc_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc" VLNV="xilinx.com:ip:axi_intc:4.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_intc;v=v4_1;d=pg099-axi-intc.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="4096" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="ISR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Status Register.&#xA;For each bit up to number of periperhal interrupts:&#xA;  R - Reads active interrupt signal.&#xA;  W - No effect after MER HIE bit has been set, otherwise writes active interrupt signal.&#xA;For remaining bits defined by number of software interrupts:&#xA;  R - Reads software interrupt value.&#xA;  W - Writes software interrupt value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IPR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Pending Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Pending Register.&#xA;For each bit:&#xA;  R - Reads logical AND of bits in ISR and IER.&#xA;  W - No effect.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IER">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Enable Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Enable Register.&#xA;For each bit:&#xA;  R - Reads interrupt enable value.&#xA;  W - Writes interrupt enable value.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IAR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Acknowledge Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0xC"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Acknowledge Register.&#xA;For each bit:&#xA;  W - Acknowledge interrupt.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="SIE">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Set Interrupt Enables"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Set Interrupt Enables&#xA;For each bit:&#xA;  R - Reads active interrupt.&#xA;  W - Writing 1 enables the interrupt, writing 0 has no effect.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToSet"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="CIE">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Clear Interrupt Enables"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Clear Interrupt Enables&#xA;For each bit:&#xA;  R - Reads active interrupt.&#xA;  W - Writing 1 disables the interrupt, writing 0 has no effect.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
+              <PROPERTY NAME="SIZE" VALUE="5"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="IVN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Number.&#xA;  R - Reads ordinal of highest priority, enabled, active interrupt.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="5"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="MER">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Master Enable Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
+              <PROPERTY NAME="SIZE" VALUE="2"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="ME">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Master IRQ Enable.&#xA;  0 - All interrupts disabled.&#xA;  1 - All interrupts can be enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="HIE">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Hardware Interrupt Enable.&#xA;  0 - HW interrupts disabled.&#xA;  1 - HW interrupts enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IMR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Mode Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Mode Register.&#xA;For each bit:&#xA;  R - Reads interrupt mode.&#xA;  W - Sets interrupt mode, where 0 is normal mode and 1 is fast mode.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="ILR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Level Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x24"/>
+              <PROPERTY NAME="SIZE" VALUE="5"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="ILN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Level Number.&#xA;  R - Reads ordinal of highest priority interrupt not allowed to generate IRQ.&#xA;  W - Writes ordinal of highest priority interrupt not allowed to generate IRQ.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="5"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 0"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x100"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 0 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x104"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 1 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x108"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 2 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_3">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 3"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 3 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_4">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 4"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x110"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 4 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_5">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 5"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x114"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 5 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_6">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 6"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x118"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 6 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_7">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 7"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x11C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 7 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_8">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 8"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x120"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 8 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_9">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 9"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x124"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 9 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_10">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 10"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x128"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 10 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_11">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 11"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x12C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 11 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_12">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 12"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x130"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 12 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_13">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 13"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x134"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 13 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_14">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 14"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x138"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 14 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_15">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 15"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x13C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 15 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_16">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 16"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x140"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 16 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_17">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 17"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x144"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 17 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_18">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 18"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x148"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 18 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_19">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 19"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 19 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_20">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 20"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x150"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 20 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_21">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 21"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x154"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 21 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_22">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 22"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x158"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 22 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_23">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 23"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x15C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 23 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_24">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 24"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x160"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 24 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_25">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 25"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x164"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 25 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_26">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 26"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x168"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 26 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_27">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 27"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x16C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 27 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_28">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 28"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x170"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 28 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_29">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 29"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x174"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 29 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_30">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 30"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x178"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 30 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVAR_31">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 31"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x17C"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 31 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 0"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x200"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 0 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 1"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x208"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 1 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_2">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 2"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x210"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 2 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_3">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 3"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x218"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 3 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_4">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 4"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x220"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 4 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_5">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 5"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x228"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 5 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_6">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 6"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x230"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 6 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_7">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 7"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x238"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 7 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_8">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 8"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x240"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 8 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_9">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 9"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x248"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 9 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_10">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 10"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x250"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 10 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_11">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 11"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x258"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 11 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_12">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 12"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x260"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 12 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_13">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 13"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x268"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 13 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_14">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 14"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x270"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 14 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_15">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 15"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x278"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 15 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_16">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 16"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x280"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 16 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_17">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 17"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x288"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 17 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_18">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 18"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x290"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 18 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_19">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 19"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x298"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 19 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_20">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 20"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2A0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 20 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_21">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 21"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2A8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 21 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_22">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 22"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2B0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 22 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_23">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 23"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2B8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 23 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_24">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 24"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 24 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_25">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 25"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 25 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_26">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 26"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2D0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 26 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_27">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 27"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2D8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 27 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_28">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 28"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2E0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 28 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_29">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 29"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2E8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 29 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_30">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 30"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2F0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 30 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="IVEAR_31">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 31"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2F8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
+              <FIELDS>
+                <FIELD NAME="IVA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 31 with highest priority.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ASYNC_INTR" VALUE="0xFFFFFFFE"/>
+        <PARAMETER NAME="C_CASCADE_MASTER" VALUE="0"/>
+        <PARAMETER NAME="C_DISABLE_SYNCHRONIZERS" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_ASYNC" VALUE="0"/>
+        <PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="0"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_HAS_CIE" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_FAST" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_ILR" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_IPR" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_IVR" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_SIE" VALUE="1"/>
+        <PARAMETER NAME="C_INSTANCE" VALUE="mb_design_1_axi_intc_0_0"/>
+        <PARAMETER NAME="C_IRQ_ACTIVE" VALUE="0x1"/>
+        <PARAMETER NAME="C_IRQ_IS_LEVEL" VALUE="1"/>
+        <PARAMETER NAME="C_IVAR_RESET_VALUE" VALUE="0x0000000000000010"/>
+        <PARAMETER NAME="C_KIND_OF_EDGE" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="C_KIND_OF_INTR" VALUE="0xfffffffe"/>
+        <PARAMETER NAME="C_KIND_OF_LVL" VALUE="0xFFFFFFFF"/>
+        <PARAMETER NAME="C_MB_CLK_NOT_CONNECTED" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_INTR_INPUTS" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_SW_INTR" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF" VALUE="2"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_IRQ_CONNECTION" VALUE="0"/>
+        <PARAMETER NAME="C_PROCESSOR_CLK_FREQ_MHZ" VALUE="100.0"/>
+        <PARAMETER NAME="C_S_AXI_ACLK_FREQ_MHZ" VALUE="100.0"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_axi_intc_0_0"/>
+        <PARAMETER NAME="Sense_of_IRQ_Edge_Type" VALUE="Rising"/>
+        <PARAMETER NAME="Sense_of_IRQ_Level_Type" VALUE="Active_High"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="INTR_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x41200000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x4120FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="intr" RIGHT="0" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xlconcat_0_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconcat_0" PORT="dout"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="irq" SIGIS="undef" SIGNAME="axi_intc_0_irq">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Interrupt"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M03_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="9"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.0"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="interrupt" TYPE="INITIATOR" VLNV="xilinx.com:interface:mbinterrupt:1.0">
+          <PARAMETER NAME="LOW_LATENCY" VALUE="0"/>
+          <PARAMETER NAME="SENSITIVITY" VALUE="LEVEL_HIGH"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="INTERRUPT" PHYSICAL="irq"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="33" FULLNAME="/axi_interconnect_0" HWVERSION="2.1" INSTANCE="axi_interconnect_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_axi_interconnect_0_0"/>
+        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+        <PARAMETER NAME="NUM_MI" VALUE="5"/>
+        <PARAMETER NAME="NUM_SI" VALUE="1"/>
+        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+        <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
+        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
+        <PARAMETER NAME="STRATEGY" VALUE="0"/>
+        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="interconnect_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_arready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_arvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_awready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_bready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_rready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_rvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M01_AXI_wready" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_gpio_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M03_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M03_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M03_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M03_AXI_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M03_AXI_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M04_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_arready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_arvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_awready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_awvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_bready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_bvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M04_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_rready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M04_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_rvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M04_AXI_wready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M04_AXI_wvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M01_AXI" DATAWIDTH="32" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M02_AXI" DATAWIDTH="32" NAME="M02_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M02_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M02_AXI_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M02_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M02_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M02_AXI_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M02_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M02_AXI_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M02_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M02_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M02_AXI_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M02_AXI_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M02_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M02_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M02_AXI_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M02_AXI_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M02_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M02_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M03_AXI" DATAWIDTH="32" NAME="M03_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M03_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M03_AXI_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M03_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M03_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M03_AXI_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M03_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M03_AXI_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M03_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M03_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M03_AXI_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M03_AXI_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M03_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M03_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M03_AXI_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M03_AXI_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M03_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M03_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M04_AXI" DATAWIDTH="32" NAME="M04_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M04_AXI_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M04_AXI_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M04_AXI_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M04_AXI_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M04_AXI_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M04_AXI_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M04_AXI_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M04_AXI_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M04_AXI_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M04_AXI_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M04_AXI_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M04_AXI_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M04_AXI_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M04_AXI_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M04_AXI_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M04_AXI_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M04_AXI_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="34" FULLNAME="/axi_timer_0" HWVERSION="2.0" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_timer" VLNV="xilinx.com:ip:axi_timer:2.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v2_0;d=pg079-axi-timer.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="512" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="TCSR0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Control and Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="MDT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Mode&#xA;0 - Timer mode is generate&#xA;1 - Timer mode is capture&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="UDT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Up/Down Count Timer 0&#xA;  0 - Timer functions as up counter&#xA;  1 - Timer functions as down counter&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="GENT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Generate Signal Timer 0&#xA;  0 - Disables external generate signal&#xA;  1 - Enables external generate signal&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CAPT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Capture Trigger Timer 0&#xA;  0 - Disables external capture trigger&#xA;  1 - Enables external capture trigger&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ARHT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Auto Reload/Hold Timer 0.&#xA;When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. &#xA;In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.      0 = Hold counter or capture value. The TLR must be read before providing the external capture.      1 = Reload generate value or overwrite capture value&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="LOAD0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Load Timer 0      0 = No load      1 = Loads timer with value in TLR0 Setting this bit loads timer/counter register (TCR0) with a specified value in the timer/counter load register (TLR0).  This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT0) bit in TCSR0.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENIT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Interrupt for Timer 0&#xA;Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T0INT) in TCSR0.      0 - Disable interrupt signal   1 - Enable interrupt signal&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENT0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Timer 0&#xA;  0 - Disable timer (counter halts)&#xA;  1 - Enable timer (counter runs)&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="T0INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Interrupt&#xA;Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.&#xA;Read:      0 - No interrupt has occurred      1 - Interrupt has occurred  Write:      0 - No change in state of T0INT   1 - Clear T0INT (clear to 0)&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="PWMA0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Pulse Width Modulation for Timer 0      0 - Disable pulse width modulation      1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair.  Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0 and C_GEN0_ASSERT and C_GEN1_ASSERT must be 1.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENALL">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable All Timers      0 - No effect on timers      1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. &#xA;Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CASC">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable cascade mode of timers      0 - Disable cascaded operation      1 - Enable cascaded operation Cascaded operation requires using Timer 0 and Timer 1 together as a pair.  The counting event for the Timer 1 is when the Timer 0 rolls over from all 1s to all 0s or vice-versa when counting down.&#xA;TLR0 and TLR1 are used for lower 32-bit and higher 32-bit respectively. Similarly, TCR0 contains lower 32-bits for the 64-bit counter and TCR1 contains the higher 32-bits.&#xA;Only TCSR0 is valid for both the timer/counters in this mode.&#xA;This CASC bit must be set before enabling the timer/counter.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TLR0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Load Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="TCLR0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Load Register&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TCR0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Counter Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="TCR0">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Register&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TCSR1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Control and Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="MDT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Mode&#xA;  0 - Timer mode is generate&#xA;  1 - Timer mode is capture&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="UDT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Up/Down Count Timer 1&#xA;  0 - Timer functions as up counter&#xA;  1 - Timer functions as down counter&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="GENT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Generate Signal Timer 1&#xA;  0 - Disables external generate signal&#xA;  1 - Enables external generate signal&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CAPT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Capture Trigger Timer 1&#xA;  0 - Disables external capture trigger&#xA;  1 - Enables external capture trigger&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ARHT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Auto Reload/Hold Timer 1.&#xA;When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. &#xA;In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.&#xA;0 = Hold counter or capture value. The TLR must be read before providing the external capture.   &#xA;1 = Reload generate value or overwrite capture value&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="LOAD1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Load Timer 1      0 = No load      1 = Loads timer with value in TLR1 Setting this bit loads timer/counter register (TCR1) with a specified value in the timer/counter load register (TLR1).  This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT1) bit in TCSR1.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENIT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Interrupt for Timer 1&#xA;Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T1INT) in TCSR1.      0 - Disable interrupt signal      1 - Enable interrupt signal&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENT1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Timer 1&#xA;  0 - Disable timer (counter halts)&#xA;  1 - Enable timer (counter runs)&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="T1INT">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Interrupt&#xA;Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.&#xA;Read:      0 - No interrupt has occurred      1 - Interrupt has occurred  Write:      0 - No change in state of T0INT      1 - Clear T1INT (clear to 0)&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="PWMA1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable Pulse Width Modulation for Timer 1      0 - Disable pulse width modulation      1 - Enable pulse width modulation  PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENALL">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable All Timers      0 - No effect on timers      1 - Enable all timers (counters run)  This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. &#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TLR1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Load Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="TCLR1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Load Register&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TCR1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Counter Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="TCR1">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Register&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_COUNT_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_GEN0_ASSERT" VALUE="1"/>
+        <PARAMETER NAME="C_GEN1_ASSERT" VALUE="1"/>
+        <PARAMETER NAME="C_ONE_TIMER_ONLY" VALUE="1"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_TRIG0_ASSERT" VALUE="1"/>
+        <PARAMETER NAME="C_TRIG1_ASSERT" VALUE="1"/>
+        <PARAMETER NAME="COUNT_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_axi_timer_0_0"/>
+        <PARAMETER NAME="GEN0_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="GEN1_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="TRIG0_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="TRIG1_ASSERT" VALUE="Active_High"/>
+        <PARAMETER NAME="enable_timer2" VALUE="0"/>
+        <PARAMETER NAME="mode_64bit" VALUE="0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x41C00000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x41C0FFFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="capturetrig0" SIGIS="undef"/>
+        <PORT DIR="I" NAME="capturetrig1" SIGIS="undef"/>
+        <PORT DIR="I" NAME="freeze" SIGIS="undef"/>
+        <PORT DIR="O" NAME="generateout0" SIGIS="undef"/>
+        <PORT DIR="O" NAME="generateout1" SIGIS="undef"/>
+        <PORT DIR="O" NAME="interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_timer_0_interrupt">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="xlconcat_0" PORT="In0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="pwm0" SIGIS="undef"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M02_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="5"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.0"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="8" FULLNAME="/blk_mem_gen_0" HWVERSION="8.4" INSTANCE="blk_mem_gen_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY" MODTYPE="blk_mem_gen" VLNV="xilinx.com:ip:blk_mem_gen:8.4">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=blk_mem_gen;v=v8_4;d=pg058-blk-mem-gen.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ADDRA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ADDRB_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_ALGORITHM" VALUE="1"/>
+        <PARAMETER NAME="C_AXI_ID_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_AXI_SLAVE_TYPE" VALUE="0"/>
+        <PARAMETER NAME="C_AXI_TYPE" VALUE="1"/>
+        <PARAMETER NAME="C_BYTE_SIZE" VALUE="8"/>
+        <PARAMETER NAME="C_COMMON_CLK" VALUE="0"/>
+        <PARAMETER NAME="C_COUNT_18K_BRAM" VALUE="0"/>
+        <PARAMETER NAME="C_COUNT_36K_BRAM" VALUE="8"/>
+        <PARAMETER NAME="C_CTRL_ECC_ALGO" VALUE="NONE"/>
+        <PARAMETER NAME="C_DEFAULT_DATA" VALUE="0"/>
+        <PARAMETER NAME="C_DISABLE_WARN_BHV_COLL" VALUE="0"/>
+        <PARAMETER NAME="C_DISABLE_WARN_BHV_RANGE" VALUE="0"/>
+        <PARAMETER NAME="C_ELABORATION_DIR" VALUE="./"/>
+        <PARAMETER NAME="C_ENABLE_32BIT_ADDRESS" VALUE="1"/>
+        <PARAMETER NAME="C_EN_DEEPSLEEP_PIN" VALUE="0"/>
+        <PARAMETER NAME="C_EN_ECC_PIPE" VALUE="0"/>
+        <PARAMETER NAME="C_EN_RDADDRA_CHG" VALUE="0"/>
+        <PARAMETER NAME="C_EN_RDADDRB_CHG" VALUE="0"/>
+        <PARAMETER NAME="C_EN_SAFETY_CKT" VALUE="1"/>
+        <PARAMETER NAME="C_EN_SHUTDOWN_PIN" VALUE="0"/>
+        <PARAMETER NAME="C_EN_SLEEP_PIN" VALUE="0"/>
+        <PARAMETER NAME="C_EST_POWER_SUMMARY" VALUE="Estimated Power for IP     :     20.388 mW"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_HAS_AXI_ID" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_ENA" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_ENB" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_INJECTERR" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_A" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MEM_OUTPUT_REGS_B" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_A" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_MUX_OUTPUT_REGS_B" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_REGCEA" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_REGCEB" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_RSTA" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_RSTB" VALUE="1"/>
+        <PARAMETER NAME="C_HAS_SOFTECC_INPUT_REGS_A" VALUE="0"/>
+        <PARAMETER NAME="C_HAS_SOFTECC_OUTPUT_REGS_B" VALUE="0"/>
+        <PARAMETER NAME="C_INITA_VAL" VALUE="0"/>
+        <PARAMETER NAME="C_INITB_VAL" VALUE="0"/>
+        <PARAMETER NAME="C_INIT_FILE" VALUE="mb_design_1_blk_mem_gen_0_0.mem"/>
+        <PARAMETER NAME="C_INIT_FILE_NAME" VALUE="no_coe_file_loaded"/>
+        <PARAMETER NAME="C_INTERFACE_TYPE" VALUE="0"/>
+        <PARAMETER NAME="C_LOAD_INIT_FILE" VALUE="0"/>
+        <PARAMETER NAME="C_MEM_TYPE" VALUE="2"/>
+        <PARAMETER NAME="C_MUX_PIPELINE_STAGES" VALUE="0"/>
+        <PARAMETER NAME="C_PRIM_TYPE" VALUE="1"/>
+        <PARAMETER NAME="C_READ_DEPTH_A" VALUE="8192"/>
+        <PARAMETER NAME="C_READ_DEPTH_B" VALUE="8192"/>
+        <PARAMETER NAME="C_READ_LATENCY_A" VALUE="1"/>
+        <PARAMETER NAME="C_READ_LATENCY_B" VALUE="1"/>
+        <PARAMETER NAME="C_READ_WIDTH_A" VALUE="32"/>
+        <PARAMETER NAME="C_READ_WIDTH_B" VALUE="32"/>
+        <PARAMETER NAME="C_RSTRAM_A" VALUE="0"/>
+        <PARAMETER NAME="C_RSTRAM_B" VALUE="0"/>
+        <PARAMETER NAME="C_RST_PRIORITY_A" VALUE="CE"/>
+        <PARAMETER NAME="C_RST_PRIORITY_B" VALUE="CE"/>
+        <PARAMETER NAME="C_SIM_COLLISION_CHECK" VALUE="ALL"/>
+        <PARAMETER NAME="C_USE_BRAM_BLOCK" VALUE="1"/>
+        <PARAMETER NAME="C_USE_BYTE_WEA" VALUE="1"/>
+        <PARAMETER NAME="C_USE_BYTE_WEB" VALUE="1"/>
+        <PARAMETER NAME="C_USE_DEFAULT_DATA" VALUE="0"/>
+        <PARAMETER NAME="C_USE_ECC" VALUE="0"/>
+        <PARAMETER NAME="C_USE_SOFTECC" VALUE="0"/>
+        <PARAMETER NAME="C_USE_URAM" VALUE="0"/>
+        <PARAMETER NAME="C_WEA_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_WEB_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_WRITE_DEPTH_A" VALUE="8192"/>
+        <PARAMETER NAME="C_WRITE_DEPTH_B" VALUE="8192"/>
+        <PARAMETER NAME="C_WRITE_MODE_A" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="C_WRITE_MODE_B" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="C_WRITE_WIDTH_A" VALUE="32"/>
+        <PARAMETER NAME="C_WRITE_WIDTH_B" VALUE="32"/>
+        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="AXI_ID_Width" VALUE="4"/>
+        <PARAMETER NAME="AXI_Slave_Type" VALUE="Memory_Slave"/>
+        <PARAMETER NAME="AXI_Type" VALUE="AXI4_Full"/>
+        <PARAMETER NAME="Additional_Inputs_for_Power_Estimation" VALUE="false"/>
+        <PARAMETER NAME="Algorithm" VALUE="Minimum_Area"/>
+        <PARAMETER NAME="Assume_Synchronous_Clk" VALUE="false"/>
+        <PARAMETER NAME="Byte_Size" VALUE="8"/>
+        <PARAMETER NAME="CTRL_ECC_ALGO" VALUE="NONE"/>
+        <PARAMETER NAME="Coe_File" VALUE="no_coe_file_loaded"/>
+        <PARAMETER NAME="Collision_Warnings" VALUE="ALL"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_blk_mem_gen_0_0"/>
+        <PARAMETER NAME="Disable_Collision_Warnings" VALUE="false"/>
+        <PARAMETER NAME="Disable_Out_of_Range_Warnings" VALUE="false"/>
+        <PARAMETER NAME="ECC" VALUE="false"/>
+        <PARAMETER NAME="EN_DEEPSLEEP_PIN" VALUE="false"/>
+        <PARAMETER NAME="EN_ECC_PIPE" VALUE="false"/>
+        <PARAMETER NAME="EN_SAFETY_CKT" VALUE="true"/>
+        <PARAMETER NAME="EN_SHUTDOWN_PIN" VALUE="false"/>
+        <PARAMETER NAME="EN_SLEEP_PIN" VALUE="false"/>
+        <PARAMETER NAME="Enable_32bit_Address" VALUE="true"/>
+        <PARAMETER NAME="Enable_A" VALUE="Use_ENA_Pin"/>
+        <PARAMETER NAME="Enable_B" VALUE="Use_ENB_Pin"/>
+        <PARAMETER NAME="Error_Injection_Type" VALUE="Single_Bit_Error_Injection"/>
+        <PARAMETER NAME="Fill_Remaining_Memory_Locations" VALUE="false"/>
+        <PARAMETER NAME="Interface_Type" VALUE="Native"/>
+        <PARAMETER NAME="Load_Init_File" VALUE="false"/>
+        <PARAMETER NAME="MEM_FILE" VALUE="mb_design_1_blk_mem_gen_0_0.mem"/>
+        <PARAMETER NAME="Memory_Type" VALUE="True_Dual_Port_RAM"/>
+        <PARAMETER NAME="Operating_Mode_A" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="Operating_Mode_B" VALUE="WRITE_FIRST"/>
+        <PARAMETER NAME="Output_Reset_Value_A" VALUE="0"/>
+        <PARAMETER NAME="Output_Reset_Value_B" VALUE="0"/>
+        <PARAMETER NAME="PRIM_type_to_Implement" VALUE="BRAM"/>
+        <PARAMETER NAME="Pipeline_Stages" VALUE="0"/>
+        <PARAMETER NAME="Port_A_Clock" VALUE="100"/>
+        <PARAMETER NAME="Port_A_Enable_Rate" VALUE="100"/>
+        <PARAMETER NAME="Port_A_Write_Rate" VALUE="50"/>
+        <PARAMETER NAME="Port_B_Clock" VALUE="100"/>
+        <PARAMETER NAME="Port_B_Enable_Rate" VALUE="100"/>
+        <PARAMETER NAME="Port_B_Write_Rate" VALUE="50"/>
+        <PARAMETER NAME="Primitive" VALUE="8kx2"/>
+        <PARAMETER NAME="RD_ADDR_CHNG_A" VALUE="false"/>
+        <PARAMETER NAME="RD_ADDR_CHNG_B" VALUE="false"/>
+        <PARAMETER NAME="READ_LATENCY_A" VALUE="1"/>
+        <PARAMETER NAME="READ_LATENCY_B" VALUE="1"/>
+        <PARAMETER NAME="Read_Width_A" VALUE="32"/>
+        <PARAMETER NAME="Read_Width_B" VALUE="32"/>
+        <PARAMETER NAME="Register_PortA_Output_of_Memory_Core" VALUE="false"/>
+        <PARAMETER NAME="Register_PortA_Output_of_Memory_Primitives" VALUE="false"/>
+        <PARAMETER NAME="Register_PortB_Output_of_Memory_Core" VALUE="false"/>
+        <PARAMETER NAME="Register_PortB_Output_of_Memory_Primitives" VALUE="false"/>
+        <PARAMETER NAME="Remaining_Memory_Locations" VALUE="0"/>
+        <PARAMETER NAME="Reset_Memory_Latch_A" VALUE="false"/>
+        <PARAMETER NAME="Reset_Memory_Latch_B" VALUE="false"/>
+        <PARAMETER NAME="Reset_Priority_A" VALUE="CE"/>
+        <PARAMETER NAME="Reset_Priority_B" VALUE="CE"/>
+        <PARAMETER NAME="Reset_Type" VALUE="SYNC"/>
+        <PARAMETER NAME="Use_AXI_ID" VALUE="false"/>
+        <PARAMETER NAME="Use_Byte_Write_Enable" VALUE="true"/>
+        <PARAMETER NAME="Use_Error_Injection_Pins" VALUE="false"/>
+        <PARAMETER NAME="Use_REGCEA_Pin" VALUE="false"/>
+        <PARAMETER NAME="Use_REGCEB_Pin" VALUE="false"/>
+        <PARAMETER NAME="Use_RSTA_Pin" VALUE="true"/>
+        <PARAMETER NAME="Use_RSTB_Pin" VALUE="true"/>
+        <PARAMETER NAME="Write_Depth_A" VALUE="8192"/>
+        <PARAMETER NAME="Write_Width_A" VALUE="32"/>
+        <PARAMETER NAME="Write_Width_B" VALUE="32"/>
+        <PARAMETER NAME="ecctype" VALUE="No_ECC"/>
+        <PARAMETER NAME="register_porta_input_of_softecc" VALUE="false"/>
+        <PARAMETER NAME="register_portb_output_of_softecc" VALUE="false"/>
+        <PARAMETER NAME="softecc" VALUE="false"/>
+        <PARAMETER NAME="use_bram_block" VALUE="BRAM_Controller"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="31" NAME="addra" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_addra">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_Addr_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="addrb" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_addrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_Addr_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="clka" SIGIS="clk" SIGNAME="blk_mem_gen_0_clka">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_Clk_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="clkb" SIGIS="clk" SIGNAME="blk_mem_gen_0_clkb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_Clk_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="dina" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_dina">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_Dout_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="dinb" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_dinb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_Dout_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="douta" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_douta">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_Din_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="doutb" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_doutb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_Din_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ena" SIGIS="undef" SIGNAME="blk_mem_gen_0_ena">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_EN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="enb" SIGIS="undef" SIGNAME="blk_mem_gen_0_enb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_EN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="rsta" SIGIS="rst" SIGNAME="blk_mem_gen_0_rsta">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_Rst_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="rsta_busy" SIGIS="undef"/>
+        <PORT DIR="I" NAME="rstb" SIGIS="rst" SIGNAME="blk_mem_gen_0_rstb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_Rst_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="rstb_busy" SIGIS="undef"/>
+        <PORT DIR="I" LEFT="3" NAME="wea" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_wea">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="BRAM_WEN_A"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="web" RIGHT="0" SIGIS="undef" SIGNAME="blk_mem_gen_0_web">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="BRAM_WEN_A"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="ilmb_bram_if_cntlr_0_BRAM_PORT" NAME="BRAM_PORTA" TYPE="TARGET" VLNV="xilinx.com:interface:bram:1.0">
+          <PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
+          <PARAMETER NAME="MEM_ADDRESS_MODE" VALUE="BYTE_ADDRESS"/>
+          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
+          <PARAMETER NAME="MEM_SIZE" VALUE="32768"/>
+          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ADDR" PHYSICAL="addra"/>
+            <PORTMAP LOGICAL="CLK" PHYSICAL="clka"/>
+            <PORTMAP LOGICAL="DIN" PHYSICAL="dina"/>
+            <PORTMAP LOGICAL="DOUT" PHYSICAL="douta"/>
+            <PORTMAP LOGICAL="EN" PHYSICAL="ena"/>
+            <PORTMAP LOGICAL="RST" PHYSICAL="rsta"/>
+            <PORTMAP LOGICAL="WE" PHYSICAL="wea"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="dlmb_bram_if_cntlr_0_BRAM_PORT" NAME="BRAM_PORTB" TYPE="TARGET" VLNV="xilinx.com:interface:bram:1.0">
+          <PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
+          <PARAMETER NAME="MEM_ADDRESS_MODE" VALUE="BYTE_ADDRESS"/>
+          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
+          <PARAMETER NAME="MEM_SIZE" VALUE="32768"/>
+          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ADDR" PHYSICAL="addrb"/>
+            <PORTMAP LOGICAL="CLK" PHYSICAL="clkb"/>
+            <PORTMAP LOGICAL="DIN" PHYSICAL="dinb"/>
+            <PORTMAP LOGICAL="DOUT" PHYSICAL="doutb"/>
+            <PORTMAP LOGICAL="EN" PHYSICAL="enb"/>
+            <PORTMAP LOGICAL="RST" PHYSICAL="rstb"/>
+            <PORTMAP LOGICAL="WE" PHYSICAL="web"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="14" FULLNAME="/clk_wiz_0" HWVERSION="6.0" INSTANCE="clk_wiz_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_wiz" VLNV="xilinx.com:ip:clk_wiz:6.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clk_wiz;v=v6_0;d=pg065-clk-wiz.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_AUTO_PRIMITIVE" VALUE="MMCM"/>
+        <PARAMETER NAME="C_CDDCDONE_PORT" VALUE="cddcdone"/>
+        <PARAMETER NAME="C_CDDCREQ_PORT" VALUE="cddcreq"/>
+        <PARAMETER NAME="C_CLKFBOUT_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKFBOUT_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
+        <PARAMETER NAME="C_CLKFB_IN_PORT" VALUE="clkfb_in"/>
+        <PARAMETER NAME="C_CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
+        <PARAMETER NAME="C_CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
+        <PARAMETER NAME="C_CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
+        <PARAMETER NAME="C_CLKFB_OUT_PORT" VALUE="clkfb_out"/>
+        <PARAMETER NAME="C_CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
+        <PARAMETER NAME="C_CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
+        <PARAMETER NAME="C_CLKIN1_JITTER_PS" VALUE="100.0"/>
+        <PARAMETER NAME="C_CLKIN2_JITTER_PS" VALUE="100.0"/>
+        <PARAMETER NAME="C_CLKOUT0_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT0_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT0_ACTUAL_FREQ" VALUE="100.00000"/>
+        <PARAMETER NAME="C_CLKOUT1_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT1_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT1_ACTUAL_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT1_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT1_DUTY_CYCLE" VALUE="50.0"/>
+        <PARAMETER NAME="C_CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT1_OUT_FREQ" VALUE="100.00000"/>
+        <PARAMETER NAME="C_CLKOUT1_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT1_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT2_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT2_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT2_ACTUAL_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT2_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT2_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT2_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT2_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT2_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT2_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT2_USED" VALUE="0"/>
+        <PARAMETER NAME="C_CLKOUT3_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT3_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT3_ACTUAL_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT3_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT3_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT3_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT3_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT3_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT3_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT3_USED" VALUE="0"/>
+        <PARAMETER NAME="C_CLKOUT4_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT4_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT4_ACTUAL_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT4_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT4_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT4_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT4_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT4_USED" VALUE="0"/>
+        <PARAMETER NAME="C_CLKOUT5_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT5_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT5_ACTUAL_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT5_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT5_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT5_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT5_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT5_USED" VALUE="0"/>
+        <PARAMETER NAME="C_CLKOUT6_1" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT6_2" VALUE="0000"/>
+        <PARAMETER NAME="C_CLKOUT6_ACTUAL_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT6_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT6_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT6_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT6_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT6_USED" VALUE="0"/>
+        <PARAMETER NAME="C_CLKOUT7_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="C_CLKOUT7_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="C_CLKOUT7_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT7_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="C_CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="C_CLKOUT7_USED" VALUE="0"/>
+        <PARAMETER NAME="C_CLKOUTPHY_MODE" VALUE="VCO"/>
+        <PARAMETER NAME="C_CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
+        <PARAMETER NAME="C_CLK_OUT1_PORT" VALUE="clk_100mhz"/>
+        <PARAMETER NAME="C_CLK_OUT2_PORT" VALUE="clk_out2"/>
+        <PARAMETER NAME="C_CLK_OUT3_PORT" VALUE="clk_out3"/>
+        <PARAMETER NAME="C_CLK_OUT4_PORT" VALUE="clk_out4"/>
+        <PARAMETER NAME="C_CLK_OUT5_PORT" VALUE="clk_out5"/>
+        <PARAMETER NAME="C_CLK_OUT6_PORT" VALUE="clk_out6"/>
+        <PARAMETER NAME="C_CLK_OUT7_PORT" VALUE="clk_out7"/>
+        <PARAMETER NAME="C_CLK_VALID_PORT" VALUE="CLK_VALID"/>
+        <PARAMETER NAME="C_CLOCK_MGR_TYPE" VALUE="NA"/>
+        <PARAMETER NAME="C_DADDR_PORT" VALUE="daddr"/>
+        <PARAMETER NAME="C_DCLK_PORT" VALUE="dclk"/>
+        <PARAMETER NAME="C_DEN_PORT" VALUE="den"/>
+        <PARAMETER NAME="C_DIN_PORT" VALUE="din"/>
+        <PARAMETER NAME="C_DIVCLK" VALUE="0000"/>
+        <PARAMETER NAME="C_DIVIDE1_AUTO" VALUE="1"/>
+        <PARAMETER NAME="C_DIVIDE2_AUTO" VALUE="0.1"/>
+        <PARAMETER NAME="C_DIVIDE3_AUTO" VALUE="0.1"/>
+        <PARAMETER NAME="C_DIVIDE4_AUTO" VALUE="0.1"/>
+        <PARAMETER NAME="C_DIVIDE5_AUTO" VALUE="0.1"/>
+        <PARAMETER NAME="C_DIVIDE6_AUTO" VALUE="0.1"/>
+        <PARAMETER NAME="C_DIVIDE7_AUTO" VALUE="0.1"/>
+        <PARAMETER NAME="C_DOUT_PORT" VALUE="dout"/>
+        <PARAMETER NAME="C_DRDY_PORT" VALUE="drdy"/>
+        <PARAMETER NAME="C_DWE_PORT" VALUE="dwe"/>
+        <PARAMETER NAME="C_D_MAX" VALUE="80.000"/>
+        <PARAMETER NAME="C_D_MIN" VALUE="1.000"/>
+        <PARAMETER NAME="C_ENABLE_CLKOUTPHY" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_CLOCK_MONITOR" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_USER_CLOCK0" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_USER_CLOCK1" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_USER_CLOCK2" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_USER_CLOCK3" VALUE="0"/>
+        <PARAMETER NAME="C_Enable_PLL0" VALUE="0"/>
+        <PARAMETER NAME="C_Enable_PLL1" VALUE="0"/>
+        <PARAMETER NAME="C_FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
+        <PARAMETER NAME="C_FILTER_1" VALUE="0000"/>
+        <PARAMETER NAME="C_FILTER_2" VALUE="0000"/>
+        <PARAMETER NAME="C_HAS_CDDC" VALUE="0"/>
+        <PARAMETER NAME="C_INCLK_SUM_ROW0" VALUE="Input Clock   Freq (MHz)    Input Jitter (UI)"/>
+        <PARAMETER NAME="C_INCLK_SUM_ROW1" VALUE="__primary_________100.000____________0.010"/>
+        <PARAMETER NAME="C_INCLK_SUM_ROW2" VALUE="no_secondary_input_clock"/>
+        <PARAMETER NAME="C_INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
+        <PARAMETER NAME="C_INTERFACE_SELECTION" VALUE="0"/>
+        <PARAMETER NAME="C_IN_FREQ_UNITS" VALUE="Units_MHz"/>
+        <PARAMETER NAME="C_JITTER_SEL" VALUE="No_Jitter"/>
+        <PARAMETER NAME="C_LOCKED_PORT" VALUE="locked"/>
+        <PARAMETER NAME="C_LOCK_1" VALUE="0000"/>
+        <PARAMETER NAME="C_LOCK_2" VALUE="0000"/>
+        <PARAMETER NAME="C_LOCK_3" VALUE="0000"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV1" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV2" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV3" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV4" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV5" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV6" VALUE="false"/>
+        <PARAMETER NAME="C_MMCMBUFGCEDIV7" VALUE="false"/>
+        <PARAMETER NAME="C_MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
+        <PARAMETER NAME="C_MMCM_CLKFBOUT_MULT_F" VALUE="10.000"/>
+        <PARAMETER NAME="C_MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKFBOUT_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKIN1_PERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="C_MMCM_CLKIN2_PERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT0_DIVIDE_F" VALUE="10.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT0_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT1_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT1_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT1_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT2_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT2_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT2_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT3_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT4_CASCADE" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT4_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT5_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_MMCM_CLKOUT6_USE_FINE_PS" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_CLOCK_HOLD" VALUE="FALSE"/>
+        <PARAMETER NAME="C_MMCM_COMPENSATION" VALUE="ZHOLD"/>
+        <PARAMETER NAME="C_MMCM_DIVCLK_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_MMCM_NOTES" VALUE="None"/>
+        <PARAMETER NAME="C_MMCM_REF_JITTER1" VALUE="0.010"/>
+        <PARAMETER NAME="C_MMCM_REF_JITTER2" VALUE="0.010"/>
+        <PARAMETER NAME="C_MMCM_STARTUP_WAIT" VALUE="FALSE"/>
+        <PARAMETER NAME="C_M_MAX" VALUE="64.000"/>
+        <PARAMETER NAME="C_M_MIN" VALUE="2.000"/>
+        <PARAMETER NAME="C_NUM_OUT_CLKS" VALUE="1"/>
+        <PARAMETER NAME="C_OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="0"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW0A" VALUE="Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW0B" VALUE="Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW1" VALUE="clk_100mhz__100.00000______0.000______50.0______130.958_____98.575"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW2" VALUE="no_CLK_OUT2_output"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW3" VALUE="no_CLK_OUT3_output"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW4" VALUE="no_CLK_OUT4_output"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW5" VALUE="no_CLK_OUT5_output"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW6" VALUE="no_CLK_OUT6_output"/>
+        <PARAMETER NAME="C_OUTCLK_SUM_ROW7" VALUE="no_CLK_OUT7_output"/>
+        <PARAMETER NAME="C_OVERRIDE_MMCM" VALUE="0"/>
+        <PARAMETER NAME="C_OVERRIDE_PLL" VALUE="0"/>
+        <PARAMETER NAME="C_O_MAX" VALUE="128.000"/>
+        <PARAMETER NAME="C_O_MIN" VALUE="1.000"/>
+        <PARAMETER NAME="C_PHASESHIFT_MODE" VALUE="WAVEFORM"/>
+        <PARAMETER NAME="C_PLATFORM" VALUE="UNKNOWN"/>
+        <PARAMETER NAME="C_PLLBUFGCEDIV" VALUE="false"/>
+        <PARAMETER NAME="C_PLLBUFGCEDIV1" VALUE="false"/>
+        <PARAMETER NAME="C_PLLBUFGCEDIV2" VALUE="false"/>
+        <PARAMETER NAME="C_PLLBUFGCEDIV3" VALUE="false"/>
+        <PARAMETER NAME="C_PLLBUFGCEDIV4" VALUE="false"/>
+        <PARAMETER NAME="C_PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
+        <PARAMETER NAME="C_PLL_CLKFBOUT_MULT" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLKIN_PERIOD" VALUE="1.000"/>
+        <PARAMETER NAME="C_PLL_CLKOUT0_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_PLL_CLKOUT0_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLKOUT1_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_PLL_CLKOUT1_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLKOUT2_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_PLL_CLKOUT2_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLKOUT3_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_PLL_CLKOUT3_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLKOUT4_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_PLL_CLKOUT4_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLKOUT5_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="C_PLL_CLKOUT5_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="C_PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
+        <PARAMETER NAME="C_PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
+        <PARAMETER NAME="C_PLL_DIVCLK_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="C_PLL_NOTES" VALUE="No notes"/>
+        <PARAMETER NAME="C_PLL_REF_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="C_POWER_DOWN_PORT" VALUE="power_down"/>
+        <PARAMETER NAME="C_POWER_REG" VALUE="0000"/>
+        <PARAMETER NAME="C_PRECISION" VALUE="1"/>
+        <PARAMETER NAME="C_PRIMARY_PORT" VALUE="clk_in1"/>
+        <PARAMETER NAME="C_PRIMITIVE" VALUE="MMCM"/>
+        <PARAMETER NAME="C_PRIMTYPE_SEL" VALUE="AUTO"/>
+        <PARAMETER NAME="C_PRIM_IN_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_PRIM_IN_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="C_PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="C_PRIM_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
+        <PARAMETER NAME="C_PSCLK_PORT" VALUE="psclk"/>
+        <PARAMETER NAME="C_PSDONE_PORT" VALUE="psdone"/>
+        <PARAMETER NAME="C_PSEN_PORT" VALUE="psen"/>
+        <PARAMETER NAME="C_PSINCDEC_PORT" VALUE="psincdec"/>
+        <PARAMETER NAME="C_REF_CLK_FREQ" VALUE="100.0"/>
+        <PARAMETER NAME="C_RESET_LOW" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_PORT" VALUE="reset"/>
+        <PARAMETER NAME="C_SECONDARY_IN_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="C_SECONDARY_IN_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="C_SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="C_SECONDARY_PORT" VALUE="clk_in2"/>
+        <PARAMETER NAME="C_SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
+        <PARAMETER NAME="C_SS_MODE" VALUE="CENTER_HIGH"/>
+        <PARAMETER NAME="C_SS_MOD_PERIOD" VALUE="4000"/>
+        <PARAMETER NAME="C_SS_MOD_TIME" VALUE="0.004"/>
+        <PARAMETER NAME="C_STATUS_PORT" VALUE="STATUS"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="11"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_USER_CLK_FREQ0" VALUE="100.0"/>
+        <PARAMETER NAME="C_USER_CLK_FREQ1" VALUE="100.0"/>
+        <PARAMETER NAME="C_USER_CLK_FREQ2" VALUE="100.0"/>
+        <PARAMETER NAME="C_USER_CLK_FREQ3" VALUE="100.0"/>
+        <PARAMETER NAME="C_USE_CLKFB_STOPPED" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CLKOUT1_BAR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CLKOUT2_BAR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CLKOUT3_BAR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CLKOUT4_BAR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CLK_VALID" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CLOCK_SEQUENCING" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DYN_PHASE_SHIFT" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DYN_RECONFIG" VALUE="0"/>
+        <PARAMETER NAME="C_USE_FAST_SIMULATION" VALUE="0"/>
+        <PARAMETER NAME="C_USE_FREEZE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_FREQ_SYNTH" VALUE="1"/>
+        <PARAMETER NAME="C_USE_INCLK_STOPPED" VALUE="0"/>
+        <PARAMETER NAME="C_USE_INCLK_SWITCHOVER" VALUE="0"/>
+        <PARAMETER NAME="C_USE_LOCKED" VALUE="1"/>
+        <PARAMETER NAME="C_USE_MAX_I_JITTER" VALUE="0"/>
+        <PARAMETER NAME="C_USE_MIN_O_JITTER" VALUE="0"/>
+        <PARAMETER NAME="C_USE_MIN_POWER" VALUE="0"/>
+        <PARAMETER NAME="C_USE_PHASE_ALIGNMENT" VALUE="1"/>
+        <PARAMETER NAME="C_USE_POWER_DOWN" VALUE="0"/>
+        <PARAMETER NAME="C_USE_RESET" VALUE="1"/>
+        <PARAMETER NAME="C_USE_SAFE_CLOCK_STARTUP" VALUE="0"/>
+        <PARAMETER NAME="C_USE_SPREAD_SPECTRUM" VALUE="0"/>
+        <PARAMETER NAME="C_USE_STATUS" VALUE="0"/>
+        <PARAMETER NAME="C_VCO_MAX" VALUE="1200.000"/>
+        <PARAMETER NAME="C_VCO_MIN" VALUE="600.000"/>
+        <PARAMETER NAME="c_component_name" VALUE="mb_design_1_clk_wiz_0_0"/>
+        <PARAMETER NAME="AUTO_PRIMITIVE" VALUE="MMCM"/>
+        <PARAMETER NAME="AXI_DRP" VALUE="false"/>
+        <PARAMETER NAME="CALC_DONE" VALUE="empty"/>
+        <PARAMETER NAME="CDDCDONE_PORT" VALUE="cddcdone"/>
+        <PARAMETER NAME="CDDCREQ_PORT" VALUE="cddcreq"/>
+        <PARAMETER NAME="CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
+        <PARAMETER NAME="CLKFB_IN_PORT" VALUE="clkfb_in"/>
+        <PARAMETER NAME="CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
+        <PARAMETER NAME="CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
+        <PARAMETER NAME="CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
+        <PARAMETER NAME="CLKFB_OUT_PORT" VALUE="clkfb_out"/>
+        <PARAMETER NAME="CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
+        <PARAMETER NAME="CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
+        <PARAMETER NAME="CLKIN1_JITTER_PS" VALUE="100.0"/>
+        <PARAMETER NAME="CLKIN1_UI_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="CLKIN2_JITTER_PS" VALUE="100.0"/>
+        <PARAMETER NAME="CLKIN2_UI_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="CLKOUT1_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT1_JITTER" VALUE="130.958"/>
+        <PARAMETER NAME="CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT1_PHASE_ERROR" VALUE="98.575"/>
+        <PARAMETER NAME="CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT1_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT1_USED" VALUE="true"/>
+        <PARAMETER NAME="CLKOUT2_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT2_JITTER" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT2_PHASE_ERROR" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT2_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT2_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT2_USED" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT3_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT3_JITTER" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT3_PHASE_ERROR" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT3_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT3_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT3_USED" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT4_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT4_JITTER" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT4_PHASE_ERROR" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT4_USED" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT5_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT5_JITTER" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT5_PHASE_ERROR" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT5_USED" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT6_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT6_JITTER" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT6_PHASE_ERROR" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT6_USED" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT7_DRIVES" VALUE="BUFG"/>
+        <PARAMETER NAME="CLKOUT7_JITTER" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
+        <PARAMETER NAME="CLKOUT7_PHASE_ERROR" VALUE="0.0"/>
+        <PARAMETER NAME="CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
+        <PARAMETER NAME="CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
+        <PARAMETER NAME="CLKOUT7_USED" VALUE="false"/>
+        <PARAMETER NAME="CLKOUTPHY_REQUESTED_FREQ" VALUE="600.000"/>
+        <PARAMETER NAME="CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
+        <PARAMETER NAME="CLK_OUT1_PORT" VALUE="clk_100mhz"/>
+        <PARAMETER NAME="CLK_OUT1_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_OUT2_PORT" VALUE="clk_out2"/>
+        <PARAMETER NAME="CLK_OUT2_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_OUT3_PORT" VALUE="clk_out3"/>
+        <PARAMETER NAME="CLK_OUT3_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_OUT4_PORT" VALUE="clk_out4"/>
+        <PARAMETER NAME="CLK_OUT4_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_OUT5_PORT" VALUE="clk_out5"/>
+        <PARAMETER NAME="CLK_OUT5_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_OUT6_PORT" VALUE="clk_out6"/>
+        <PARAMETER NAME="CLK_OUT6_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_OUT7_PORT" VALUE="clk_out7"/>
+        <PARAMETER NAME="CLK_OUT7_USE_FINE_PS_GUI" VALUE="false"/>
+        <PARAMETER NAME="CLK_VALID_PORT" VALUE="CLK_VALID"/>
+        <PARAMETER NAME="CLOCK_MGR_TYPE" VALUE="auto"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_clk_wiz_0_0"/>
+        <PARAMETER NAME="DADDR_PORT" VALUE="daddr"/>
+        <PARAMETER NAME="DCLK_PORT" VALUE="dclk"/>
+        <PARAMETER NAME="DEN_PORT" VALUE="den"/>
+        <PARAMETER NAME="DIFF_CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="DIFF_CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="DIN_PORT" VALUE="din"/>
+        <PARAMETER NAME="DOUT_PORT" VALUE="dout"/>
+        <PARAMETER NAME="DRDY_PORT" VALUE="drdy"/>
+        <PARAMETER NAME="DWE_PORT" VALUE="dwe"/>
+        <PARAMETER NAME="ENABLE_CDDC" VALUE="false"/>
+        <PARAMETER NAME="ENABLE_CLKOUTPHY" VALUE="false"/>
+        <PARAMETER NAME="ENABLE_CLOCK_MONITOR" VALUE="false"/>
+        <PARAMETER NAME="ENABLE_USER_CLOCK0" VALUE="false"/>
+        <PARAMETER NAME="ENABLE_USER_CLOCK1" VALUE="false"/>
+        <PARAMETER NAME="ENABLE_USER_CLOCK2" VALUE="false"/>
+        <PARAMETER NAME="ENABLE_USER_CLOCK3" VALUE="false"/>
+        <PARAMETER NAME="Enable_PLL0" VALUE="false"/>
+        <PARAMETER NAME="Enable_PLL1" VALUE="false"/>
+        <PARAMETER NAME="FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
+        <PARAMETER NAME="INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
+        <PARAMETER NAME="INPUT_MODE" VALUE="frequency"/>
+        <PARAMETER NAME="INTERFACE_SELECTION" VALUE="Enable_AXI"/>
+        <PARAMETER NAME="IN_FREQ_UNITS" VALUE="Units_MHz"/>
+        <PARAMETER NAME="IN_JITTER_UNITS" VALUE="Units_UI"/>
+        <PARAMETER NAME="JITTER_OPTIONS" VALUE="UI"/>
+        <PARAMETER NAME="JITTER_SEL" VALUE="No_Jitter"/>
+        <PARAMETER NAME="LOCKED_PORT" VALUE="locked"/>
+        <PARAMETER NAME="MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
+        <PARAMETER NAME="MMCM_CLKFBOUT_MULT_F" VALUE="10.000"/>
+        <PARAMETER NAME="MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKFBOUT_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKIN1_PERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="MMCM_CLKIN2_PERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT0_DIVIDE_F" VALUE="10.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT0_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT1_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT1_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT1_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT2_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT2_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT2_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT3_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_CASCADE" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT4_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT5_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="MMCM_CLKOUT6_USE_FINE_PS" VALUE="false"/>
+        <PARAMETER NAME="MMCM_CLOCK_HOLD" VALUE="false"/>
+        <PARAMETER NAME="MMCM_COMPENSATION" VALUE="ZHOLD"/>
+        <PARAMETER NAME="MMCM_DIVCLK_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="MMCM_NOTES" VALUE="None"/>
+        <PARAMETER NAME="MMCM_REF_JITTER1" VALUE="0.010"/>
+        <PARAMETER NAME="MMCM_REF_JITTER2" VALUE="0.010"/>
+        <PARAMETER NAME="MMCM_STARTUP_WAIT" VALUE="false"/>
+        <PARAMETER NAME="NUM_OUT_CLKS" VALUE="1"/>
+        <PARAMETER NAME="OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="false"/>
+        <PARAMETER NAME="OVERRIDE_MMCM" VALUE="false"/>
+        <PARAMETER NAME="OVERRIDE_PLL" VALUE="false"/>
+        <PARAMETER NAME="PHASESHIFT_MODE" VALUE="WAVEFORM"/>
+        <PARAMETER NAME="PHASE_DUTY_CONFIG" VALUE="false"/>
+        <PARAMETER NAME="PLATFORM" VALUE="UNKNOWN"/>
+        <PARAMETER NAME="PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
+        <PARAMETER NAME="PLL_CLKFBOUT_MULT" VALUE="4"/>
+        <PARAMETER NAME="PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLKIN_PERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="PLL_CLKOUT0_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="PLL_CLKOUT0_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLKOUT1_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="PLL_CLKOUT1_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLKOUT2_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="PLL_CLKOUT2_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLKOUT3_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="PLL_CLKOUT3_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLKOUT4_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="PLL_CLKOUT4_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLKOUT5_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
+        <PARAMETER NAME="PLL_CLKOUT5_PHASE" VALUE="0.000"/>
+        <PARAMETER NAME="PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
+        <PARAMETER NAME="PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
+        <PARAMETER NAME="PLL_DIVCLK_DIVIDE" VALUE="1"/>
+        <PARAMETER NAME="PLL_NOTES" VALUE="None"/>
+        <PARAMETER NAME="PLL_REF_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="POWER_DOWN_PORT" VALUE="power_down"/>
+        <PARAMETER NAME="PRECISION" VALUE="1"/>
+        <PARAMETER NAME="PRIMARY_PORT" VALUE="clk_in1"/>
+        <PARAMETER NAME="PRIMITIVE" VALUE="MMCM"/>
+        <PARAMETER NAME="PRIMTYPE_SEL" VALUE="mmcm_adv"/>
+        <PARAMETER NAME="PRIM_IN_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="PRIM_IN_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="PRIM_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
+        <PARAMETER NAME="PSCLK_PORT" VALUE="psclk"/>
+        <PARAMETER NAME="PSDONE_PORT" VALUE="psdone"/>
+        <PARAMETER NAME="PSEN_PORT" VALUE="psen"/>
+        <PARAMETER NAME="PSINCDEC_PORT" VALUE="psincdec"/>
+        <PARAMETER NAME="REF_CLK_FREQ" VALUE="100.0"/>
+        <PARAMETER NAME="RELATIVE_INCLK" VALUE="REL_PRIMARY"/>
+        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="RESET_PORT" VALUE="reset"/>
+        <PARAMETER NAME="RESET_TYPE" VALUE="ACTIVE_HIGH"/>
+        <PARAMETER NAME="SECONDARY_IN_FREQ" VALUE="100.000"/>
+        <PARAMETER NAME="SECONDARY_IN_JITTER" VALUE="0.010"/>
+        <PARAMETER NAME="SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
+        <PARAMETER NAME="SECONDARY_PORT" VALUE="clk_in2"/>
+        <PARAMETER NAME="SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
+        <PARAMETER NAME="SS_MODE" VALUE="CENTER_HIGH"/>
+        <PARAMETER NAME="SS_MOD_FREQ" VALUE="250"/>
+        <PARAMETER NAME="SS_MOD_TIME" VALUE="0.004"/>
+        <PARAMETER NAME="STATUS_PORT" VALUE="STATUS"/>
+        <PARAMETER NAME="SUMMARY_STRINGS" VALUE="empty"/>
+        <PARAMETER NAME="USER_CLK_FREQ0" VALUE="100.0"/>
+        <PARAMETER NAME="USER_CLK_FREQ1" VALUE="100.0"/>
+        <PARAMETER NAME="USER_CLK_FREQ2" VALUE="100.0"/>
+        <PARAMETER NAME="USER_CLK_FREQ3" VALUE="100.0"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+        <PARAMETER NAME="USE_CLKFB_STOPPED" VALUE="false"/>
+        <PARAMETER NAME="USE_CLK_VALID" VALUE="false"/>
+        <PARAMETER NAME="USE_CLOCK_SEQUENCING" VALUE="false"/>
+        <PARAMETER NAME="USE_DYN_PHASE_SHIFT" VALUE="false"/>
+        <PARAMETER NAME="USE_DYN_RECONFIG" VALUE="false"/>
+        <PARAMETER NAME="USE_FREEZE" VALUE="false"/>
+        <PARAMETER NAME="USE_FREQ_SYNTH" VALUE="true"/>
+        <PARAMETER NAME="USE_INCLK_STOPPED" VALUE="false"/>
+        <PARAMETER NAME="USE_INCLK_SWITCHOVER" VALUE="false"/>
+        <PARAMETER NAME="USE_LOCKED" VALUE="true"/>
+        <PARAMETER NAME="USE_MAX_I_JITTER" VALUE="false"/>
+        <PARAMETER NAME="USE_MIN_O_JITTER" VALUE="false"/>
+        <PARAMETER NAME="USE_MIN_POWER" VALUE="false"/>
+        <PARAMETER NAME="USE_PHASE_ALIGNMENT" VALUE="true"/>
+        <PARAMETER NAME="USE_POWER_DOWN" VALUE="false"/>
+        <PARAMETER NAME="USE_RESET" VALUE="true"/>
+        <PARAMETER NAME="USE_SAFE_CLOCK_STARTUP" VALUE="false"/>
+        <PARAMETER NAME="USE_SPREAD_SPECTRUM" VALUE="false"/>
+        <PARAMETER NAME="USE_STATUS" VALUE="false"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="clk_100mhz" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Clk"/>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="slowest_sync_clk"/>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_Clk"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="ACLK"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ACLK"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ACLK"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_ACLK"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_ACLK"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_ACLK"/>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_ACLK"/>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aclk"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_ACLK"/>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_aclk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk_in1" SIGIS="clk" SIGNAME="External_Ports_clk_in1">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="clk_in1"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="locked" SIGIS="undef" SIGNAME="clk_wiz_0_locked">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="dcm_locked"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="External_Ports_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="reset"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="24" FULLNAME="/dlmb_bram_if_cntlr_0" HWVERSION="4.0" INSTANCE="dlmb_bram_if_cntlr_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="SLMB" NAME="Mem" RANGE="8192" USAGE="memory"/>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ARBITRATION" VALUE="0"/>
+        <PARAMETER NAME="C_BRAM_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_ECC" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
+        <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="C_MASK" VALUE="0x00000000c0000000"/>
+        <PARAMETER NAME="C_MASK1" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK2" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK3" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK4" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK5" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK6" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK7" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_lmb_bram_if_cntlr_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x00007FFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="blk_mem_gen_0_addrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="addrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="clk" SIGNAME="blk_mem_gen_0_clkb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="clkb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="blk_mem_gen_0_doutb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="doutb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="blk_mem_gen_0_dinb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="dinb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="blk_mem_gen_0_enb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="enb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="rst" SIGNAME="blk_mem_gen_0_rstb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="rstb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="blk_mem_gen_0_web">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="web"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_Rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="proc_sys_reset_0_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="dlmb_v10_0_LMB_Sl_0" DATAWIDTH="32" NAME="SLMB" TYPE="SLAVE" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="LMB_ABus"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP LOGICAL="BE" PHYSICAL="LMB_BE"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="Sl_CE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="Sl_DBus"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="Sl_Ready"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="Sl_UE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="Sl_Wait"/>
+            <PORTMAP LOGICAL="WRITEDBUS" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP LOGICAL="WRITESTROBE" PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="dlmb_bram_if_cntlr_0_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
+          <PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
+          <PARAMETER NAME="MEM_ADDRESS_MODE"/>
+          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
+          <PARAMETER NAME="MEM_SIZE" VALUE="32768"/>
+          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
+          <PARAMETER NAME="READ_WRITE_MODE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ADDR" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP LOGICAL="CLK" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP LOGICAL="DIN" PHYSICAL="BRAM_Dout_A"/>
+            <PORTMAP LOGICAL="DOUT" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP LOGICAL="EN" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP LOGICAL="RST" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP LOGICAL="WE" PHYSICAL="BRAM_WEN_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="14" FULLNAME="/dlmb_v10_0" HWVERSION="3.0" INSTANCE="dlmb_v10_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
+        <PARAMETER NAME="C_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_ilmb_v10_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DCE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_ReadDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Data_Read"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DReady"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DUE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="DWait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_v10_0_M_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Data_Addr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="dlmb_v10_0_M_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="D_AS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_BE" RIGHT="3" SIGIS="undef" SIGNAME="dlmb_v10_0_M_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Byte_Enable"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_DBus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_v10_0_M_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Data_Write"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="dlmb_v10_0_M_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Read_Strobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_WriteStrobe" SIGIS="undef" SIGNAME="dlmb_v10_0_M_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Write_Strobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="SYS_Rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="proc_sys_reset_0_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="dlmb_bram_if_cntlr_0_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="dlmb_v10_0_LMB_Sl_0" DATAWIDTH="32" NAME="LMB_Sl_0" TYPE="SLAVE" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="LMB_ABus"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP LOGICAL="BE" PHYSICAL="LMB_BE"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="Sl_CE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="Sl_DBus"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="Sl_Ready"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="Sl_UE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="Sl_Wait"/>
+            <PORTMAP LOGICAL="WRITEDBUS" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP LOGICAL="WRITESTROBE" PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_DLMB" DATAWIDTH="32" NAME="LMB_M" TYPE="SLAVE" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="M_ABus"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="M_AddrStrobe"/>
+            <PORTMAP LOGICAL="BE" PHYSICAL="M_BE"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="LMB_CE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="LMB_ReadDBus"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="M_ReadStrobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="LMB_Ready"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="LMB_UE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="LMB_Wait"/>
+            <PORTMAP LOGICAL="WRITEDBUS" PHYSICAL="M_DBus"/>
+            <PORTMAP LOGICAL="WRITESTROBE" PHYSICAL="M_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="24" FULLNAME="/ilmb_bram_if_cntlr_0" HWVERSION="4.0" INSTANCE="ilmb_bram_if_cntlr_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" VLNV="xilinx.com:ip:lmb_bram_if_cntlr:4.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_bram_if_cntlr;v=v4_0;d=pg112-lmb-bram-if-cntlr.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ARBITRATION" VALUE="0"/>
+        <PARAMETER NAME="C_BRAM_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_CE_COUNTER_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_CE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_ECC" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_REGISTER" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_ONOFF_RESET_VALUE" VALUE="1"/>
+        <PARAMETER NAME="C_ECC_STATUS_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_FAULT_INJECT" VALUE="0"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="0"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="C_MASK" VALUE="0x0000000000000000"/>
+        <PARAMETER NAME="C_MASK1" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK2" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK3" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK4" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK5" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK6" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_MASK7" VALUE="0x0000000000800000"/>
+        <PARAMETER NAME="C_NUM_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_UE_FAILING_REGISTERS" VALUE="0"/>
+        <PARAMETER NAME="C_WRITE_ACCESS" VALUE="2"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_S_AXI_CTRL_PROTOCOL" VALUE="AXI4LITE"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_lmb_bram_if_cntlr_0_1"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="BRAM_CTRL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x00007FFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Addr_A" RIGHT="31" SIGIS="undef" SIGNAME="blk_mem_gen_0_addra">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="addra"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Clk_A" SIGIS="clk" SIGNAME="blk_mem_gen_0_clka">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="clka"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="BRAM_Din_A" RIGHT="31" SIGIS="undef" SIGNAME="blk_mem_gen_0_douta">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="douta"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_Dout_A" RIGHT="31" SIGIS="undef" SIGNAME="blk_mem_gen_0_dina">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="dina"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_EN_A" SIGIS="undef" SIGNAME="blk_mem_gen_0_ena">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="ena"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="BRAM_Rst_A" SIGIS="rst" SIGNAME="blk_mem_gen_0_rsta">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="rsta"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="BRAM_WEN_A" RIGHT="3" SIGIS="undef" SIGNAME="blk_mem_gen_0_wea">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="blk_mem_gen_0" PORT="wea"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_Rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="proc_sys_reset_0_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_CE" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Ready" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_UE" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Sl_Wait" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="ilmb_v10_0_LMB_Sl_0" DATAWIDTH="32" NAME="SLMB" TYPE="SLAVE" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="LMB_ABus"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP LOGICAL="BE" PHYSICAL="LMB_BE"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="Sl_CE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="Sl_DBus"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="Sl_Ready"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="Sl_UE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="Sl_Wait"/>
+            <PORTMAP LOGICAL="WRITEDBUS" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP LOGICAL="WRITESTROBE" PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="ilmb_bram_if_cntlr_0_BRAM_PORT" NAME="BRAM_PORT" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
+          <PARAMETER NAME="MASTER_TYPE" VALUE="BRAM_CTRL"/>
+          <PARAMETER NAME="MEM_ADDRESS_MODE"/>
+          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
+          <PARAMETER NAME="MEM_SIZE" VALUE="32768"/>
+          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
+          <PARAMETER NAME="READ_WRITE_MODE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ADDR" PHYSICAL="BRAM_Addr_A"/>
+            <PORTMAP LOGICAL="CLK" PHYSICAL="BRAM_Clk_A"/>
+            <PORTMAP LOGICAL="DIN" PHYSICAL="BRAM_Dout_A"/>
+            <PORTMAP LOGICAL="DOUT" PHYSICAL="BRAM_Din_A"/>
+            <PORTMAP LOGICAL="EN" PHYSICAL="BRAM_EN_A"/>
+            <PORTMAP LOGICAL="RST" PHYSICAL="BRAM_Rst_A"/>
+            <PORTMAP LOGICAL="WE" PHYSICAL="BRAM_WEN_A"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="14" FULLNAME="/ilmb_v10_0" HWVERSION="3.0" INSTANCE="ilmb_v10_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="lmb_v10" VLNV="xilinx.com:ip:lmb_v10:3.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=lmb_v10;v=v3_0;d=pg113-lmb-v10.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_LMB_NUM_SLAVES" VALUE="1"/>
+        <PARAMETER NAME="C_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_lmb_v10_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ABus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_AddrStrobe" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_BE" RIGHT="3" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_CE" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="ICE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="LMB_Clk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_ReadDBus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_ReadDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Instr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_ReadStrobe" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Ready" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IReady"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_UE" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IUE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_Wait" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IWAIT"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="LMB_WriteDBus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_WriteDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_WriteDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="LMB_WriteStrobe" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_LMB_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="M_ABus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_v10_0_M_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Instr_Addr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AddrStrobe" SIGIS="undef" SIGNAME="ilmb_v10_0_M_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="I_AS"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_ReadStrobe" SIGIS="undef" SIGNAME="ilmb_v10_0_M_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="IFetch"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="SYS_Rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="proc_sys_reset_0_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="bus_struct_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_CE" RIGHT="0" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="Sl_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_DBus" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="Sl_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Ready" RIGHT="0" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="Sl_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_UE" RIGHT="0" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="Sl_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Sl_Wait" RIGHT="0" SIGIS="undef" SIGNAME="ilmb_bram_if_cntlr_0_Sl_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="Sl_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="ilmb_v10_0_LMB_Sl_0" DATAWIDTH="32" NAME="LMB_Sl_0" TYPE="SLAVE" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="LMB_ABus"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="LMB_AddrStrobe"/>
+            <PORTMAP LOGICAL="BE" PHYSICAL="LMB_BE"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="Sl_CE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="Sl_DBus"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="LMB_ReadStrobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="Sl_Ready"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="Sl_UE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="Sl_Wait"/>
+            <PORTMAP LOGICAL="WRITEDBUS" PHYSICAL="LMB_WriteDBus"/>
+            <PORTMAP LOGICAL="WRITESTROBE" PHYSICAL="LMB_WriteStrobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_ILMB" DATAWIDTH="32" NAME="LMB_M" TYPE="SLAVE" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="M_ABus"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="M_AddrStrobe"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="LMB_CE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="LMB_ReadDBus"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="M_ReadStrobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="LMB_Ready"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="LMB_UE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="LMB_Wait"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+    </MODULE>
+    <MODULE COREREVISION="26" FULLNAME="/mdm_0" HWVERSION="3.2" INSTANCE="mdm_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="DEBUG" MODTYPE="mdm" VLNV="xilinx.com:ip:mdm:3.2">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=mdm;v=v3_2;d=pg115-mdm.pdf"/>
+      </DOCUMENTS>
+      <ADDRESSBLOCKS>
+        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="4096" USAGE="register">
+          <REGISTERS>
+            <REGISTER NAME="UART_RX_FIFO">
+              <PROPERTY NAME="DESCRIPTION" VALUE="JTAG UART Receive Data"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="UART_RX">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="UART Receive Data."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="UART_TX_FIFO">
+              <PROPERTY NAME="DESCRIPTION" VALUE="JTAG UART Transmit Data"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+              <FIELDS>
+                <FIELD NAME="UART_TX">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="UART Transmit Data."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="UART_STATUS">
+              <PROPERTY NAME="DESCRIPTION" VALUE="JTAG UART Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
+              <PROPERTY NAME="SIZE" VALUE="5"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="RX_FIFO_Valid_Data">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates if the receive FIFO has valid data:&#xA;  0 - Receive FIFO is empty.&#xA;  1 - Receive FIFO has valid data.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="RX_FIFO_Full">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates if the receive FIFO is full:&#xA;  0 - Receive FIFO is not full.&#xA;  1 - Receive FIFO is full.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="TX_FIFO_Empty">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates if the transmit FIFO is empty:&#xA;  0 - Transmit FIFO is not empty.&#xA;  1 - Transmit FIFO is empty.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="TX_FIFO_Full">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates if the transmit FIFO is full:&#xA;  0 - Transmit FIFO is not full.&#xA;  1 - Transmit FIFO is full.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Interrupt_Enabled">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates that interrupt is enabled:&#xA;  0 - Interrupt is disabled.&#xA;  1 - Interrupt is enabled.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="UART_CTRL">
+              <PROPERTY NAME="DESCRIPTION" VALUE="JTAG UART Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0xC"/>
+              <PROPERTY NAME="SIZE" VALUE="5"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Reset_TX_FIFO">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reset/clear the transmit FIFO:&#xA;  0 - Do nothing.&#xA;  1 - Clear the transmit FIFO.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Reset_RX_FIFO">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reset/clear the receive FIFO:&#xA;  0 - Do nothing.&#xA;  1 - Clear the receive FIFO.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Clear_EXT_BRK">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Clear the EXT_BRK signal set by JTAG:&#xA;  0 - Do nothing.&#xA;  1 - Clear the signal.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Interrupt_Enabled">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates interrupt for the MDM JTAG UART:&#xA;  0 - Disable interrupt interrupt.&#xA;  1 - Enable interrupt signal.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="DBG_STATUS">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Access Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+              <PROPERTY NAME="SIZE" VALUE="1"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="LOCK">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the access lock status:&#xA;  0 - The lock is not acquired.&#xA;  1 - The lock has been acquired by the JTAG interface.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="DBG_CTRL">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Access Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+              <PROPERTY NAME="SIZE" VALUE="20"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Bit_Size">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Number of bits in the accessed debug register - 1"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="9"/>
+                </FIELD>
+                <FIELD NAME="MDM_Command">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="MDM command."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+                <FIELD NAME="Access_MDM">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Access MDM or MicroBlaze Debug register:&#xA;  0 - MicroBlaze debug register access.&#xA;  1 - MDM debug register access.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="Access_Lock_Type">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Access lock type write:&#xA;  0 - Release access lock to abort atomic sequence.&#xA;  1 - Lock before first access and unlock after last.&#xA;  2 - Lock before first access, otherwise keep lock.&#xA;  3 - Force lock acquisition, even if aquired by JTAG.&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="18"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="DBG_DATA">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Access Data Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="DBG_DATA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Read or write debug register data indicated by DBG_CTRL."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="DBG_LOCK">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Access Locking Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
+              <PROPERTY NAME="SIZE" VALUE="16"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="DBG_LOCK">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Unlock access to registers DBG_CTLR and DBG_DATA when writing 0xEBAB."/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PCCTRLR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Performance Counter Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5440"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="Event">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Performance counter event"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PCCMDR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Performance Counter Command Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5480"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="RES">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Reset accessed counter to the first event counter"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SAM">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Sample status and values in all counters for reading"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="STOP">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Stop counting all counters"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="STA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Start counting configured events for all counters"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CLR">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Clear all counters to zero"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PCSR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Performance Counter Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x54C0"/>
+              <PROPERTY NAME="SIZE" VALUE="2"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="FULL">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Set when a new latency counter event is started before previous event has finished"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="OF">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Set when the counter has counted past its maximum value"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PCDRR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Performance Counter Data Read Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5580"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="ITEM">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Sampled counter value item"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PCDWR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Performance Counter Data Write Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x55C0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="ITEM">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Counter value item to write into a counter"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TCTRLR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Trace Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5840"/>
+              <PROPERTY NAME="SIZE" VALUE="22"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="SR">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Save new program counter for return instructions"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SL">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Save load and get instructions for new data value"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="SPC">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Save new program counter for all taken branches"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="FH">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Debug Halt on full trace buffer or cycle count overflow"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="LEVEL">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Trace compression level:&#xA;  00 - Complete trace&#xA;  01 - Program flow&#xA;  11 - Program flow and cycle count&#xA;"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="2"/>
+                </FIELD>
+                <FIELD NAME="TP">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Change corresponding breakpoint or watchpoint to a tracepoint"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TCMDR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Trace Command Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5880"/>
+              <PROPERTY NAME="SIZE" VALUE="4"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="SAM">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Sample number of current items in the trace buffer"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="STOP">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Stop trace immediately"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="STA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Start trace immediately"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="CLR">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Clear trace status and empty the trace buffer"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TSR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Trace Status Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58C0"/>
+              <PROPERTY NAME="SIZE" VALUE="18"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="IC">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Sampled trace buffer item count"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
+                </FIELD>
+                <FIELD NAME="OF">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Cycle count overflow"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="STA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Trace started"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="17"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="TDRR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Trace Data Read Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5980"/>
+              <PROPERTY NAME="SIZE" VALUE="18"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="ITEM">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Embedded Trace Buffer item"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="18"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PCTRLR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Debug Register Profiling Control Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5C40"/>
+              <PROPERTY NAME="SIZE" VALUE="8"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="BIN">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Number of addresses counted by each bin"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="5"/>
+                </FIELD>
+                <FIELD NAME="CC">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable cycle count to count cycles of executed instructions"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="DIS">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Disable and stop profiling"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+                <FIELD NAME="ENA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Enable and start profiling"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PLAR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Profiling Low Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5C80"/>
+              <PROPERTY NAME="SIZE" VALUE="30"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="LWA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Low word address of the profiled area"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="30"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PHAR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Profiling High Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5CC0"/>
+              <PROPERTY NAME="SIZE" VALUE="30"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="HWA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="High word address of the profiled area"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="30"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PBAR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Profiling Buffer Address Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5D00"/>
+              <PROPERTY NAME="SIZE" VALUE="15"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="BWA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Buffer word address of the profiled area"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="15"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PDRR0">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Profiling Data Read Register, 32 LSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5D80"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="DATA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Number of executed instructions or clock cycles in the bin, 32 LSB"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PDRR1">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Profiling Data Read Register, 4 MSB"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5D84"/>
+              <PROPERTY NAME="SIZE" VALUE="4"/>
+              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="DATA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Number of executed instructions or clock cycles in the bin, 4 MSB"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+            <REGISTER NAME="PDWR">
+              <PROPERTY NAME="DESCRIPTION" VALUE="Profiling Data Write Register"/>
+              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x5DC0"/>
+              <PROPERTY NAME="SIZE" VALUE="32"/>
+              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+              <FIELDS>
+                <FIELD NAME="DATA">
+                  <PROPERTY NAME="DESCRIPTION" VALUE="Data to write to a bin"/>
+                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
+                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+                </FIELD>
+              </FIELDS>
+            </REGISTER>
+          </REGISTERS>
+        </ADDRESSBLOCK>
+      </ADDRESSBLOCKS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ADDR_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_AVOID_PRIMITIVES" VALUE="0"/>
+        <PARAMETER NAME="C_BSCANID" VALUE="76547328"/>
+        <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_DBG_MEM_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_DBG_REG_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_INTERFACE" VALUE="0"/>
+        <PARAMETER NAME="C_DEVICE" VALUE="xc7a200t"/>
+        <PARAMETER NAME="C_EXT_TRIG_RESET_VALUE" VALUE="0xF1234"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
+        <PARAMETER NAME="C_JTAG_CHAIN" VALUE="2"/>
+        <PARAMETER NAME="C_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="C_MB_DBG_PORTS" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXIS_ID_WIDTH" VALUE="7"/>
+        <PARAMETER NAME="C_M_AXI_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_REVISION"/>
+        <PARAMETER NAME="C_S_AXI_ACLK_FREQ_HZ" VALUE="100000000"/>
+        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_TRACE_ASYNC_RESET" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_CLK_FREQ_HZ" VALUE="200000000"/>
+        <PARAMETER NAME="C_TRACE_CLK_OUT_PHASE" VALUE="90"/>
+        <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_TRACE_ID" VALUE="110"/>
+        <PARAMETER NAME="C_TRACE_OUTPUT" VALUE="0"/>
+        <PARAMETER NAME="C_TRACE_PROTOCOL" VALUE="1"/>
+        <PARAMETER NAME="C_USE_BSCAN" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CROSS_TRIGGER" VALUE="0"/>
+        <PARAMETER NAME="C_USE_UART" VALUE="1"/>
+        <PARAMETER NAME="C_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_TRIG_IN_PORTS" VALUE="1"/>
+        <PARAMETER NAME="C_TRIG_OUT_PORTS" VALUE="1"/>
+        <PARAMETER NAME="C_XMTC" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_mdm_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+        <PARAMETER NAME="C_BASEADDR" VALUE="0x41400000"/>
+        <PARAMETER NAME="C_HIGHADDR" VALUE="0x41400FFF"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" NAME="Dbg_Capture_0" SIGIS="undef" SIGNAME="mdm_0_Dbg_Capture_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Capture"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Clk_0" SIGIS="clk" SIGNAME="mdm_0_Dbg_Clk_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Clk"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Disable_0" SIGIS="undef" SIGNAME="mdm_0_Dbg_Disable_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Disable"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGIS="undef" SIGNAME="mdm_0_Dbg_Reg_En_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Reg_En"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Rst_0" SIGIS="rst" SIGNAME="mdm_0_Dbg_Rst_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Debug_Rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Shift_0" SIGIS="undef" SIGNAME="mdm_0_Dbg_Shift_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Shift"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_TDI_0" SIGIS="undef" SIGNAME="mdm_0_Dbg_TDI_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDI"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_TDO_0" SIGIS="undef" SIGNAME="mdm_0_Dbg_TDO_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_TDO"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_Update_0" SIGIS="undef" SIGNAME="mdm_0_Dbg_Update_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Dbg_Update"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Debug_SYS_Rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="mdm_0_Debug_SYS_Rst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="mb_debug_sys_rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="S_AXI_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_ARESETN" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_ARREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_ARVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_AWREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_AWVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_BREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S_AXI_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_BVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="S_AXI_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_RREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="1" NAME="S_AXI_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_RVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="S_AXI_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="S_AXI_WREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="S_AXI_WVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_interconnect_0_M00_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="4"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.0"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXI_ARADDR"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXI_ARREADY"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXI_ARVALID"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXI_AWADDR"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXI_AWREADY"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXI_AWVALID"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXI_BREADY"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXI_BRESP"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXI_BVALID"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXI_RDATA"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXI_RREADY"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXI_RRESP"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXI_RVALID"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXI_WDATA"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXI_WREADY"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXI_WSTRB"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXI_WVALID"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="mdm_0_MBDEBUG_0" NAME="MBDEBUG_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:mbdebug:3.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="CAPTURE" PHYSICAL="Dbg_Capture_0"/>
+            <PORTMAP LOGICAL="CLK" PHYSICAL="Dbg_Clk_0"/>
+            <PORTMAP LOGICAL="DISABLE" PHYSICAL="Dbg_Disable_0"/>
+            <PORTMAP LOGICAL="REG_EN" PHYSICAL="Dbg_Reg_En_0"/>
+            <PORTMAP LOGICAL="RST" PHYSICAL="Dbg_Rst_0"/>
+            <PORTMAP LOGICAL="SHIFT" PHYSICAL="Dbg_Shift_0"/>
+            <PORTMAP LOGICAL="TDI" PHYSICAL="Dbg_TDI_0"/>
+            <PORTMAP LOGICAL="TDO" PHYSICAL="Dbg_TDO_0"/>
+            <PORTMAP LOGICAL="UPDATE" PHYSICAL="Dbg_Update_0"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP/>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="microblaze_0"/>
+      </PERIPHERALS>
+    </MODULE>
+    <MODULE COREREVISION="13" FULLNAME="/microblaze_0" HWVERSION="11.0" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" IS_ENABLE="1" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="microblaze" VLNV="xilinx.com:ip:microblaze:11.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug984-vivado-microblaze-ref.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_ADDR_TAG_BITS" VALUE="0"/>
+        <PARAMETER NAME="C_ALLOW_DCACHE_WR" VALUE="1"/>
+        <PARAMETER NAME="C_ALLOW_ICACHE_WR" VALUE="1"/>
+        <PARAMETER NAME="C_AREA_OPTIMIZED" VALUE="0"/>
+        <PARAMETER NAME="C_ASYNC_INTERRUPT" VALUE="1"/>
+        <PARAMETER NAME="C_ASYNC_WAKEUP" VALUE="3"/>
+        <PARAMETER NAME="C_AVOID_PRIMITIVES" VALUE="0"/>
+        <PARAMETER NAME="C_BASE_VECTORS" VALUE="0x0000000000000000"/>
+        <PARAMETER NAME="C_BRANCH_TARGET_CACHE_SIZE" VALUE="0"/>
+        <PARAMETER NAME="C_CACHE_BYTE_SIZE" VALUE="8192"/>
+        <PARAMETER NAME="C_DADDR_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_DATA_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_DCACHE_ADDR_TAG" VALUE="0"/>
+        <PARAMETER NAME="C_DCACHE_ALWAYS_USED" VALUE="1"/>
+        <PARAMETER NAME="C_DCACHE_BASEADDR" VALUE="0x0000000000000000"/>
+        <PARAMETER NAME="C_DCACHE_BYTE_SIZE" VALUE="8192"/>
+        <PARAMETER NAME="C_DCACHE_DATA_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_DCACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
+        <PARAMETER NAME="C_DCACHE_HIGHADDR" VALUE="0x000000003fffffff"/>
+        <PARAMETER NAME="C_DCACHE_LINE_LEN" VALUE="4"/>
+        <PARAMETER NAME="C_DCACHE_USE_WRITEBACK" VALUE="0"/>
+        <PARAMETER NAME="C_DCACHE_VICTIMS" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_COUNTER_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_DEBUG_ENABLED" VALUE="1"/>
+        <PARAMETER NAME="C_DEBUG_EVENT_COUNTERS" VALUE="5"/>
+        <PARAMETER NAME="C_DEBUG_EXTERNAL_TRACE" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_INTERFACE" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_LATENCY_COUNTERS" VALUE="1"/>
+        <PARAMETER NAME="C_DEBUG_PROFILE_SIZE" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_TRACE_ASYNC_RESET" VALUE="0"/>
+        <PARAMETER NAME="C_DEBUG_TRACE_SIZE" VALUE="8192"/>
+        <PARAMETER NAME="C_DIV_ZERO_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_DYNAMIC_BUS_SIZING" VALUE="0"/>
+        <PARAMETER NAME="C_D_AXI" VALUE="1"/>
+        <PARAMETER NAME="C_D_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_D_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="C_ECC_USE_CE_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_EDGE_IS_POSITIVE" VALUE="1"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_FAULT_TOLERANT" VALUE="0"/>
+        <PARAMETER NAME="C_FPU_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_FREQ" VALUE="100000000"/>
+        <PARAMETER NAME="C_FSL_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_FSL_LINKS" VALUE="0"/>
+        <PARAMETER NAME="C_IADDR_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_ICACHE_ALWAYS_USED" VALUE="1"/>
+        <PARAMETER NAME="C_ICACHE_BASEADDR" VALUE="0x0000000000000000"/>
+        <PARAMETER NAME="C_ICACHE_DATA_WIDTH" VALUE="0"/>
+        <PARAMETER NAME="C_ICACHE_FORCE_TAG_LUTRAM" VALUE="0"/>
+        <PARAMETER NAME="C_ICACHE_HIGHADDR" VALUE="0x000000003fffffff"/>
+        <PARAMETER NAME="C_ICACHE_LINE_LEN" VALUE="4"/>
+        <PARAMETER NAME="C_ICACHE_STREAMS" VALUE="0"/>
+        <PARAMETER NAME="C_ICACHE_VICTIMS" VALUE="0"/>
+        <PARAMETER NAME="C_ILL_OPCODE_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_IMPRECISE_EXCEPTIONS" VALUE="0"/>
+        <PARAMETER NAME="C_INSTANCE" VALUE="mb_design_1_microblaze_0_0"/>
+        <PARAMETER NAME="C_INSTR_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_INTERCONNECT" VALUE="2"/>
+        <PARAMETER NAME="C_INTERRUPT_IS_EDGE" VALUE="0"/>
+        <PARAMETER NAME="C_I_AXI" VALUE="0"/>
+        <PARAMETER NAME="C_I_LMB" VALUE="1"/>
+        <PARAMETER NAME="C_I_LMB_PROTOCOL" VALUE="0"/>
+        <PARAMETER NAME="C_LMB_DATA_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_LOCKSTEP_MASTER" VALUE="0"/>
+        <PARAMETER NAME="C_LOCKSTEP_SLAVE" VALUE="0"/>
+        <PARAMETER NAME="C_M0_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M10_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M11_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M12_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M13_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M14_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M15_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M1_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M2_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M3_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M4_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M5_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M6_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M7_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M8_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M9_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_MMU_DTLB_SIZE" VALUE="4"/>
+        <PARAMETER NAME="C_MMU_ITLB_SIZE" VALUE="2"/>
+        <PARAMETER NAME="C_MMU_PRIVILEGED_INSTR" VALUE="0"/>
+        <PARAMETER NAME="C_MMU_TLB_ACCESS" VALUE="3"/>
+        <PARAMETER NAME="C_MMU_ZONES" VALUE="16"/>
+        <PARAMETER NAME="C_M_AXI_DC_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DC_ARUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_DC_AWUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_DC_BUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DC_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_DC_RUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DC_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DC_USER_VALUE" VALUE="31"/>
+        <PARAMETER NAME="C_M_AXI_DC_WUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_DP_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DP_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_DP_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_D_BUS_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_IC_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IC_ARUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_IC_AWUSER_WIDTH" VALUE="5"/>
+        <PARAMETER NAME="C_M_AXI_IC_BUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IC_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IC_RUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IC_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IC_USER_VALUE" VALUE="31"/>
+        <PARAMETER NAME="C_M_AXI_IC_WUSER_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_IP_ADDR_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IP_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_M_AXI_IP_THREAD_ID_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="C_M_AXI_I_BUS_EXCEPTION" VALUE="0"/>
+        <PARAMETER NAME="C_NUMBER_OF_PC_BRK" VALUE="1"/>
+        <PARAMETER NAME="C_NUMBER_OF_RD_ADDR_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_NUMBER_OF_WR_ADDR_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_CLK" VALUE="2"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_CLK_DEBUG" VALUE="2"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_CLK_IRQ" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_DBG_CLK" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_SYNC_FF_DBG_TRACE_CLK" VALUE="2"/>
+        <PARAMETER NAME="C_OPCODE_0x0_ILLEGAL" VALUE="0"/>
+        <PARAMETER NAME="C_OPTIMIZATION" VALUE="0"/>
+        <PARAMETER NAME="C_PART" VALUE="xc7a200tsbg484-1"/>
+        <PARAMETER NAME="C_PC_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_PIADDR_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_PVR" VALUE="0"/>
+        <PARAMETER NAME="C_PVR_USER1" VALUE="0x00"/>
+        <PARAMETER NAME="C_PVR_USER2" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_RESET_MSR" VALUE="0x00000000"/>
+        <PARAMETER NAME="C_S0_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S10_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S11_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S12_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S13_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S14_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S15_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S1_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S2_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S3_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S4_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S5_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S6_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S7_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S8_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_S9_AXIS_DATA_WIDTH" VALUE="32"/>
+        <PARAMETER NAME="C_SCO" VALUE="0"/>
+        <PARAMETER NAME="C_TEMPORAL_DEPTH" VALUE="0"/>
+        <PARAMETER NAME="C_UNALIGNED_EXCEPTIONS" VALUE="0"/>
+        <PARAMETER NAME="C_USE_BARREL" VALUE="0"/>
+        <PARAMETER NAME="C_USE_BRANCH_TARGET_CACHE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_CONFIG_RESET" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DCACHE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_DIV" VALUE="0"/>
+        <PARAMETER NAME="C_USE_EXTENDED_FSL_INSTR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_EXT_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_USE_EXT_NM_BRK" VALUE="0"/>
+        <PARAMETER NAME="C_USE_FPU" VALUE="0"/>
+        <PARAMETER NAME="C_USE_HW_MUL" VALUE="0"/>
+        <PARAMETER NAME="C_USE_ICACHE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_INTERRUPT" VALUE="1"/>
+        <PARAMETER NAME="C_USE_MMU" VALUE="0"/>
+        <PARAMETER NAME="C_USE_MSR_INSTR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_NON_SECURE" VALUE="0"/>
+        <PARAMETER NAME="C_USE_PCMP_INSTR" VALUE="0"/>
+        <PARAMETER NAME="C_USE_REORDER_INSTR" VALUE="1"/>
+        <PARAMETER NAME="C_USE_STACK_PROTECTION" VALUE="0"/>
+        <PARAMETER NAME="G_TEMPLATE_LIST" VALUE="0"/>
+        <PARAMETER NAME="C_ADDR_SIZE" VALUE="32"/>
+        <PARAMETER NAME="C_DC_AXI_MON" VALUE="0"/>
+        <PARAMETER NAME="C_DP_AXI_MON" VALUE="0"/>
+        <PARAMETER NAME="C_D_LMB_MON" VALUE="0"/>
+        <PARAMETER NAME="C_ENABLE_CONVERSION" VALUE="1"/>
+        <PARAMETER NAME="C_ENABLE_DISCRETE_PORTS" VALUE="0"/>
+        <PARAMETER NAME="C_IC_AXI_MON" VALUE="0"/>
+        <PARAMETER NAME="C_INTERRUPT_MON" VALUE="0"/>
+        <PARAMETER NAME="C_IP_AXI_MON" VALUE="0"/>
+        <PARAMETER NAME="C_I_LMB_MON" VALUE="0"/>
+        <PARAMETER NAME="C_LOCKSTEP_SELECT" VALUE="0"/>
+        <PARAMETER NAME="C_M0_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M10_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M11_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M12_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M13_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M14_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M15_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M1_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M2_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M3_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M4_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M5_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M6_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M7_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M8_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M9_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_M_AXI_DC_USER_SIGNALS" VALUE="0"/>
+        <PARAMETER NAME="C_M_AXI_IC_USER_SIGNALS" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR_BIP" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR_DCE" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR_EE" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR_EIP" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR_ICE" VALUE="0"/>
+        <PARAMETER NAME="C_RESET_MSR_IE" VALUE="0"/>
+        <PARAMETER NAME="C_S0_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S10_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S11_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S12_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S13_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S14_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S15_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S1_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S2_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S3_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S4_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S5_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S6_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S7_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S8_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_S9_AXIS_PROTOCOL" VALUE="GENERIC"/>
+        <PARAMETER NAME="C_TRACE" VALUE="0"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_microblaze_0_0"/>
+        <PARAMETER NAME="G_USE_EXCEPTIONS" VALUE="0"/>
+        <PARAMETER NAME="C_ENDIANNESS" VALUE="1"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PROCESSOR"/>
+        <PARAMETER NAME="EDK_SPECIAL" VALUE="microblaze"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="O" LEFT="0" NAME="Byte_Enable" RIGHT="3" SIGIS="undef" SIGNAME="dlmb_v10_0_M_BE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="M_BE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="Clk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DCE" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DReady" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DUE" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="DWait" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="D_AS" SIGIS="undef" SIGNAME="dlmb_v10_0_M_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="M_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Data_Addr" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_v10_0_M_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="M_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Data_Read" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_v10_0_LMB_ReadDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="LMB_ReadDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Data_Write" RIGHT="31" SIGIS="undef" SIGNAME="dlmb_v10_0_M_DBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="M_DBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Capture" SIGIS="undef" SIGNAME="mdm_0_Dbg_Capture_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Capture_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Clk" SIGIS="clk" SIGNAME="mdm_0_Dbg_Clk_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Clk_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Disable" SIGIS="undef" SIGNAME="mdm_0_Dbg_Disable_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Disable_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Dbg_Reg_En" RIGHT="7" SIGIS="undef" SIGNAME="mdm_0_Dbg_Reg_En_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Reg_En_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Shift" SIGIS="undef" SIGNAME="mdm_0_Dbg_Shift_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Shift_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_TDI" SIGIS="undef" SIGNAME="mdm_0_Dbg_TDI_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_TDI_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Dbg_TDO" SIGIS="undef" SIGNAME="mdm_0_Dbg_TDO_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_TDO_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Dbg_Update" SIGIS="undef" SIGNAME="mdm_0_Dbg_Update_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Update_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Debug_Rst" SIGIS="rst" SIGNAME="mdm_0_Dbg_Rst_0">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Dbg_Rst_0"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ICE" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_CE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_CE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="IFetch" SIGIS="undef" SIGNAME="ilmb_v10_0_M_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="M_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="IReady" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_Ready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_Ready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="IUE" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_UE">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_UE"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="IWAIT" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_Wait">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_Wait"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="I_AS" SIGIS="undef" SIGNAME="ilmb_v10_0_M_AddrStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="M_AddrStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="0" NAME="Instr" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_v10_0_LMB_ReadDBus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="LMB_ReadDBus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="Instr_Addr" RIGHT="31" SIGIS="undef" SIGNAME="ilmb_v10_0_M_ABus">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="M_ABus"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Interrupt" SIGIS="INTERRUPT" SIGNAME="axi_intc_0_irq">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="irq"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_araddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_araddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_arprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_ARREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_arready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_ARVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_arvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awaddr">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_awaddr"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awprot">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_awprot"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_AWREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_awready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_AWVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_awvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_BREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_bready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_bresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_BVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_bvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_rdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_RREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_rready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" LEFT="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rresp">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_rresp"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_RVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_rvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wdata">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_wdata"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="M_AXI_DP_WREADY" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wready">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_wready"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wstrb">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_wstrb"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="M_AXI_DP_WVALID" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wvalid">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_AXI_wvalid"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Read_Strobe" SIGIS="undef" SIGNAME="dlmb_v10_0_M_ReadStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="M_ReadStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="Reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="proc_sys_reset_0_mb_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="mb_reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="Write_Strobe" SIGIS="undef" SIGNAME="dlmb_v10_0_M_WriteStrobe">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="M_WriteStrobe"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES>
+        <BUSINTERFACE BUSNAME="axi_intc_0_interrupt" NAME="INTERRUPT" TYPE="TARGET" VLNV="xilinx.com:interface:mbinterrupt:1.0">
+          <PARAMETER NAME="LOW_LATENCY" VALUE="0"/>
+          <PARAMETER NAME="SENSITIVITY" VALUE="LEVEL_HIGH"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="INTERRUPT" PHYSICAL="Interrupt"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_DLMB" DATAWIDTH="32" NAME="DLMB" TYPE="MASTER" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="Data_Addr"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="D_AS"/>
+            <PORTMAP LOGICAL="BE" PHYSICAL="Byte_Enable"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="DCE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="Data_Read"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="Read_Strobe"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="DReady"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="DUE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="DWait"/>
+            <PORTMAP LOGICAL="WRITEDBUS" PHYSICAL="Data_Write"/>
+            <PORTMAP LOGICAL="WRITESTROBE" PHYSICAL="Write_Strobe"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_ILMB" DATAWIDTH="32" NAME="ILMB" TYPE="MASTER" VLNV="xilinx.com:interface:lmb:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="STANDARD"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ABUS" PHYSICAL="Instr_Addr"/>
+            <PORTMAP LOGICAL="ADDRSTROBE" PHYSICAL="I_AS"/>
+            <PORTMAP LOGICAL="CE" PHYSICAL="ICE"/>
+            <PORTMAP LOGICAL="READDBUS" PHYSICAL="Instr"/>
+            <PORTMAP LOGICAL="READSTROBE" PHYSICAL="IFetch"/>
+            <PORTMAP LOGICAL="READY" PHYSICAL="IReady"/>
+            <PORTMAP LOGICAL="UE" PHYSICAL="IUE"/>
+            <PORTMAP LOGICAL="WAIT" PHYSICAL="IWAIT"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" DATAWIDTH="32" NAME="M_AXI_DP" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
+          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
+          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+          <PARAMETER NAME="PHASE" VALUE="0.0"/>
+          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+          <PORTMAPS>
+            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_DP_ARADDR"/>
+            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_DP_ARPROT"/>
+            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_DP_ARREADY"/>
+            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_DP_ARVALID"/>
+            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_DP_AWADDR"/>
+            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_DP_AWPROT"/>
+            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_DP_AWREADY"/>
+            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_DP_AWVALID"/>
+            <PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_DP_BREADY"/>
+            <PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_DP_BRESP"/>
+            <PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_DP_BVALID"/>
+            <PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_DP_RDATA"/>
+            <PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_DP_RREADY"/>
+            <PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_DP_RRESP"/>
+            <PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_DP_RVALID"/>
+            <PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_DP_WDATA"/>
+            <PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_DP_WREADY"/>
+            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_DP_WSTRB"/>
+            <PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_DP_WVALID"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+        <BUSINTERFACE BUSNAME="mdm_0_MBDEBUG_0" NAME="DEBUG" TYPE="TARGET" VLNV="xilinx.com:interface:mbdebug:3.0">
+          <PORTMAPS>
+            <PORTMAP LOGICAL="CAPTURE" PHYSICAL="Dbg_Capture"/>
+            <PORTMAP LOGICAL="CLK" PHYSICAL="Dbg_Clk"/>
+            <PORTMAP LOGICAL="DISABLE" PHYSICAL="Dbg_Disable"/>
+            <PORTMAP LOGICAL="REG_EN" PHYSICAL="Dbg_Reg_En"/>
+            <PORTMAP LOGICAL="RST" PHYSICAL="Debug_Rst"/>
+            <PORTMAP LOGICAL="SHIFT" PHYSICAL="Dbg_Shift"/>
+            <PORTMAP LOGICAL="TDI" PHYSICAL="Dbg_TDI"/>
+            <PORTMAP LOGICAL="TDO" PHYSICAL="Dbg_TDO"/>
+            <PORTMAP LOGICAL="UPDATE" PHYSICAL="Dbg_Update"/>
+          </PORTMAPS>
+        </BUSINTERFACE>
+      </BUSINTERFACES>
+      <MEMORYMAP>
+        <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007FFF" INSTANCE="dlmb_bram_if_cntlr_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="DLMB" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="SLMB"/>
+        <MEMRANGE ADDRESSBLOCK="Mem" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007FFF" INSTANCE="ilmb_bram_if_cntlr_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="ILMB" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="SLMB"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000FFFF" INSTANCE="axi_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120FFFF" INSTANCE="axi_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41400000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41400FFF" INSTANCE="mdm_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
+        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41C00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41C0FFFF" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
+        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8000007F" INSTANCE="axi4lite_hog_build_i_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
+      </MEMORYMAP>
+      <PERIPHERALS>
+        <PERIPHERAL INSTANCE="dlmb_bram_if_cntlr_0"/>
+        <PERIPHERAL INSTANCE="ilmb_bram_if_cntlr_0"/>
+        <PERIPHERAL INSTANCE="axi_gpio_0"/>
+        <PERIPHERAL INSTANCE="axi_intc_0"/>
+        <PERIPHERAL INSTANCE="mdm_0"/>
+        <PERIPHERAL INSTANCE="axi_timer_0"/>
+        <PERIPHERAL INSTANCE="axi4lite_hog_build_i_0"/>
+      </PERIPHERALS>
+    </MODULE>
+    <MODULE COREREVISION="15" FULLNAME="/proc_sys_reset_0" HWVERSION="5.0" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
+      <DOCUMENTS>
+        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
+      </DOCUMENTS>
+      <PARAMETERS>
+        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
+        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
+        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
+        <PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
+        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
+        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_proc_sys_reset_0_0"/>
+        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
+        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst" SIGNAME="proc_sys_reset_0_bus_struct_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="ilmb_v10_0" PORT="SYS_Rst"/>
+            <CONNECTION INSTANCE="dlmb_v10_0" PORT="SYS_Rst"/>
+            <CONNECTION INSTANCE="ilmb_bram_if_cntlr_0" PORT="LMB_Rst"/>
+            <CONNECTION INSTANCE="dlmb_bram_if_cntlr_0" PORT="LMB_Rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="clk_wiz_0_locked">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="locked"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="External_Ports_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="External_Ports" PORT="reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="proc_sys_reset_0_interconnect_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="ARESETN"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="mdm_0_Debug_SYS_Rst">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="mdm_0" PORT="Debug_SYS_Rst"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="proc_sys_reset_0_mb_reset">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="microblaze_0" PORT="Reset"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ARESETN"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_ARESETN"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_ARESETN"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_ARESETN"/>
+            <CONNECTION INSTANCE="mdm_0" PORT="S_AXI_ARESETN"/>
+            <CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aresetn"/>
+            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_ARESETN"/>
+            <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_aresetn"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
+        <PORT CLKFREQUENCY="100000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+    <MODULE COREREVISION="6" FULLNAME="/xlconcat_0" HWVERSION="2.1" INSTANCE="xlconcat_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconcat" VLNV="xilinx.com:ip:xlconcat:2.1">
+      <DOCUMENTS/>
+      <PARAMETERS>
+        <PARAMETER NAME="IN0_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN100_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN101_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN102_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN103_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN104_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN105_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN106_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN107_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN108_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN109_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN10_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN110_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN111_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN112_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN113_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN114_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN115_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN116_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN117_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN118_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN119_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN11_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN120_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN121_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN122_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN123_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN124_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN125_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN126_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN127_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN12_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN13_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN14_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN15_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN16_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN17_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN18_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN19_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN1_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN20_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN21_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN22_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN23_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN24_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN25_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN26_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN27_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN28_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN29_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN2_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN30_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN31_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN32_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN33_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN34_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN35_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN36_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN37_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN38_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN39_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN3_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN40_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN41_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN42_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN43_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN44_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN45_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN46_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN47_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN48_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN49_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN4_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN50_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN51_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN52_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN53_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN54_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN55_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN56_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN57_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN58_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN59_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN5_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN60_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN61_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN62_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN63_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN64_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN65_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN66_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN67_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN68_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN69_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN6_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN70_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN71_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN72_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN73_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN74_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN75_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN76_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN77_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN78_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN79_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN7_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN80_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN81_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN82_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN83_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN84_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN85_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN86_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN87_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN88_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN89_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN8_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN90_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN91_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN92_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN93_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN94_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN95_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN96_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN97_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN98_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN99_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="IN9_WIDTH" VALUE="1"/>
+        <PARAMETER NAME="NUM_PORTS" VALUE="1"/>
+        <PARAMETER NAME="dout_width" VALUE="1"/>
+        <PARAMETER NAME="Component_Name" VALUE="mb_design_1_xlconcat_0_0"/>
+        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+      </PARAMETERS>
+      <PORTS>
+        <PORT DIR="I" LEFT="0" NAME="In0" RIGHT="0" SIGIS="undef" SIGNAME="axi_timer_0_interrupt">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_timer_0" PORT="interrupt"/>
+          </CONNECTIONS>
+        </PORT>
+        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_0_dout">
+          <CONNECTIONS>
+            <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
+          </CONNECTIONS>
+        </PORT>
+      </PORTS>
+      <BUSINTERFACES/>
+    </MODULE>
+  </MODULES>
+
+</EDKSYSTEM>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.dcp b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..f1a640e7e773b136560a206c63fe2a33d4f20003
Binary files /dev/null and b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.dcp differ
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
index 7388c6fbfe0e74c8a572e6dea5ef275c54dbcc2f..bf4a433cece651afecdc13e7d27a62952ab6ce07 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
@@ -378,7 +378,7 @@
         </spirit:parameter>
         <spirit:parameter>
           <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
           <spirit:vendorExtensions>
             <xilinx:parameterInfo>
               <xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -516,7 +516,7 @@
         </spirit:parameter>
         <spirit:parameter>
           <spirit:name>CLK_DOMAIN</spirit:name>
-          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
           <spirit:vendorExtensions>
             <xilinx:parameterInfo>
               <xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -559,6 +559,101 @@
     </spirit:memoryMap>
   </spirit:memoryMaps>
   <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>axi4lite_hog_build_info</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:81d5be4f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>axi4lite_hog_build_info</spirit:modelName>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cc80f251</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Sun Mar 23 22:27:32 UTC 2025</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cc80f251</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cc80f251</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+        <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>mb_design_1_axi4lite_hog_build_i_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Sun Mar 23 22:26:53 UTC 2025</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:81d5be4f</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+        <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:language>vhdl</spirit:language>
+        <spirit:modelName>mb_design_1_axi4lite_hog_build_i_0_0</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Sun Mar 23 22:26:53 UTC 2025</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:cc80f251</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
     <spirit:ports>
       <spirit:port>
         <spirit:name>s_axi_aclk</spirit:name>
@@ -567,7 +662,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -579,7 +675,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -595,7 +692,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -610,7 +708,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -625,7 +724,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -641,7 +741,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -660,7 +761,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -675,7 +777,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -690,7 +793,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -706,7 +810,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -718,7 +823,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -730,7 +836,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -749,7 +856,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -764,7 +872,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -779,7 +888,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -795,7 +905,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -811,7 +922,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -823,7 +935,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -835,7 +948,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
           <spirit:driver>
@@ -854,7 +968,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -870,7 +985,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -886,7 +1002,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -902,7 +1019,8 @@
           <spirit:wireTypeDefs>
             <spirit:wireTypeDef>
               <spirit:typeName>std_logic_vector</spirit:typeName>
-              <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
         </spirit:wire>
@@ -923,6 +1041,60 @@
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
   <spirit:description>xilinx.com:module_ref:axi4lite_hog_build_info:1.0</spirit:description>
   <spirit:parameters>
     <spirit:parameter>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
new file mode 100644
index 0000000000000000000000000000000000000000..7106145084d166f6f1cd48b55c5833a6112fc7b1
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
@@ -0,0 +1,2003 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+// Date        : Sun Mar 23 23:27:32 2025
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim
+//               /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
+// Design      : mb_design_1_axi4lite_hog_build_i_0_0
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *) 
+(* x_core_info = "axi4lite_hog_build_info,Vivado 2024.1.2" *) 
+(* NotValidForBitStream *)
+module mb_design_1_axi4lite_hog_build_i_0_0
+   (s_axi_aclk,
+    s_axi_aresetn,
+    s_axi_awaddr,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_araddr,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rvalid,
+    s_axi_rready,
+    hog_global_date_i,
+    hog_global_time_i,
+    hog_global_ver_i,
+    hog_global_sha_i);
+  (* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
+  (* x_interface_info = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]s_axi_awaddr;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [31:0]s_axi_araddr;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) output [31:0]s_axi_rdata;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
+  (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
+  input [31:0]hog_global_date_i;
+  input [31:0]hog_global_time_i;
+  input [31:0]hog_global_ver_i;
+  input [31:0]hog_global_sha_i;
+
+  wire \<const0> ;
+  wire [31:0]hog_global_date_i;
+  wire [31:0]hog_global_sha_i;
+  wire [31:0]hog_global_time_i;
+  wire [31:0]hog_global_ver_i;
+  wire s_axi_aclk;
+  wire [31:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready;
+  wire s_axi_arvalid;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  assign s_axi_bresp[1] = \<const0> ;
+  assign s_axi_bresp[0] = \<const0> ;
+  assign s_axi_rresp[1] = \<const0> ;
+  assign s_axi_rresp[0] = \<const0> ;
+  GND GND
+       (.G(\<const0> ));
+  mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info U0
+       (.hog_global_date_i(hog_global_date_i),
+        .hog_global_sha_i(hog_global_sha_i),
+        .hog_global_time_i(hog_global_time_i),
+        .hog_global_ver_i(hog_global_ver_i),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr[7:0]),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready_s_reg(s_axi_arready),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rdata(s_axi_rdata),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_hog_build_info" *) 
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info
+   (s_axi_wready,
+    s_axi_awready,
+    s_axi_rdata,
+    s_axi_arready_s_reg,
+    s_axi_bvalid,
+    s_axi_rvalid,
+    s_axi_aclk,
+    s_axi_awvalid,
+    s_axi_wvalid,
+    s_axi_rready,
+    s_axi_aresetn,
+    s_axi_arvalid,
+    s_axi_araddr,
+    hog_global_ver_i,
+    hog_global_sha_i,
+    hog_global_date_i,
+    hog_global_time_i,
+    s_axi_bready);
+  output s_axi_wready;
+  output s_axi_awready;
+  output [31:0]s_axi_rdata;
+  output s_axi_arready_s_reg;
+  output s_axi_bvalid;
+  output s_axi_rvalid;
+  input s_axi_aclk;
+  input s_axi_awvalid;
+  input s_axi_wvalid;
+  input s_axi_rready;
+  input s_axi_aresetn;
+  input s_axi_arvalid;
+  input [7:0]s_axi_araddr;
+  input [31:0]hog_global_ver_i;
+  input [31:0]hog_global_sha_i;
+  input [31:0]hog_global_date_i;
+  input [31:0]hog_global_time_i;
+  input s_axi_bready;
+
+  wire [31:0]hog_global_date_i;
+  wire [31:0]hog_global_sha_i;
+  wire [31:0]hog_global_time_i;
+  wire [31:0]hog_global_ver_i;
+  wire p_0_in;
+  wire [31:0]p_1_in;
+  wire rd_valid_s;
+  wire s_axi_aclk;
+  wire [7:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready_s_reg;
+  wire s_axi_arvalid;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire [31:0]s_axi_rdata;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if axi4lite_if_inst
+       (.D(p_1_in),
+        .E(rd_valid_s),
+        .SR(p_0_in),
+        .hog_global_date_i(hog_global_date_i),
+        .hog_global_sha_i(hog_global_sha_i),
+        .hog_global_time_i(hog_global_time_i),
+        .hog_global_ver_i(hog_global_ver_i),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready_s_reg(s_axi_arready_s_reg),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+  mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs hog_build_info_regs_inst
+       (.D(p_1_in),
+        .E(rd_valid_s),
+        .SR(p_0_in),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_rdata(s_axi_rdata));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_if" *) 
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if
+   (s_axi_wready,
+    s_axi_awready,
+    s_axi_bvalid,
+    s_axi_arready_s_reg,
+    s_axi_rvalid,
+    D,
+    E,
+    SR,
+    s_axi_aclk,
+    s_axi_rready,
+    s_axi_aresetn,
+    s_axi_arvalid,
+    s_axi_araddr,
+    hog_global_ver_i,
+    hog_global_sha_i,
+    hog_global_date_i,
+    hog_global_time_i,
+    s_axi_wvalid,
+    s_axi_bready,
+    s_axi_awvalid);
+  output s_axi_wready;
+  output s_axi_awready;
+  output s_axi_bvalid;
+  output s_axi_arready_s_reg;
+  output s_axi_rvalid;
+  output [31:0]D;
+  output [0:0]E;
+  input [0:0]SR;
+  input s_axi_aclk;
+  input s_axi_rready;
+  input s_axi_aresetn;
+  input s_axi_arvalid;
+  input [7:0]s_axi_araddr;
+  input [31:0]hog_global_ver_i;
+  input [31:0]hog_global_sha_i;
+  input [31:0]hog_global_date_i;
+  input [31:0]hog_global_time_i;
+  input s_axi_wvalid;
+  input s_axi_bready;
+  input s_axi_awvalid;
+
+  wire [31:0]D;
+  wire [0:0]E;
+  wire [0:0]SR;
+  wire [31:0]hog_global_date_i;
+  wire [31:0]hog_global_sha_i;
+  wire [31:0]hog_global_time_i;
+  wire [31:0]hog_global_ver_i;
+  wire s_axi_aclk;
+  wire [7:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready_s_reg;
+  wire s_axi_arvalid;
+  wire s_axi_awready;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_wready;
+  wire s_axi_wvalid;
+
+  mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if axi4lite_rd_channel_if_i
+       (.D(D),
+        .E(E),
+        .SR(SR),
+        .hog_global_date_i(hog_global_date_i),
+        .hog_global_sha_i(hog_global_sha_i),
+        .hog_global_time_i(hog_global_time_i),
+        .hog_global_ver_i(hog_global_ver_i),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_araddr(s_axi_araddr),
+        .s_axi_aresetn(s_axi_aresetn),
+        .s_axi_arready_s_reg_0(s_axi_arready_s_reg),
+        .s_axi_arvalid(s_axi_arvalid),
+        .s_axi_rready(s_axi_rready),
+        .s_axi_rvalid(s_axi_rvalid));
+  mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if axi4lite_wr_channel_if_i
+       (.SR(SR),
+        .s_axi_aclk(s_axi_aclk),
+        .s_axi_awready(s_axi_awready),
+        .s_axi_awvalid(s_axi_awvalid),
+        .s_axi_bready(s_axi_bready),
+        .s_axi_bvalid(s_axi_bvalid),
+        .s_axi_wready(s_axi_wready),
+        .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_rd_channel_if" *) 
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if
+   (s_axi_arready_s_reg_0,
+    s_axi_rvalid,
+    D,
+    E,
+    SR,
+    s_axi_aclk,
+    s_axi_rready,
+    s_axi_aresetn,
+    s_axi_arvalid,
+    s_axi_araddr,
+    hog_global_ver_i,
+    hog_global_sha_i,
+    hog_global_date_i,
+    hog_global_time_i);
+  output s_axi_arready_s_reg_0;
+  output s_axi_rvalid;
+  output [31:0]D;
+  output [0:0]E;
+  input [0:0]SR;
+  input s_axi_aclk;
+  input s_axi_rready;
+  input s_axi_aresetn;
+  input s_axi_arvalid;
+  input [7:0]s_axi_araddr;
+  input [31:0]hog_global_ver_i;
+  input [31:0]hog_global_sha_i;
+  input [31:0]hog_global_date_i;
+  input [31:0]hog_global_time_i;
+
+  wire [31:0]D;
+  wire [0:0]E;
+  wire [0:0]SR;
+  wire [7:0]addr_s;
+  wire \addr_s[0]_i_1_n_0 ;
+  wire \addr_s[1]_i_1_n_0 ;
+  wire \addr_s[2]_i_1_n_0 ;
+  wire \addr_s[3]_i_1_n_0 ;
+  wire \addr_s[4]_i_1_n_0 ;
+  wire \addr_s[5]_i_1_n_0 ;
+  wire \addr_s[6]_i_1_n_0 ;
+  wire \addr_s[7]_i_1_n_0 ;
+  wire [31:0]hog_global_date_i;
+  wire [31:0]hog_global_sha_i;
+  wire [31:0]hog_global_time_i;
+  wire [31:0]hog_global_ver_i;
+  wire rd_addr_latched;
+  wire rd_addr_latched_i_1_n_0;
+  wire \rd_data_s[0]_i_2_n_0 ;
+  wire \rd_data_s[0]_i_3_n_0 ;
+  wire \rd_data_s[10]_i_2_n_0 ;
+  wire \rd_data_s[10]_i_3_n_0 ;
+  wire \rd_data_s[11]_i_2_n_0 ;
+  wire \rd_data_s[11]_i_3_n_0 ;
+  wire \rd_data_s[12]_i_2_n_0 ;
+  wire \rd_data_s[12]_i_3_n_0 ;
+  wire \rd_data_s[13]_i_2_n_0 ;
+  wire \rd_data_s[13]_i_3_n_0 ;
+  wire \rd_data_s[14]_i_2_n_0 ;
+  wire \rd_data_s[14]_i_3_n_0 ;
+  wire \rd_data_s[15]_i_2_n_0 ;
+  wire \rd_data_s[15]_i_3_n_0 ;
+  wire \rd_data_s[16]_i_2_n_0 ;
+  wire \rd_data_s[16]_i_3_n_0 ;
+  wire \rd_data_s[17]_i_2_n_0 ;
+  wire \rd_data_s[17]_i_3_n_0 ;
+  wire \rd_data_s[18]_i_2_n_0 ;
+  wire \rd_data_s[18]_i_3_n_0 ;
+  wire \rd_data_s[19]_i_2_n_0 ;
+  wire \rd_data_s[19]_i_3_n_0 ;
+  wire \rd_data_s[1]_i_2_n_0 ;
+  wire \rd_data_s[1]_i_3_n_0 ;
+  wire \rd_data_s[20]_i_2_n_0 ;
+  wire \rd_data_s[20]_i_3_n_0 ;
+  wire \rd_data_s[21]_i_2_n_0 ;
+  wire \rd_data_s[21]_i_3_n_0 ;
+  wire \rd_data_s[22]_i_2_n_0 ;
+  wire \rd_data_s[22]_i_3_n_0 ;
+  wire \rd_data_s[23]_i_2_n_0 ;
+  wire \rd_data_s[23]_i_3_n_0 ;
+  wire \rd_data_s[24]_i_2_n_0 ;
+  wire \rd_data_s[24]_i_3_n_0 ;
+  wire \rd_data_s[25]_i_2_n_0 ;
+  wire \rd_data_s[25]_i_3_n_0 ;
+  wire \rd_data_s[26]_i_2_n_0 ;
+  wire \rd_data_s[26]_i_3_n_0 ;
+  wire \rd_data_s[27]_i_2_n_0 ;
+  wire \rd_data_s[27]_i_3_n_0 ;
+  wire \rd_data_s[28]_i_2_n_0 ;
+  wire \rd_data_s[28]_i_3_n_0 ;
+  wire \rd_data_s[29]_i_2_n_0 ;
+  wire \rd_data_s[29]_i_3_n_0 ;
+  wire \rd_data_s[2]_i_2_n_0 ;
+  wire \rd_data_s[2]_i_3_n_0 ;
+  wire \rd_data_s[30]_i_2_n_0 ;
+  wire \rd_data_s[30]_i_3_n_0 ;
+  wire \rd_data_s[31]_i_3_n_0 ;
+  wire \rd_data_s[31]_i_4_n_0 ;
+  wire \rd_data_s[31]_i_5_n_0 ;
+  wire \rd_data_s[31]_i_6_n_0 ;
+  wire \rd_data_s[31]_i_7_n_0 ;
+  wire \rd_data_s[3]_i_2_n_0 ;
+  wire \rd_data_s[3]_i_3_n_0 ;
+  wire \rd_data_s[4]_i_2_n_0 ;
+  wire \rd_data_s[4]_i_3_n_0 ;
+  wire \rd_data_s[5]_i_2_n_0 ;
+  wire \rd_data_s[5]_i_3_n_0 ;
+  wire \rd_data_s[6]_i_2_n_0 ;
+  wire \rd_data_s[6]_i_3_n_0 ;
+  wire \rd_data_s[7]_i_2_n_0 ;
+  wire \rd_data_s[7]_i_3_n_0 ;
+  wire \rd_data_s[8]_i_2_n_0 ;
+  wire \rd_data_s[8]_i_3_n_0 ;
+  wire \rd_data_s[9]_i_2_n_0 ;
+  wire \rd_data_s[9]_i_3_n_0 ;
+  wire s_axi_aclk;
+  wire [7:0]s_axi_araddr;
+  wire s_axi_aresetn;
+  wire s_axi_arready_s_i_1_n_0;
+  wire s_axi_arready_s_reg_0;
+  wire s_axi_arvalid;
+  wire s_axi_rready;
+  wire s_axi_rvalid;
+  wire s_axi_rvalid_s_i_1_n_0;
+
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[0]_i_1 
+       (.I0(addr_s[0]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[0]),
+        .O(\addr_s[0]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[1]_i_1 
+       (.I0(addr_s[1]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[1]),
+        .O(\addr_s[1]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hBF80)) 
+    \addr_s[2]_i_1 
+       (.I0(s_axi_araddr[2]),
+        .I1(s_axi_arvalid),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(addr_s[2]),
+        .O(\addr_s[2]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[3]_i_1 
+       (.I0(addr_s[3]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[3]),
+        .O(\addr_s[3]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[4]_i_1 
+       (.I0(addr_s[4]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[4]),
+        .O(\addr_s[4]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[5]_i_1 
+       (.I0(addr_s[5]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[5]),
+        .O(\addr_s[5]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[6]_i_1 
+       (.I0(addr_s[6]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[6]),
+        .O(\addr_s[6]_i_1_n_0 ));
+  LUT4 #(
+    .INIT(16'hEA2A)) 
+    \addr_s[7]_i_1 
+       (.I0(addr_s[7]),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_arvalid),
+        .I3(s_axi_araddr[7]),
+        .O(\addr_s[7]_i_1_n_0 ));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[0]_i_1_n_0 ),
+        .Q(addr_s[0]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[1]_i_1_n_0 ),
+        .Q(addr_s[1]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[2]_i_1_n_0 ),
+        .Q(addr_s[2]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[3]_i_1_n_0 ),
+        .Q(addr_s[3]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[4]_i_1_n_0 ),
+        .Q(addr_s[4]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[5]_i_1_n_0 ),
+        .Q(addr_s[5]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[6]_i_1_n_0 ),
+        .Q(addr_s[6]),
+        .R(SR));
+  FDRE #(
+    .INIT(1'b0)) 
+    \addr_s_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(\addr_s[7]_i_1_n_0 ),
+        .Q(addr_s[7]),
+        .R(SR));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT4 #(
+    .INIT(16'hEFAA)) 
+    rd_addr_latched_i_1
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_rready),
+        .I3(rd_addr_latched),
+        .O(rd_addr_latched_i_1_n_0));
+  FDRE #(
+    .INIT(1'b0)) 
+    rd_addr_latched_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(rd_addr_latched_i_1_n_0),
+        .Q(rd_addr_latched),
+        .R(SR));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[0]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[0]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[0]_i_3_n_0 ),
+        .O(D[0]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[0]_i_2 
+       (.I0(hog_global_date_i[0]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[0]),
+        .O(\rd_data_s[0]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[0]_i_3 
+       (.I0(hog_global_ver_i[0]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[0]),
+        .O(\rd_data_s[0]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[10]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[10]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[10]_i_3_n_0 ),
+        .O(D[10]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[10]_i_2 
+       (.I0(hog_global_date_i[10]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[10]),
+        .O(\rd_data_s[10]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[10]_i_3 
+       (.I0(hog_global_ver_i[10]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[10]),
+        .O(\rd_data_s[10]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[11]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[11]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[11]_i_3_n_0 ),
+        .O(D[11]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[11]_i_2 
+       (.I0(hog_global_date_i[11]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[11]),
+        .O(\rd_data_s[11]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[11]_i_3 
+       (.I0(hog_global_ver_i[11]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[11]),
+        .O(\rd_data_s[11]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[12]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[12]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[12]_i_3_n_0 ),
+        .O(D[12]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[12]_i_2 
+       (.I0(hog_global_date_i[12]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[12]),
+        .O(\rd_data_s[12]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[12]_i_3 
+       (.I0(hog_global_ver_i[12]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[12]),
+        .O(\rd_data_s[12]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[13]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[13]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[13]_i_3_n_0 ),
+        .O(D[13]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[13]_i_2 
+       (.I0(hog_global_date_i[13]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[13]),
+        .O(\rd_data_s[13]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[13]_i_3 
+       (.I0(hog_global_ver_i[13]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[13]),
+        .O(\rd_data_s[13]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[14]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[14]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[14]_i_3_n_0 ),
+        .O(D[14]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[14]_i_2 
+       (.I0(hog_global_date_i[14]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[14]),
+        .O(\rd_data_s[14]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[14]_i_3 
+       (.I0(hog_global_ver_i[14]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[14]),
+        .O(\rd_data_s[14]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[15]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[15]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[15]_i_3_n_0 ),
+        .O(D[15]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[15]_i_2 
+       (.I0(hog_global_date_i[15]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[15]),
+        .O(\rd_data_s[15]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[15]_i_3 
+       (.I0(hog_global_ver_i[15]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[15]),
+        .O(\rd_data_s[15]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[16]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[16]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[16]_i_3_n_0 ),
+        .O(D[16]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[16]_i_2 
+       (.I0(hog_global_date_i[16]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[16]),
+        .O(\rd_data_s[16]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[16]_i_3 
+       (.I0(hog_global_ver_i[16]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[16]),
+        .O(\rd_data_s[16]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[17]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[17]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[17]_i_3_n_0 ),
+        .O(D[17]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[17]_i_2 
+       (.I0(hog_global_date_i[17]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[17]),
+        .O(\rd_data_s[17]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[17]_i_3 
+       (.I0(hog_global_ver_i[17]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[17]),
+        .O(\rd_data_s[17]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[18]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[18]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[18]_i_3_n_0 ),
+        .O(D[18]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[18]_i_2 
+       (.I0(hog_global_date_i[18]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[18]),
+        .O(\rd_data_s[18]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[18]_i_3 
+       (.I0(hog_global_ver_i[18]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[18]),
+        .O(\rd_data_s[18]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[19]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[19]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[19]_i_3_n_0 ),
+        .O(D[19]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[19]_i_2 
+       (.I0(hog_global_date_i[19]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[19]),
+        .O(\rd_data_s[19]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[19]_i_3 
+       (.I0(hog_global_ver_i[19]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[19]),
+        .O(\rd_data_s[19]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[1]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[1]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[1]_i_3_n_0 ),
+        .O(D[1]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[1]_i_2 
+       (.I0(hog_global_date_i[1]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[1]),
+        .O(\rd_data_s[1]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[1]_i_3 
+       (.I0(hog_global_ver_i[1]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[1]),
+        .O(\rd_data_s[1]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[20]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[20]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[20]_i_3_n_0 ),
+        .O(D[20]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[20]_i_2 
+       (.I0(hog_global_date_i[20]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[20]),
+        .O(\rd_data_s[20]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[20]_i_3 
+       (.I0(hog_global_ver_i[20]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[20]),
+        .O(\rd_data_s[20]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[21]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[21]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[21]_i_3_n_0 ),
+        .O(D[21]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[21]_i_2 
+       (.I0(hog_global_date_i[21]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[21]),
+        .O(\rd_data_s[21]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[21]_i_3 
+       (.I0(hog_global_ver_i[21]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[21]),
+        .O(\rd_data_s[21]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[22]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[22]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[22]_i_3_n_0 ),
+        .O(D[22]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[22]_i_2 
+       (.I0(hog_global_date_i[22]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[22]),
+        .O(\rd_data_s[22]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[22]_i_3 
+       (.I0(hog_global_ver_i[22]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[22]),
+        .O(\rd_data_s[22]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[23]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[23]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[23]_i_3_n_0 ),
+        .O(D[23]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[23]_i_2 
+       (.I0(hog_global_date_i[23]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[23]),
+        .O(\rd_data_s[23]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[23]_i_3 
+       (.I0(hog_global_ver_i[23]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[23]),
+        .O(\rd_data_s[23]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[24]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[24]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[24]_i_3_n_0 ),
+        .O(D[24]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[24]_i_2 
+       (.I0(hog_global_date_i[24]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[24]),
+        .O(\rd_data_s[24]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[24]_i_3 
+       (.I0(hog_global_ver_i[24]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[24]),
+        .O(\rd_data_s[24]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[25]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[25]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[25]_i_3_n_0 ),
+        .O(D[25]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[25]_i_2 
+       (.I0(hog_global_date_i[25]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[25]),
+        .O(\rd_data_s[25]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[25]_i_3 
+       (.I0(hog_global_ver_i[25]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[25]),
+        .O(\rd_data_s[25]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[26]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[26]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[26]_i_3_n_0 ),
+        .O(D[26]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[26]_i_2 
+       (.I0(hog_global_date_i[26]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[26]),
+        .O(\rd_data_s[26]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[26]_i_3 
+       (.I0(hog_global_ver_i[26]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[26]),
+        .O(\rd_data_s[26]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[27]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[27]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[27]_i_3_n_0 ),
+        .O(D[27]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[27]_i_2 
+       (.I0(hog_global_date_i[27]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[27]),
+        .O(\rd_data_s[27]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[27]_i_3 
+       (.I0(hog_global_ver_i[27]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[27]),
+        .O(\rd_data_s[27]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[28]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[28]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[28]_i_3_n_0 ),
+        .O(D[28]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[28]_i_2 
+       (.I0(hog_global_date_i[28]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[28]),
+        .O(\rd_data_s[28]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[28]_i_3 
+       (.I0(hog_global_ver_i[28]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[28]),
+        .O(\rd_data_s[28]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[29]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[29]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[29]_i_3_n_0 ),
+        .O(D[29]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[29]_i_2 
+       (.I0(hog_global_date_i[29]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[29]),
+        .O(\rd_data_s[29]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[29]_i_3 
+       (.I0(hog_global_ver_i[29]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[29]),
+        .O(\rd_data_s[29]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[2]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[2]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[2]_i_3_n_0 ),
+        .O(D[2]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[2]_i_2 
+       (.I0(hog_global_date_i[2]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[2]),
+        .O(\rd_data_s[2]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[2]_i_3 
+       (.I0(hog_global_ver_i[2]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[2]),
+        .O(\rd_data_s[2]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[30]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[30]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[30]_i_3_n_0 ),
+        .O(D[30]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[30]_i_2 
+       (.I0(hog_global_date_i[30]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[30]),
+        .O(\rd_data_s[30]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[30]_i_3 
+       (.I0(hog_global_ver_i[30]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[30]),
+        .O(\rd_data_s[30]_i_3_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT2 #(
+    .INIT(4'h8)) 
+    \rd_data_s[31]_i_1 
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_arready_s_reg_0),
+        .O(E));
+  LUT6 #(
+    .INIT(64'h000000E200000000)) 
+    \rd_data_s[31]_i_2 
+       (.I0(\rd_data_s[31]_i_3_n_0 ),
+        .I1(\addr_s[3]_i_1_n_0 ),
+        .I2(\rd_data_s[31]_i_4_n_0 ),
+        .I3(\rd_data_s[31]_i_5_n_0 ),
+        .I4(\rd_data_s[31]_i_6_n_0 ),
+        .I5(\rd_data_s[31]_i_7_n_0 ),
+        .O(D[31]));
+  LUT6 #(
+    .INIT(64'hFEEEAEEE0222A222)) 
+    \rd_data_s[31]_i_3 
+       (.I0(hog_global_date_i[31]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[31]),
+        .O(\rd_data_s[31]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'hFEEEAEEE0222A222)) 
+    \rd_data_s[31]_i_4 
+       (.I0(hog_global_ver_i[31]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[31]),
+        .O(\rd_data_s[31]_i_4_n_0 ));
+  LUT6 #(
+    .INIT(64'hFAFFFFFFFACCCCCC)) 
+    \rd_data_s[31]_i_5 
+       (.I0(s_axi_araddr[6]),
+        .I1(addr_s[6]),
+        .I2(s_axi_araddr[5]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_arready_s_reg_0),
+        .I5(addr_s[5]),
+        .O(\rd_data_s[31]_i_5_n_0 ));
+  LUT6 #(
+    .INIT(64'hFAFFFFFFFACCCCCC)) 
+    \rd_data_s[31]_i_6 
+       (.I0(s_axi_araddr[7]),
+        .I1(addr_s[7]),
+        .I2(s_axi_araddr[0]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_arready_s_reg_0),
+        .I5(addr_s[0]),
+        .O(\rd_data_s[31]_i_6_n_0 ));
+  LUT6 #(
+    .INIT(64'h0500000005333333)) 
+    \rd_data_s[31]_i_7 
+       (.I0(s_axi_araddr[4]),
+        .I1(addr_s[4]),
+        .I2(s_axi_araddr[1]),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_arready_s_reg_0),
+        .I5(addr_s[1]),
+        .O(\rd_data_s[31]_i_7_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[3]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[3]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[3]_i_3_n_0 ),
+        .O(D[3]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[3]_i_2 
+       (.I0(hog_global_date_i[3]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[3]),
+        .O(\rd_data_s[3]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[3]_i_3 
+       (.I0(hog_global_ver_i[3]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[3]),
+        .O(\rd_data_s[3]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[4]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[4]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[4]_i_3_n_0 ),
+        .O(D[4]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[4]_i_2 
+       (.I0(hog_global_date_i[4]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[4]),
+        .O(\rd_data_s[4]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[4]_i_3 
+       (.I0(hog_global_ver_i[4]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[4]),
+        .O(\rd_data_s[4]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[5]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[5]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[5]_i_3_n_0 ),
+        .O(D[5]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[5]_i_2 
+       (.I0(hog_global_date_i[5]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[5]),
+        .O(\rd_data_s[5]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[5]_i_3 
+       (.I0(hog_global_ver_i[5]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[5]),
+        .O(\rd_data_s[5]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[6]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[6]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[6]_i_3_n_0 ),
+        .O(D[6]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[6]_i_2 
+       (.I0(hog_global_date_i[6]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[6]),
+        .O(\rd_data_s[6]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[6]_i_3 
+       (.I0(hog_global_ver_i[6]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[6]),
+        .O(\rd_data_s[6]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[7]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[7]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[7]_i_3_n_0 ),
+        .O(D[7]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[7]_i_2 
+       (.I0(hog_global_date_i[7]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[7]),
+        .O(\rd_data_s[7]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[7]_i_3 
+       (.I0(hog_global_ver_i[7]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[7]),
+        .O(\rd_data_s[7]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[8]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[8]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[8]_i_3_n_0 ),
+        .O(D[8]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[8]_i_2 
+       (.I0(hog_global_date_i[8]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[8]),
+        .O(\rd_data_s[8]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[8]_i_3 
+       (.I0(hog_global_ver_i[8]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[8]),
+        .O(\rd_data_s[8]_i_3_n_0 ));
+  LUT6 #(
+    .INIT(64'h0000001010100010)) 
+    \rd_data_s[9]_i_1 
+       (.I0(\rd_data_s[31]_i_5_n_0 ),
+        .I1(\rd_data_s[31]_i_6_n_0 ),
+        .I2(\rd_data_s[31]_i_7_n_0 ),
+        .I3(\rd_data_s[9]_i_2_n_0 ),
+        .I4(\addr_s[3]_i_1_n_0 ),
+        .I5(\rd_data_s[9]_i_3_n_0 ),
+        .O(D[9]));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[9]_i_2 
+       (.I0(hog_global_date_i[9]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_time_i[9]),
+        .O(\rd_data_s[9]_i_2_n_0 ));
+  LUT6 #(
+    .INIT(64'h01115111FDDD5DDD)) 
+    \rd_data_s[9]_i_3 
+       (.I0(hog_global_ver_i[9]),
+        .I1(addr_s[2]),
+        .I2(s_axi_arready_s_reg_0),
+        .I3(s_axi_arvalid),
+        .I4(s_axi_araddr[2]),
+        .I5(hog_global_sha_i[9]),
+        .O(\rd_data_s[9]_i_3_n_0 ));
+  (* SOFT_HLUTNM = "soft_lutpair0" *) 
+  LUT5 #(
+    .INIT(32'h00004F00)) 
+    s_axi_arready_s_i_1
+       (.I0(s_axi_arready_s_reg_0),
+        .I1(s_axi_rready),
+        .I2(rd_addr_latched),
+        .I3(s_axi_aresetn),
+        .I4(s_axi_arvalid),
+        .O(s_axi_arready_s_i_1_n_0));
+  FDRE #(
+    .INIT(1'b0)) 
+    s_axi_arready_s_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(s_axi_arready_s_i_1_n_0),
+        .Q(s_axi_arready_s_reg_0),
+        .R(1'b0));
+  (* SOFT_HLUTNM = "soft_lutpair1" *) 
+  LUT4 #(
+    .INIT(16'h88F8)) 
+    s_axi_rvalid_s_i_1
+       (.I0(s_axi_arvalid),
+        .I1(s_axi_arready_s_reg_0),
+        .I2(s_axi_rvalid),
+        .I3(s_axi_rready),
+        .O(s_axi_rvalid_s_i_1_n_0));
+  FDRE #(
+    .INIT(1'b0)) 
+    s_axi_rvalid_s_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(s_axi_rvalid_s_i_1_n_0),
+        .Q(s_axi_rvalid),
+        .R(SR));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_wr_channel_if" *) 
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if
+   (s_axi_wready,
+    s_axi_awready,
+    s_axi_bvalid,
+    SR,
+    s_axi_aclk,
+    s_axi_wvalid,
+    s_axi_bready,
+    s_axi_awvalid);
+  output s_axi_wready;
+  output s_axi_awready;
+  output s_axi_bvalid;
+  input [0:0]SR;
+  input s_axi_aclk;
+  input s_axi_wvalid;
+  input s_axi_bready;
+  input s_axi_awvalid;
+
+  wire [0:0]SR;
+  wire aw_en_i_1_n_0;
+  wire aw_en_reg_n_0;
+  wire s_axi_aclk;
+  wire s_axi_awready;
+  wire s_axi_awready_s0__0;
+  wire s_axi_awvalid;
+  wire s_axi_bready;
+  wire s_axi_bvalid;
+  wire s_axi_bvalid_s_i_1_n_0;
+  wire s_axi_wready;
+  wire s_axi_wready_s0;
+  wire s_axi_wvalid;
+
+  LUT5 #(
+    .INIT(32'h7F2A2A2A)) 
+    aw_en_i_1
+       (.I0(aw_en_reg_n_0),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_bready),
+        .I4(s_axi_bvalid),
+        .O(aw_en_i_1_n_0));
+  FDSE #(
+    .INIT(1'b0)) 
+    aw_en_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(aw_en_i_1_n_0),
+        .Q(aw_en_reg_n_0),
+        .S(SR));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT3 #(
+    .INIT(8'h80)) 
+    s_axi_awready_s0
+       (.I0(s_axi_awvalid),
+        .I1(s_axi_wvalid),
+        .I2(aw_en_reg_n_0),
+        .O(s_axi_awready_s0__0));
+  FDRE #(
+    .INIT(1'b0)) 
+    s_axi_awready_s_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(s_axi_awready_s0__0),
+        .Q(s_axi_awready),
+        .R(SR));
+  LUT4 #(
+    .INIT(16'h8F88)) 
+    s_axi_bvalid_s_i_1
+       (.I0(s_axi_wready),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_bready),
+        .I3(s_axi_bvalid),
+        .O(s_axi_bvalid_s_i_1_n_0));
+  FDRE #(
+    .INIT(1'b0)) 
+    s_axi_bvalid_s_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(s_axi_bvalid_s_i_1_n_0),
+        .Q(s_axi_bvalid),
+        .R(SR));
+  (* SOFT_HLUTNM = "soft_lutpair2" *) 
+  LUT4 #(
+    .INIT(16'h0080)) 
+    s_axi_wready_s_i_1
+       (.I0(aw_en_reg_n_0),
+        .I1(s_axi_wvalid),
+        .I2(s_axi_awvalid),
+        .I3(s_axi_wready),
+        .O(s_axi_wready_s0));
+  FDRE #(
+    .INIT(1'b0)) 
+    s_axi_wready_s_reg
+       (.C(s_axi_aclk),
+        .CE(1'b1),
+        .D(s_axi_wready_s0),
+        .Q(s_axi_wready),
+        .R(SR));
+endmodule
+
+(* ORIG_REF_NAME = "hog_build_info_regs" *) 
+module mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs
+   (SR,
+    s_axi_rdata,
+    s_axi_aresetn,
+    E,
+    D,
+    s_axi_aclk);
+  output [0:0]SR;
+  output [31:0]s_axi_rdata;
+  input s_axi_aresetn;
+  input [0:0]E;
+  input [31:0]D;
+  input s_axi_aclk;
+
+  wire [31:0]D;
+  wire [0:0]E;
+  wire [0:0]SR;
+  wire s_axi_aclk;
+  wire s_axi_aresetn;
+  wire [31:0]s_axi_rdata;
+
+  FDRE \rd_data_s_reg[0] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[0]),
+        .Q(s_axi_rdata[0]),
+        .R(SR));
+  FDRE \rd_data_s_reg[10] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[10]),
+        .Q(s_axi_rdata[10]),
+        .R(SR));
+  FDRE \rd_data_s_reg[11] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[11]),
+        .Q(s_axi_rdata[11]),
+        .R(SR));
+  FDRE \rd_data_s_reg[12] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[12]),
+        .Q(s_axi_rdata[12]),
+        .R(SR));
+  FDRE \rd_data_s_reg[13] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[13]),
+        .Q(s_axi_rdata[13]),
+        .R(SR));
+  FDRE \rd_data_s_reg[14] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[14]),
+        .Q(s_axi_rdata[14]),
+        .R(SR));
+  FDRE \rd_data_s_reg[15] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[15]),
+        .Q(s_axi_rdata[15]),
+        .R(SR));
+  FDRE \rd_data_s_reg[16] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[16]),
+        .Q(s_axi_rdata[16]),
+        .R(SR));
+  FDRE \rd_data_s_reg[17] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[17]),
+        .Q(s_axi_rdata[17]),
+        .R(SR));
+  FDRE \rd_data_s_reg[18] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[18]),
+        .Q(s_axi_rdata[18]),
+        .R(SR));
+  FDRE \rd_data_s_reg[19] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[19]),
+        .Q(s_axi_rdata[19]),
+        .R(SR));
+  FDRE \rd_data_s_reg[1] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[1]),
+        .Q(s_axi_rdata[1]),
+        .R(SR));
+  FDRE \rd_data_s_reg[20] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[20]),
+        .Q(s_axi_rdata[20]),
+        .R(SR));
+  FDRE \rd_data_s_reg[21] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[21]),
+        .Q(s_axi_rdata[21]),
+        .R(SR));
+  FDRE \rd_data_s_reg[22] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[22]),
+        .Q(s_axi_rdata[22]),
+        .R(SR));
+  FDRE \rd_data_s_reg[23] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[23]),
+        .Q(s_axi_rdata[23]),
+        .R(SR));
+  FDRE \rd_data_s_reg[24] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[24]),
+        .Q(s_axi_rdata[24]),
+        .R(SR));
+  FDRE \rd_data_s_reg[25] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[25]),
+        .Q(s_axi_rdata[25]),
+        .R(SR));
+  FDRE \rd_data_s_reg[26] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[26]),
+        .Q(s_axi_rdata[26]),
+        .R(SR));
+  FDRE \rd_data_s_reg[27] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[27]),
+        .Q(s_axi_rdata[27]),
+        .R(SR));
+  FDRE \rd_data_s_reg[28] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[28]),
+        .Q(s_axi_rdata[28]),
+        .R(SR));
+  FDRE \rd_data_s_reg[29] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[29]),
+        .Q(s_axi_rdata[29]),
+        .R(SR));
+  FDRE \rd_data_s_reg[2] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[2]),
+        .Q(s_axi_rdata[2]),
+        .R(SR));
+  FDRE \rd_data_s_reg[30] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[30]),
+        .Q(s_axi_rdata[30]),
+        .R(SR));
+  FDRE \rd_data_s_reg[31] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[31]),
+        .Q(s_axi_rdata[31]),
+        .R(SR));
+  FDRE \rd_data_s_reg[3] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[3]),
+        .Q(s_axi_rdata[3]),
+        .R(SR));
+  FDRE \rd_data_s_reg[4] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[4]),
+        .Q(s_axi_rdata[4]),
+        .R(SR));
+  FDRE \rd_data_s_reg[5] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[5]),
+        .Q(s_axi_rdata[5]),
+        .R(SR));
+  FDRE \rd_data_s_reg[6] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[6]),
+        .Q(s_axi_rdata[6]),
+        .R(SR));
+  FDRE \rd_data_s_reg[7] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[7]),
+        .Q(s_axi_rdata[7]),
+        .R(SR));
+  FDRE \rd_data_s_reg[8] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[8]),
+        .Q(s_axi_rdata[8]),
+        .R(SR));
+  FDRE \rd_data_s_reg[9] 
+       (.C(s_axi_aclk),
+        .CE(E),
+        .D(D[9]),
+        .Q(s_axi_rdata[9]),
+        .R(SR));
+  LUT1 #(
+    .INIT(2'h1)) 
+    s_axi_awready_s_i_1
+       (.I0(s_axi_aresetn),
+        .O(SR));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..89c24fa585fa67479bec00d5ad142bc84f21125d
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
@@ -0,0 +1,2305 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+-- Date        : Sun Mar 23 23:27:32 2025
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim
+--               /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
+-- Design      : mb_design_1_axi4lite_hog_build_i_0_0
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if is
+  port (
+    s_axi_arready_s_reg_0 : out STD_LOGIC;
+    s_axi_rvalid : out STD_LOGIC;
+    D : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    E : out STD_LOGIC_VECTOR ( 0 to 0 );
+    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if : entity is "axi4lite_rd_channel_if";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if is
+  signal addr_s : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal \addr_s[0]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[1]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[2]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[3]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[4]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[5]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[6]_i_1_n_0\ : STD_LOGIC;
+  signal \addr_s[7]_i_1_n_0\ : STD_LOGIC;
+  signal rd_addr_latched : STD_LOGIC;
+  signal rd_addr_latched_i_1_n_0 : STD_LOGIC;
+  signal \rd_data_s[0]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[0]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[10]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[10]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[11]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[11]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[12]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[12]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[13]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[13]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[14]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[14]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[15]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[15]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[16]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[16]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[17]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[17]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[18]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[18]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[19]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[19]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[1]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[1]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[20]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[20]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[21]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[21]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[22]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[22]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[23]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[23]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[24]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[24]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[25]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[25]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[26]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[26]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[27]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[27]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[28]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[28]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[29]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[29]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[2]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[2]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[30]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[30]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[31]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[31]_i_4_n_0\ : STD_LOGIC;
+  signal \rd_data_s[31]_i_5_n_0\ : STD_LOGIC;
+  signal \rd_data_s[31]_i_6_n_0\ : STD_LOGIC;
+  signal \rd_data_s[31]_i_7_n_0\ : STD_LOGIC;
+  signal \rd_data_s[3]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[3]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[4]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[4]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[5]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[5]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[6]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[6]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[7]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[7]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[8]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[8]_i_3_n_0\ : STD_LOGIC;
+  signal \rd_data_s[9]_i_2_n_0\ : STD_LOGIC;
+  signal \rd_data_s[9]_i_3_n_0\ : STD_LOGIC;
+  signal s_axi_arready_s_i_1_n_0 : STD_LOGIC;
+  signal \^s_axi_arready_s_reg_0\ : STD_LOGIC;
+  signal \^s_axi_rvalid\ : STD_LOGIC;
+  signal s_axi_rvalid_s_i_1_n_0 : STD_LOGIC;
+  attribute SOFT_HLUTNM : string;
+  attribute SOFT_HLUTNM of rd_addr_latched_i_1 : label is "soft_lutpair1";
+  attribute SOFT_HLUTNM of \rd_data_s[31]_i_1\ : label is "soft_lutpair0";
+  attribute SOFT_HLUTNM of s_axi_arready_s_i_1 : label is "soft_lutpair0";
+  attribute SOFT_HLUTNM of s_axi_rvalid_s_i_1 : label is "soft_lutpair1";
+begin
+  s_axi_arready_s_reg_0 <= \^s_axi_arready_s_reg_0\;
+  s_axi_rvalid <= \^s_axi_rvalid\;
+\addr_s[0]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(0),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(0),
+      O => \addr_s[0]_i_1_n_0\
+    );
+\addr_s[1]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(1),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(1),
+      O => \addr_s[1]_i_1_n_0\
+    );
+\addr_s[2]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"BF80"
+    )
+        port map (
+      I0 => s_axi_araddr(2),
+      I1 => s_axi_arvalid,
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => addr_s(2),
+      O => \addr_s[2]_i_1_n_0\
+    );
+\addr_s[3]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(3),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(3),
+      O => \addr_s[3]_i_1_n_0\
+    );
+\addr_s[4]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(4),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(4),
+      O => \addr_s[4]_i_1_n_0\
+    );
+\addr_s[5]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(5),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(5),
+      O => \addr_s[5]_i_1_n_0\
+    );
+\addr_s[6]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(6),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(6),
+      O => \addr_s[6]_i_1_n_0\
+    );
+\addr_s[7]_i_1\: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EA2A"
+    )
+        port map (
+      I0 => addr_s(7),
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_arvalid,
+      I3 => s_axi_araddr(7),
+      O => \addr_s[7]_i_1_n_0\
+    );
+\addr_s_reg[0]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[0]_i_1_n_0\,
+      Q => addr_s(0),
+      R => SR(0)
+    );
+\addr_s_reg[1]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[1]_i_1_n_0\,
+      Q => addr_s(1),
+      R => SR(0)
+    );
+\addr_s_reg[2]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[2]_i_1_n_0\,
+      Q => addr_s(2),
+      R => SR(0)
+    );
+\addr_s_reg[3]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[3]_i_1_n_0\,
+      Q => addr_s(3),
+      R => SR(0)
+    );
+\addr_s_reg[4]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[4]_i_1_n_0\,
+      Q => addr_s(4),
+      R => SR(0)
+    );
+\addr_s_reg[5]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[5]_i_1_n_0\,
+      Q => addr_s(5),
+      R => SR(0)
+    );
+\addr_s_reg[6]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[6]_i_1_n_0\,
+      Q => addr_s(6),
+      R => SR(0)
+    );
+\addr_s_reg[7]\: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \addr_s[7]_i_1_n_0\,
+      Q => addr_s(7),
+      R => SR(0)
+    );
+rd_addr_latched_i_1: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"EFAA"
+    )
+        port map (
+      I0 => s_axi_arvalid,
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => s_axi_rready,
+      I3 => rd_addr_latched,
+      O => rd_addr_latched_i_1_n_0
+    );
+rd_addr_latched_reg: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => rd_addr_latched_i_1_n_0,
+      Q => rd_addr_latched,
+      R => SR(0)
+    );
+\rd_data_s[0]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[0]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[0]_i_3_n_0\,
+      O => D(0)
+    );
+\rd_data_s[0]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(0),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(0),
+      O => \rd_data_s[0]_i_2_n_0\
+    );
+\rd_data_s[0]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(0),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(0),
+      O => \rd_data_s[0]_i_3_n_0\
+    );
+\rd_data_s[10]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[10]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[10]_i_3_n_0\,
+      O => D(10)
+    );
+\rd_data_s[10]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(10),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(10),
+      O => \rd_data_s[10]_i_2_n_0\
+    );
+\rd_data_s[10]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(10),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(10),
+      O => \rd_data_s[10]_i_3_n_0\
+    );
+\rd_data_s[11]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[11]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[11]_i_3_n_0\,
+      O => D(11)
+    );
+\rd_data_s[11]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(11),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(11),
+      O => \rd_data_s[11]_i_2_n_0\
+    );
+\rd_data_s[11]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(11),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(11),
+      O => \rd_data_s[11]_i_3_n_0\
+    );
+\rd_data_s[12]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[12]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[12]_i_3_n_0\,
+      O => D(12)
+    );
+\rd_data_s[12]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(12),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(12),
+      O => \rd_data_s[12]_i_2_n_0\
+    );
+\rd_data_s[12]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(12),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(12),
+      O => \rd_data_s[12]_i_3_n_0\
+    );
+\rd_data_s[13]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[13]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[13]_i_3_n_0\,
+      O => D(13)
+    );
+\rd_data_s[13]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(13),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(13),
+      O => \rd_data_s[13]_i_2_n_0\
+    );
+\rd_data_s[13]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(13),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(13),
+      O => \rd_data_s[13]_i_3_n_0\
+    );
+\rd_data_s[14]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[14]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[14]_i_3_n_0\,
+      O => D(14)
+    );
+\rd_data_s[14]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(14),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(14),
+      O => \rd_data_s[14]_i_2_n_0\
+    );
+\rd_data_s[14]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(14),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(14),
+      O => \rd_data_s[14]_i_3_n_0\
+    );
+\rd_data_s[15]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[15]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[15]_i_3_n_0\,
+      O => D(15)
+    );
+\rd_data_s[15]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(15),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(15),
+      O => \rd_data_s[15]_i_2_n_0\
+    );
+\rd_data_s[15]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(15),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(15),
+      O => \rd_data_s[15]_i_3_n_0\
+    );
+\rd_data_s[16]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[16]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[16]_i_3_n_0\,
+      O => D(16)
+    );
+\rd_data_s[16]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(16),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(16),
+      O => \rd_data_s[16]_i_2_n_0\
+    );
+\rd_data_s[16]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(16),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(16),
+      O => \rd_data_s[16]_i_3_n_0\
+    );
+\rd_data_s[17]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[17]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[17]_i_3_n_0\,
+      O => D(17)
+    );
+\rd_data_s[17]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(17),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(17),
+      O => \rd_data_s[17]_i_2_n_0\
+    );
+\rd_data_s[17]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(17),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(17),
+      O => \rd_data_s[17]_i_3_n_0\
+    );
+\rd_data_s[18]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[18]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[18]_i_3_n_0\,
+      O => D(18)
+    );
+\rd_data_s[18]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(18),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(18),
+      O => \rd_data_s[18]_i_2_n_0\
+    );
+\rd_data_s[18]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(18),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(18),
+      O => \rd_data_s[18]_i_3_n_0\
+    );
+\rd_data_s[19]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[19]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[19]_i_3_n_0\,
+      O => D(19)
+    );
+\rd_data_s[19]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(19),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(19),
+      O => \rd_data_s[19]_i_2_n_0\
+    );
+\rd_data_s[19]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(19),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(19),
+      O => \rd_data_s[19]_i_3_n_0\
+    );
+\rd_data_s[1]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[1]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[1]_i_3_n_0\,
+      O => D(1)
+    );
+\rd_data_s[1]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(1),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(1),
+      O => \rd_data_s[1]_i_2_n_0\
+    );
+\rd_data_s[1]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(1),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(1),
+      O => \rd_data_s[1]_i_3_n_0\
+    );
+\rd_data_s[20]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[20]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[20]_i_3_n_0\,
+      O => D(20)
+    );
+\rd_data_s[20]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(20),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(20),
+      O => \rd_data_s[20]_i_2_n_0\
+    );
+\rd_data_s[20]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(20),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(20),
+      O => \rd_data_s[20]_i_3_n_0\
+    );
+\rd_data_s[21]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[21]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[21]_i_3_n_0\,
+      O => D(21)
+    );
+\rd_data_s[21]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(21),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(21),
+      O => \rd_data_s[21]_i_2_n_0\
+    );
+\rd_data_s[21]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(21),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(21),
+      O => \rd_data_s[21]_i_3_n_0\
+    );
+\rd_data_s[22]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[22]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[22]_i_3_n_0\,
+      O => D(22)
+    );
+\rd_data_s[22]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(22),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(22),
+      O => \rd_data_s[22]_i_2_n_0\
+    );
+\rd_data_s[22]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(22),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(22),
+      O => \rd_data_s[22]_i_3_n_0\
+    );
+\rd_data_s[23]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[23]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[23]_i_3_n_0\,
+      O => D(23)
+    );
+\rd_data_s[23]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(23),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(23),
+      O => \rd_data_s[23]_i_2_n_0\
+    );
+\rd_data_s[23]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(23),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(23),
+      O => \rd_data_s[23]_i_3_n_0\
+    );
+\rd_data_s[24]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[24]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[24]_i_3_n_0\,
+      O => D(24)
+    );
+\rd_data_s[24]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(24),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(24),
+      O => \rd_data_s[24]_i_2_n_0\
+    );
+\rd_data_s[24]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(24),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(24),
+      O => \rd_data_s[24]_i_3_n_0\
+    );
+\rd_data_s[25]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[25]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[25]_i_3_n_0\,
+      O => D(25)
+    );
+\rd_data_s[25]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(25),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(25),
+      O => \rd_data_s[25]_i_2_n_0\
+    );
+\rd_data_s[25]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(25),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(25),
+      O => \rd_data_s[25]_i_3_n_0\
+    );
+\rd_data_s[26]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[26]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[26]_i_3_n_0\,
+      O => D(26)
+    );
+\rd_data_s[26]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(26),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(26),
+      O => \rd_data_s[26]_i_2_n_0\
+    );
+\rd_data_s[26]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(26),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(26),
+      O => \rd_data_s[26]_i_3_n_0\
+    );
+\rd_data_s[27]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[27]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[27]_i_3_n_0\,
+      O => D(27)
+    );
+\rd_data_s[27]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(27),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(27),
+      O => \rd_data_s[27]_i_2_n_0\
+    );
+\rd_data_s[27]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(27),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(27),
+      O => \rd_data_s[27]_i_3_n_0\
+    );
+\rd_data_s[28]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[28]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[28]_i_3_n_0\,
+      O => D(28)
+    );
+\rd_data_s[28]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(28),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(28),
+      O => \rd_data_s[28]_i_2_n_0\
+    );
+\rd_data_s[28]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(28),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(28),
+      O => \rd_data_s[28]_i_3_n_0\
+    );
+\rd_data_s[29]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[29]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[29]_i_3_n_0\,
+      O => D(29)
+    );
+\rd_data_s[29]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(29),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(29),
+      O => \rd_data_s[29]_i_2_n_0\
+    );
+\rd_data_s[29]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(29),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(29),
+      O => \rd_data_s[29]_i_3_n_0\
+    );
+\rd_data_s[2]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[2]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[2]_i_3_n_0\,
+      O => D(2)
+    );
+\rd_data_s[2]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(2),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(2),
+      O => \rd_data_s[2]_i_2_n_0\
+    );
+\rd_data_s[2]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(2),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(2),
+      O => \rd_data_s[2]_i_3_n_0\
+    );
+\rd_data_s[30]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[30]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[30]_i_3_n_0\,
+      O => D(30)
+    );
+\rd_data_s[30]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(30),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(30),
+      O => \rd_data_s[30]_i_2_n_0\
+    );
+\rd_data_s[30]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(30),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(30),
+      O => \rd_data_s[30]_i_3_n_0\
+    );
+\rd_data_s[31]_i_1\: unisim.vcomponents.LUT2
+    generic map(
+      INIT => X"8"
+    )
+        port map (
+      I0 => s_axi_arvalid,
+      I1 => \^s_axi_arready_s_reg_0\,
+      O => E(0)
+    );
+\rd_data_s[31]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"000000E200000000"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_3_n_0\,
+      I1 => \addr_s[3]_i_1_n_0\,
+      I2 => \rd_data_s[31]_i_4_n_0\,
+      I3 => \rd_data_s[31]_i_5_n_0\,
+      I4 => \rd_data_s[31]_i_6_n_0\,
+      I5 => \rd_data_s[31]_i_7_n_0\,
+      O => D(31)
+    );
+\rd_data_s[31]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"FEEEAEEE0222A222"
+    )
+        port map (
+      I0 => hog_global_date_i(31),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(31),
+      O => \rd_data_s[31]_i_3_n_0\
+    );
+\rd_data_s[31]_i_4\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"FEEEAEEE0222A222"
+    )
+        port map (
+      I0 => hog_global_ver_i(31),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(31),
+      O => \rd_data_s[31]_i_4_n_0\
+    );
+\rd_data_s[31]_i_5\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"FAFFFFFFFACCCCCC"
+    )
+        port map (
+      I0 => s_axi_araddr(6),
+      I1 => addr_s(6),
+      I2 => s_axi_araddr(5),
+      I3 => s_axi_arvalid,
+      I4 => \^s_axi_arready_s_reg_0\,
+      I5 => addr_s(5),
+      O => \rd_data_s[31]_i_5_n_0\
+    );
+\rd_data_s[31]_i_6\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"FAFFFFFFFACCCCCC"
+    )
+        port map (
+      I0 => s_axi_araddr(7),
+      I1 => addr_s(7),
+      I2 => s_axi_araddr(0),
+      I3 => s_axi_arvalid,
+      I4 => \^s_axi_arready_s_reg_0\,
+      I5 => addr_s(0),
+      O => \rd_data_s[31]_i_6_n_0\
+    );
+\rd_data_s[31]_i_7\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0500000005333333"
+    )
+        port map (
+      I0 => s_axi_araddr(4),
+      I1 => addr_s(4),
+      I2 => s_axi_araddr(1),
+      I3 => s_axi_arvalid,
+      I4 => \^s_axi_arready_s_reg_0\,
+      I5 => addr_s(1),
+      O => \rd_data_s[31]_i_7_n_0\
+    );
+\rd_data_s[3]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[3]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[3]_i_3_n_0\,
+      O => D(3)
+    );
+\rd_data_s[3]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(3),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(3),
+      O => \rd_data_s[3]_i_2_n_0\
+    );
+\rd_data_s[3]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(3),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(3),
+      O => \rd_data_s[3]_i_3_n_0\
+    );
+\rd_data_s[4]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[4]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[4]_i_3_n_0\,
+      O => D(4)
+    );
+\rd_data_s[4]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(4),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(4),
+      O => \rd_data_s[4]_i_2_n_0\
+    );
+\rd_data_s[4]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(4),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(4),
+      O => \rd_data_s[4]_i_3_n_0\
+    );
+\rd_data_s[5]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[5]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[5]_i_3_n_0\,
+      O => D(5)
+    );
+\rd_data_s[5]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(5),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(5),
+      O => \rd_data_s[5]_i_2_n_0\
+    );
+\rd_data_s[5]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(5),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(5),
+      O => \rd_data_s[5]_i_3_n_0\
+    );
+\rd_data_s[6]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[6]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[6]_i_3_n_0\,
+      O => D(6)
+    );
+\rd_data_s[6]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(6),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(6),
+      O => \rd_data_s[6]_i_2_n_0\
+    );
+\rd_data_s[6]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(6),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(6),
+      O => \rd_data_s[6]_i_3_n_0\
+    );
+\rd_data_s[7]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[7]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[7]_i_3_n_0\,
+      O => D(7)
+    );
+\rd_data_s[7]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(7),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(7),
+      O => \rd_data_s[7]_i_2_n_0\
+    );
+\rd_data_s[7]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(7),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(7),
+      O => \rd_data_s[7]_i_3_n_0\
+    );
+\rd_data_s[8]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[8]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[8]_i_3_n_0\,
+      O => D(8)
+    );
+\rd_data_s[8]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(8),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(8),
+      O => \rd_data_s[8]_i_2_n_0\
+    );
+\rd_data_s[8]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(8),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(8),
+      O => \rd_data_s[8]_i_3_n_0\
+    );
+\rd_data_s[9]_i_1\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"0000001010100010"
+    )
+        port map (
+      I0 => \rd_data_s[31]_i_5_n_0\,
+      I1 => \rd_data_s[31]_i_6_n_0\,
+      I2 => \rd_data_s[31]_i_7_n_0\,
+      I3 => \rd_data_s[9]_i_2_n_0\,
+      I4 => \addr_s[3]_i_1_n_0\,
+      I5 => \rd_data_s[9]_i_3_n_0\,
+      O => D(9)
+    );
+\rd_data_s[9]_i_2\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_date_i(9),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_time_i(9),
+      O => \rd_data_s[9]_i_2_n_0\
+    );
+\rd_data_s[9]_i_3\: unisim.vcomponents.LUT6
+    generic map(
+      INIT => X"01115111FDDD5DDD"
+    )
+        port map (
+      I0 => hog_global_ver_i(9),
+      I1 => addr_s(2),
+      I2 => \^s_axi_arready_s_reg_0\,
+      I3 => s_axi_arvalid,
+      I4 => s_axi_araddr(2),
+      I5 => hog_global_sha_i(9),
+      O => \rd_data_s[9]_i_3_n_0\
+    );
+s_axi_arready_s_i_1: unisim.vcomponents.LUT5
+    generic map(
+      INIT => X"00004F00"
+    )
+        port map (
+      I0 => \^s_axi_arready_s_reg_0\,
+      I1 => s_axi_rready,
+      I2 => rd_addr_latched,
+      I3 => s_axi_aresetn,
+      I4 => s_axi_arvalid,
+      O => s_axi_arready_s_i_1_n_0
+    );
+s_axi_arready_s_reg: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => s_axi_arready_s_i_1_n_0,
+      Q => \^s_axi_arready_s_reg_0\,
+      R => '0'
+    );
+s_axi_rvalid_s_i_1: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"88F8"
+    )
+        port map (
+      I0 => s_axi_arvalid,
+      I1 => \^s_axi_arready_s_reg_0\,
+      I2 => \^s_axi_rvalid\,
+      I3 => s_axi_rready,
+      O => s_axi_rvalid_s_i_1_n_0
+    );
+s_axi_rvalid_s_reg: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => s_axi_rvalid_s_i_1_n_0,
+      Q => \^s_axi_rvalid\,
+      R => SR(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if is
+  port (
+    s_axi_wready : out STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_bvalid : out STD_LOGIC;
+    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_awvalid : in STD_LOGIC
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if : entity is "axi4lite_wr_channel_if";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if is
+  signal aw_en_i_1_n_0 : STD_LOGIC;
+  signal aw_en_reg_n_0 : STD_LOGIC;
+  signal \s_axi_awready_s0__0\ : STD_LOGIC;
+  signal \^s_axi_bvalid\ : STD_LOGIC;
+  signal s_axi_bvalid_s_i_1_n_0 : STD_LOGIC;
+  signal \^s_axi_wready\ : STD_LOGIC;
+  signal s_axi_wready_s0 : STD_LOGIC;
+  attribute SOFT_HLUTNM : string;
+  attribute SOFT_HLUTNM of s_axi_awready_s0 : label is "soft_lutpair2";
+  attribute SOFT_HLUTNM of s_axi_wready_s_i_1 : label is "soft_lutpair2";
+begin
+  s_axi_bvalid <= \^s_axi_bvalid\;
+  s_axi_wready <= \^s_axi_wready\;
+aw_en_i_1: unisim.vcomponents.LUT5
+    generic map(
+      INIT => X"7F2A2A2A"
+    )
+        port map (
+      I0 => aw_en_reg_n_0,
+      I1 => s_axi_wvalid,
+      I2 => s_axi_awvalid,
+      I3 => s_axi_bready,
+      I4 => \^s_axi_bvalid\,
+      O => aw_en_i_1_n_0
+    );
+aw_en_reg: unisim.vcomponents.FDSE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => aw_en_i_1_n_0,
+      Q => aw_en_reg_n_0,
+      S => SR(0)
+    );
+s_axi_awready_s0: unisim.vcomponents.LUT3
+    generic map(
+      INIT => X"80"
+    )
+        port map (
+      I0 => s_axi_awvalid,
+      I1 => s_axi_wvalid,
+      I2 => aw_en_reg_n_0,
+      O => \s_axi_awready_s0__0\
+    );
+s_axi_awready_s_reg: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => \s_axi_awready_s0__0\,
+      Q => s_axi_awready,
+      R => SR(0)
+    );
+s_axi_bvalid_s_i_1: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"8F88"
+    )
+        port map (
+      I0 => \^s_axi_wready\,
+      I1 => s_axi_wvalid,
+      I2 => s_axi_bready,
+      I3 => \^s_axi_bvalid\,
+      O => s_axi_bvalid_s_i_1_n_0
+    );
+s_axi_bvalid_s_reg: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => s_axi_bvalid_s_i_1_n_0,
+      Q => \^s_axi_bvalid\,
+      R => SR(0)
+    );
+s_axi_wready_s_i_1: unisim.vcomponents.LUT4
+    generic map(
+      INIT => X"0080"
+    )
+        port map (
+      I0 => aw_en_reg_n_0,
+      I1 => s_axi_wvalid,
+      I2 => s_axi_awvalid,
+      I3 => \^s_axi_wready\,
+      O => s_axi_wready_s0
+    );
+s_axi_wready_s_reg: unisim.vcomponents.FDRE
+    generic map(
+      INIT => '0'
+    )
+        port map (
+      C => s_axi_aclk,
+      CE => '1',
+      D => s_axi_wready_s0,
+      Q => \^s_axi_wready\,
+      R => SR(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs is
+  port (
+    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_aresetn : in STD_LOGIC;
+    E : in STD_LOGIC_VECTOR ( 0 to 0 );
+    D : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_aclk : in STD_LOGIC
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs : entity is "hog_build_info_regs";
+end mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs is
+  signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  SR(0) <= \^sr\(0);
+\rd_data_s_reg[0]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(0),
+      Q => s_axi_rdata(0),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[10]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(10),
+      Q => s_axi_rdata(10),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[11]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(11),
+      Q => s_axi_rdata(11),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[12]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(12),
+      Q => s_axi_rdata(12),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[13]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(13),
+      Q => s_axi_rdata(13),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[14]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(14),
+      Q => s_axi_rdata(14),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[15]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(15),
+      Q => s_axi_rdata(15),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[16]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(16),
+      Q => s_axi_rdata(16),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[17]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(17),
+      Q => s_axi_rdata(17),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[18]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(18),
+      Q => s_axi_rdata(18),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[19]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(19),
+      Q => s_axi_rdata(19),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[1]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(1),
+      Q => s_axi_rdata(1),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[20]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(20),
+      Q => s_axi_rdata(20),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[21]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(21),
+      Q => s_axi_rdata(21),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[22]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(22),
+      Q => s_axi_rdata(22),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[23]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(23),
+      Q => s_axi_rdata(23),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[24]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(24),
+      Q => s_axi_rdata(24),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[25]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(25),
+      Q => s_axi_rdata(25),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[26]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(26),
+      Q => s_axi_rdata(26),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[27]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(27),
+      Q => s_axi_rdata(27),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[28]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(28),
+      Q => s_axi_rdata(28),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[29]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(29),
+      Q => s_axi_rdata(29),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[2]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(2),
+      Q => s_axi_rdata(2),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[30]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(30),
+      Q => s_axi_rdata(30),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[31]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(31),
+      Q => s_axi_rdata(31),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[3]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(3),
+      Q => s_axi_rdata(3),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[4]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(4),
+      Q => s_axi_rdata(4),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[5]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(5),
+      Q => s_axi_rdata(5),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[6]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(6),
+      Q => s_axi_rdata(6),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[7]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(7),
+      Q => s_axi_rdata(7),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[8]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(8),
+      Q => s_axi_rdata(8),
+      R => \^sr\(0)
+    );
+\rd_data_s_reg[9]\: unisim.vcomponents.FDRE
+     port map (
+      C => s_axi_aclk,
+      CE => E(0),
+      D => D(9),
+      Q => s_axi_rdata(9),
+      R => \^sr\(0)
+    );
+s_axi_awready_s_i_1: unisim.vcomponents.LUT1
+    generic map(
+      INIT => X"1"
+    )
+        port map (
+      I0 => s_axi_aresetn,
+      O => \^sr\(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if is
+  port (
+    s_axi_wready : out STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_arready_s_reg : out STD_LOGIC;
+    s_axi_rvalid : out STD_LOGIC;
+    D : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    E : out STD_LOGIC_VECTOR ( 0 to 0 );
+    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_awvalid : in STD_LOGIC
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if : entity is "axi4lite_if";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if is
+begin
+axi4lite_rd_channel_if_i: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if
+     port map (
+      D(31 downto 0) => D(31 downto 0),
+      E(0) => E(0),
+      SR(0) => SR(0),
+      hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
+      hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
+      hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
+      hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
+      s_axi_aclk => s_axi_aclk,
+      s_axi_araddr(7 downto 0) => s_axi_araddr(7 downto 0),
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_arready_s_reg_0 => s_axi_arready_s_reg,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_rready => s_axi_rready,
+      s_axi_rvalid => s_axi_rvalid
+    );
+axi4lite_wr_channel_if_i: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if
+     port map (
+      SR(0) => SR(0),
+      s_axi_aclk => s_axi_aclk,
+      s_axi_awready => s_axi_awready,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_wvalid => s_axi_wvalid
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info is
+  port (
+    s_axi_wready : out STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arready_s_reg : out STD_LOGIC;
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_bready : in STD_LOGIC
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info : entity is "axi4lite_hog_build_info";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info is
+  signal p_0_in : STD_LOGIC;
+  signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal rd_valid_s : STD_LOGIC;
+begin
+axi4lite_if_inst: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if
+     port map (
+      D(31 downto 0) => p_1_in(31 downto 0),
+      E(0) => rd_valid_s,
+      SR(0) => p_0_in,
+      hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
+      hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
+      hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
+      hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
+      s_axi_aclk => s_axi_aclk,
+      s_axi_araddr(7 downto 0) => s_axi_araddr(7 downto 0),
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_arready_s_reg => s_axi_arready_s_reg,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_rready => s_axi_rready,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_wvalid => s_axi_wvalid
+    );
+hog_build_info_regs_inst: entity work.mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs
+     port map (
+      D(31 downto 0) => p_1_in(31 downto 0),
+      E(0) => rd_valid_s,
+      SR(0) => p_0_in,
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of mb_design_1_axi4lite_hog_build_i_0_0 : entity is true;
+  attribute CHECK_LICENSE_TYPE : string;
+  attribute CHECK_LICENSE_TYPE of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}";
+  attribute downgradeipidentifiedwarnings : string;
+  attribute downgradeipidentifiedwarnings of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "yes";
+  attribute ip_definition_source : string;
+  attribute ip_definition_source of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "module_ref";
+  attribute x_core_info : string;
+  attribute x_core_info of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "axi4lite_hog_build_info,Vivado 2024.1.2";
+end mb_design_1_axi4lite_hog_build_i_0_0;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0 is
+  signal \<const0>\ : STD_LOGIC;
+  attribute x_interface_info : string;
+  attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
+  attribute x_interface_parameter : string;
+  attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
+  attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
+  attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
+  attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
+  attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
+  attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
+  attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 s_axi BREADY";
+  attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi BVALID";
+  attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 s_axi RREADY";
+  attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi RVALID";
+  attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 s_axi WREADY";
+  attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi WVALID";
+  attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
+  attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
+  attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 s_axi BRESP";
+  attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 s_axi RDATA";
+  attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 s_axi RRESP";
+  attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 s_axi WDATA";
+  attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
+begin
+  s_axi_bresp(1) <= \<const0>\;
+  s_axi_bresp(0) <= \<const0>\;
+  s_axi_rresp(1) <= \<const0>\;
+  s_axi_rresp(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+     port map (
+      G => \<const0>\
+    );
+U0: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info
+     port map (
+      hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
+      hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
+      hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
+      hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
+      s_axi_aclk => s_axi_aclk,
+      s_axi_araddr(7 downto 0) => s_axi_araddr(7 downto 0),
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_arready_s_reg => s_axi_arready,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
+      s_axi_rready => s_axi_rready,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_wvalid => s_axi_wvalid
+    );
+end STRUCTURE;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
new file mode 100644
index 0000000000000000000000000000000000000000..3916951e61441e9e9ffae3b5c51ef66198f9a56b
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
@@ -0,0 +1,48 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+// Date        : Sun Mar 23 23:27:32 2025
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub
+//               /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
+// Design      : mb_design_1_axi4lite_hog_build_i_0_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi4lite_hog_build_info,Vivado 2024.1.2" *)
+module mb_design_1_axi4lite_hog_build_i_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, hog_global_date_i, hog_global_time_i, 
+  hog_global_ver_i, hog_global_sha_i)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,hog_global_date_i[31:0],hog_global_time_i[31:0],hog_global_ver_i[31:0],hog_global_sha_i[31:0]" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+  input s_axi_aclk /* synthesis syn_isclock = 1 */;
+  input s_axi_aresetn;
+  input [31:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [31:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input [31:0]hog_global_date_i;
+  input [31:0]hog_global_time_i;
+  input [31:0]hog_global_ver_i;
+  input [31:0]hog_global_sha_i;
+endmodule
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..75114786903849a3581426cc5835562866b9bb48
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
@@ -0,0 +1,53 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+-- Date        : Sun Mar 23 23:27:32 2025
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
+-- Design      : mb_design_1_axi4lite_hog_build_i_0_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity mb_design_1_axi4lite_hog_build_i_0_0 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end mb_design_1_axi4lite_hog_build_i_0_0;
+
+architecture stub of mb_design_1_axi4lite_hog_build_i_0_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,hog_global_date_i[31:0],hog_global_time_i[31:0],hog_global_ver_i[31:0],hog_global_sha_i[31:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi4lite_hog_build_info,Vivado 2024.1.2";
+begin
+end;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..94dc9a0ee9c4ed98201806073a9938d9cca9704a
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd
@@ -0,0 +1,172 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axi4lite_hog_build_info:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY mb_design_1_axi4lite_hog_build_i_0_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END mb_design_1_axi4lite_hog_build_i_0_0;
+
+ARCHITECTURE mb_design_1_axi4lite_hog_build_i_0_0_arch OF mb_design_1_axi4lite_hog_build_i_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi4lite_hog_build_info IS
+    GENERIC (
+      C_ADDR_WIDTH : INTEGER
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi4lite_hog_build_info;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" & 
+", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
+BEGIN
+  U0 : axi4lite_hog_build_info
+    GENERIC MAP (
+      C_ADDR_WIDTH => 8
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      hog_global_date_i => hog_global_date_i,
+      hog_global_time_i => hog_global_time_i,
+      hog_global_ver_i => hog_global_ver_i,
+      hog_global_sha_i => hog_global_sha_i
+    );
+END mb_design_1_axi4lite_hog_build_i_0_0_arch;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a89e011711d1290e91f095abc066e2ae9829bced
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd
@@ -0,0 +1,180 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axi4lite_hog_build_info:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY mb_design_1_axi4lite_hog_build_i_0_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END mb_design_1_axi4lite_hog_build_i_0_0;
+
+ARCHITECTURE mb_design_1_axi4lite_hog_build_i_0_0_arch OF mb_design_1_axi4lite_hog_build_i_0_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi4lite_hog_build_info IS
+    GENERIC (
+      C_ADDR_WIDTH : INTEGER
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi4lite_hog_build_info;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "axi4lite_hog_build_info,Vivado 2024.1.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF mb_design_1_axi4lite_hog_build_i_0_0_arch : ARCHITECTURE IS "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axi4lite_hog_build_info,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ADDR_WIDTH=8}";
+  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+  ATTRIBUTE IP_DEFINITION_SOURCE OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "module_ref";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" & 
+", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
+BEGIN
+  U0 : axi4lite_hog_build_info
+    GENERIC MAP (
+      C_ADDR_WIDTH => 8
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      hog_global_date_i => hog_global_date_i,
+      hog_global_time_i => hog_global_time_i,
+      hog_global_ver_i => hog_global_ver_i,
+      hog_global_sha_i => hog_global_sha_i
+    );
+END mb_design_1_axi4lite_hog_build_i_0_0_arch;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
new file mode 100644
index 0000000000000000000000000000000000000000..f4217e021dfa8a881e7b16ef73d3bf306d786f55
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
@@ -0,0 +1,11 @@
+WORKFLOW_OPERATION simulation,dialog;
+
+DEFINE_MEMORY_TYPE blk_mem_gen_0_MEM_DEVICE [0x00008000] 32;
+
+ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 microblaze_0
+   ADDRESS_SPACE blk_mem_gen_0_ADDR_SPACE blk_mem_gen_0_MEM_DEVICE  [0x00000000:0x00007FFF] dlmb_bram_if_cntlr_0
+     BUS_BLOCK
+      blk_mem_gen_0_BUS_BLK [31:0] INPUT = "mb_design_1_blk_mem_gen_0_0.mem";
+     END_BUS_BLOCK;
+   END_ADDRESS_SPACE;
+END_ADDRESS_MAP;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
index c56d0e0aeac54d6ecc36cbf1fe23f95d89f13a5d..ad2fe363fd4f7840fcfca809f1bd76b27866dc82 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
@@ -2,10 +2,62 @@
 <Root MajorVersion="0" MinorVersion="43">
   <CompositeFile CompositeFileTopName="mb_design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
     <Description>Composite Fileset</Description>
-    <Generation Name="SYNTHESIS" State="RESET" Timestamp="1742768614"/>
-    <Generation Name="SIMULATION" State="RESET" Timestamp="1742768614"/>
-    <Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1742768614"/>
-    <Generation Name="HW_HANDOFF" State="RESET" Timestamp="1742768614"/>
-    <FileCollection Name="SOURCES" Type="SOURCES"/>
+    <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1742768813"/>
+    <Generation Name="SIMULATION" State="GENERATED" Timestamp="1742768813"/>
+    <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1742768813"/>
+    <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1742768813"/>
+    <FileCollection Name="SOURCES" Type="SOURCES">
+      <File Name="synth/mb_design_1.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="sim/mb_design_1.vhd" Type="VHDL">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SIMULATION"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="mb_design_1.bmm" Type="BMM">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="SIMULATION"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="mb_design_1_ooc.xdc" Type="XDC">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SYNTHESIS"/>
+        <UsedIn Val="IMPLEMENTATION"/>
+        <UsedIn Val="OUT_OF_CONTEXT"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="hw_handoff/mb_design_1.hwh" Type="HwHandoff">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="mb_design_1.bda">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="synth/mb_design_1.hwdef">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="HW_HANDOFF"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+      <File Name="sim/mb_design_1.protoinst">
+        <Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
+        <Library Name="xil_defaultlib"/>
+        <UsedIn Val="SIMULATION"/>
+        <ProcessingOrder Val="NORMAL"/>
+      </File>
+    </FileCollection>
   </CompositeFile>
 </Root>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1_ooc.xdc b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1_ooc.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..2945923c89564d2071105ccdaa54d6bcc0fc67c4
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1_ooc.xdc
@@ -0,0 +1,11 @@
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name clk_in1 -period 10 [get_ports clk_in1]
+
+################################################################################
\ No newline at end of file
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst
new file mode 100644
index 0000000000000000000000000000000000000000..5b4f6ae7dd564ff9c4d3dae95eb86bd5c2e6eb29
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst
@@ -0,0 +1,749 @@
+{
+	"version": "1.0",
+	"modules": {
+		"mb_design_1": {
+			"proto_instances": {
+				"/axi4lite_hog_build_i_0/s_axi": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "s_axi_aclk"},
+						"ARADDR": { "actual": "s_axi_araddr[31:0]"},
+						"ARESETN": { "actual": "s_axi_aresetn"},
+						"ARREADY": { "actual": "s_axi_arready"},
+						"ARVALID": { "actual": "s_axi_arvalid"},
+						"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
+						"AWREADY": { "actual": "s_axi_awready"},
+						"AWVALID": { "actual": "s_axi_awvalid"},
+						"BREADY": { "actual": "s_axi_bready"},
+						"BRESP": { "actual": "s_axi_bresp[1:0]"},
+						"BVALID": { "actual": "s_axi_bvalid"},
+						"RDATA": { "actual": "s_axi_rdata[31:0]"},
+						"RREADY": { "actual": "s_axi_rready"},
+						"RRESP": { "actual": "s_axi_rresp[1:0]"},
+						"RVALID": { "actual": "s_axi_rvalid"},
+						"WDATA": { "actual": "s_axi_wdata[31:0]"},
+						"WREADY": { "actual": "s_axi_wready"},
+						"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+						"WVALID": { "actual": "s_axi_wvalid"}
+					}
+				},
+				"/axi_gpio_0/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "s_axi_aclk"},
+						"ARADDR": { "actual": "s_axi_araddr[8:0]"},
+						"ARESETN": { "actual": "s_axi_aresetn"},
+						"ARREADY": { "actual": "s_axi_arready"},
+						"ARVALID": { "actual": "s_axi_arvalid"},
+						"AWADDR": { "actual": "s_axi_awaddr[8:0]"},
+						"AWREADY": { "actual": "s_axi_awready"},
+						"AWVALID": { "actual": "s_axi_awvalid"},
+						"BREADY": { "actual": "s_axi_bready"},
+						"BRESP": { "actual": "s_axi_bresp[1:0]"},
+						"BVALID": { "actual": "s_axi_bvalid"},
+						"RDATA": { "actual": "s_axi_rdata[31:0]"},
+						"RREADY": { "actual": "s_axi_rready"},
+						"RRESP": { "actual": "s_axi_rresp[1:0]"},
+						"RVALID": { "actual": "s_axi_rvalid"},
+						"WDATA": { "actual": "s_axi_wdata[31:0]"},
+						"WREADY": { "actual": "s_axi_wready"},
+						"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+						"WVALID": { "actual": "s_axi_wvalid"}
+					}
+				},
+				"/axi_intc_0/s_axi": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "s_axi_aclk"},
+						"ARADDR": { "actual": "s_axi_araddr[8:0]"},
+						"ARESETN": { "actual": "s_axi_aresetn"},
+						"ARREADY": { "actual": "s_axi_arready"},
+						"ARVALID": { "actual": "s_axi_arvalid"},
+						"AWADDR": { "actual": "s_axi_awaddr[8:0]"},
+						"AWREADY": { "actual": "s_axi_awready"},
+						"AWVALID": { "actual": "s_axi_awvalid"},
+						"BREADY": { "actual": "s_axi_bready"},
+						"BRESP": { "actual": "s_axi_bresp[1:0]"},
+						"BVALID": { "actual": "s_axi_bvalid"},
+						"RDATA": { "actual": "s_axi_rdata[31:0]"},
+						"RREADY": { "actual": "s_axi_rready"},
+						"RRESP": { "actual": "s_axi_rresp[1:0]"},
+						"RVALID": { "actual": "s_axi_rvalid"},
+						"WDATA": { "actual": "s_axi_wdata[31:0]"},
+						"WREADY": { "actual": "s_axi_wready"},
+						"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+						"WVALID": { "actual": "s_axi_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/M00_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M00_ACLK"},
+						"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
+						"ARESETN": { "actual": "ARESETN"},
+						"ARREADY": { "actual": "M00_AXI_arready"},
+						"ARVALID": { "actual": "M00_AXI_arvalid"},
+						"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
+						"AWREADY": { "actual": "M00_AXI_awready"},
+						"AWVALID": { "actual": "M00_AXI_awvalid"},
+						"BREADY": { "actual": "M00_AXI_bready"},
+						"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
+						"BVALID": { "actual": "M00_AXI_bvalid"},
+						"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
+						"RREADY": { "actual": "M00_AXI_rready"},
+						"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
+						"RVALID": { "actual": "M00_AXI_rvalid"},
+						"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
+						"WREADY": { "actual": "M00_AXI_wready"},
+						"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
+						"WVALID": { "actual": "M00_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/M01_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M01_ACLK"},
+						"ARADDR": { "actual": "M01_AXI_araddr[63:32]"},
+						"ARESETN": { "actual": "ARESETN"},
+						"ARREADY": { "actual": "M01_AXI_arready"},
+						"ARVALID": { "actual": "M01_AXI_arvalid"},
+						"AWADDR": { "actual": "M01_AXI_awaddr[63:32]"},
+						"AWREADY": { "actual": "M01_AXI_awready"},
+						"AWVALID": { "actual": "M01_AXI_awvalid"},
+						"BREADY": { "actual": "M01_AXI_bready"},
+						"BRESP": { "actual": "M01_AXI_bresp[3:2]"},
+						"BVALID": { "actual": "M01_AXI_bvalid"},
+						"RDATA": { "actual": "M01_AXI_rdata[63:32]"},
+						"RREADY": { "actual": "M01_AXI_rready"},
+						"RRESP": { "actual": "M01_AXI_rresp[3:2]"},
+						"RVALID": { "actual": "M01_AXI_rvalid"},
+						"WDATA": { "actual": "M01_AXI_wdata[63:32]"},
+						"WREADY": { "actual": "M01_AXI_wready"},
+						"WSTRB": { "actual": "M01_AXI_wstrb[7:4]"},
+						"WVALID": { "actual": "M01_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/M02_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M02_ACLK"},
+						"ARADDR": { "actual": "M02_AXI_araddr[95:64]"},
+						"ARESETN": { "actual": "ARESETN"},
+						"ARREADY": { "actual": "M02_AXI_arready"},
+						"ARVALID": { "actual": "M02_AXI_arvalid"},
+						"AWADDR": { "actual": "M02_AXI_awaddr[95:64]"},
+						"AWREADY": { "actual": "M02_AXI_awready"},
+						"AWVALID": { "actual": "M02_AXI_awvalid"},
+						"BREADY": { "actual": "M02_AXI_bready"},
+						"BRESP": { "actual": "M02_AXI_bresp[5:4]"},
+						"BVALID": { "actual": "M02_AXI_bvalid"},
+						"RDATA": { "actual": "M02_AXI_rdata[95:64]"},
+						"RREADY": { "actual": "M02_AXI_rready"},
+						"RRESP": { "actual": "M02_AXI_rresp[5:4]"},
+						"RVALID": { "actual": "M02_AXI_rvalid"},
+						"WDATA": { "actual": "M02_AXI_wdata[95:64]"},
+						"WREADY": { "actual": "M02_AXI_wready"},
+						"WSTRB": { "actual": "M02_AXI_wstrb[11:8]"},
+						"WVALID": { "actual": "M02_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/M03_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M03_ACLK"},
+						"ARADDR": { "actual": "M03_AXI_araddr[127:96]"},
+						"ARESETN": { "actual": "ARESETN"},
+						"ARREADY": { "actual": "M03_AXI_arready"},
+						"ARVALID": { "actual": "M03_AXI_arvalid"},
+						"AWADDR": { "actual": "M03_AXI_awaddr[127:96]"},
+						"AWREADY": { "actual": "M03_AXI_awready"},
+						"AWVALID": { "actual": "M03_AXI_awvalid"},
+						"BREADY": { "actual": "M03_AXI_bready"},
+						"BRESP": { "actual": "M03_AXI_bresp[7:6]"},
+						"BVALID": { "actual": "M03_AXI_bvalid"},
+						"RDATA": { "actual": "M03_AXI_rdata[127:96]"},
+						"RREADY": { "actual": "M03_AXI_rready"},
+						"RRESP": { "actual": "M03_AXI_rresp[7:6]"},
+						"RVALID": { "actual": "M03_AXI_rvalid"},
+						"WDATA": { "actual": "M03_AXI_wdata[127:96]"},
+						"WREADY": { "actual": "M03_AXI_wready"},
+						"WSTRB": { "actual": "M03_AXI_wstrb[15:12]"},
+						"WVALID": { "actual": "M03_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/M04_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M04_ACLK"},
+						"ARADDR": { "actual": "M04_AXI_araddr[159:128]"},
+						"ARESETN": { "actual": "ARESETN"},
+						"ARREADY": { "actual": "M04_AXI_arready"},
+						"ARVALID": { "actual": "M04_AXI_arvalid"},
+						"AWADDR": { "actual": "M04_AXI_awaddr[159:128]"},
+						"AWREADY": { "actual": "M04_AXI_awready"},
+						"AWVALID": { "actual": "M04_AXI_awvalid"},
+						"BREADY": { "actual": "M04_AXI_bready"},
+						"BRESP": { "actual": "M04_AXI_bresp[9:8]"},
+						"BVALID": { "actual": "M04_AXI_bvalid"},
+						"RDATA": { "actual": "M04_AXI_rdata[159:128]"},
+						"RREADY": { "actual": "M04_AXI_rready"},
+						"RRESP": { "actual": "M04_AXI_rresp[9:8]"},
+						"RVALID": { "actual": "M04_AXI_rvalid"},
+						"WDATA": { "actual": "M04_AXI_wdata[159:128]"},
+						"WREADY": { "actual": "M04_AXI_wready"},
+						"WSTRB": { "actual": "M04_AXI_wstrb[19:16]"},
+						"WVALID": { "actual": "M04_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/S00_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S00_ACLK"},
+						"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
+						"ARESETN": { "actual": "ARESETN"},
+						"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
+						"ARREADY": { "actual": "S00_AXI_arready[0:0]"},
+						"ARVALID": { "actual": "S00_AXI_arvalid[0:0]"},
+						"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
+						"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
+						"AWREADY": { "actual": "S00_AXI_awready[0:0]"},
+						"AWVALID": { "actual": "S00_AXI_awvalid[0:0]"},
+						"BREADY": { "actual": "S00_AXI_bready[0:0]"},
+						"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
+						"BVALID": { "actual": "S00_AXI_bvalid[0:0]"},
+						"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
+						"RREADY": { "actual": "S00_AXI_rready[0:0]"},
+						"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
+						"RVALID": { "actual": "S00_AXI_rvalid[0:0]"},
+						"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
+						"WREADY": { "actual": "S00_AXI_wready[0:0]"},
+						"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
+						"WVALID": { "actual": "S00_AXI_wvalid[0:0]"}
+					}
+				},
+				"/axi_interconnect_0/m00_couplers/M_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M_ACLK"},
+						"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
+						"ARESETN": { "actual": "M_ARESETN"},
+						"ARREADY": { "actual": "M_AXI_arready"},
+						"ARVALID": { "actual": "M_AXI_arvalid"},
+						"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
+						"AWREADY": { "actual": "M_AXI_awready"},
+						"AWVALID": { "actual": "M_AXI_awvalid"},
+						"BREADY": { "actual": "M_AXI_bready"},
+						"BRESP": { "actual": "M_AXI_bresp[1:0]"},
+						"BVALID": { "actual": "M_AXI_bvalid"},
+						"RDATA": { "actual": "M_AXI_rdata[31:0]"},
+						"RREADY": { "actual": "M_AXI_rready"},
+						"RRESP": { "actual": "M_AXI_rresp[1:0]"},
+						"RVALID": { "actual": "M_AXI_rvalid"},
+						"WDATA": { "actual": "M_AXI_wdata[31:0]"},
+						"WREADY": { "actual": "M_AXI_wready"},
+						"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
+						"WVALID": { "actual": "M_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m00_couplers/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_ACLK"},
+						"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
+						"ARESETN": { "actual": "S_ARESETN"},
+						"ARREADY": { "actual": "S_AXI_arready"},
+						"ARVALID": { "actual": "S_AXI_arvalid"},
+						"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
+						"AWREADY": { "actual": "S_AXI_awready"},
+						"AWVALID": { "actual": "S_AXI_awvalid"},
+						"BREADY": { "actual": "S_AXI_bready"},
+						"BRESP": { "actual": "S_AXI_bresp[1:0]"},
+						"BVALID": { "actual": "S_AXI_bvalid"},
+						"RDATA": { "actual": "S_AXI_rdata[31:0]"},
+						"RREADY": { "actual": "S_AXI_rready"},
+						"RRESP": { "actual": "S_AXI_rresp[1:0]"},
+						"RVALID": { "actual": "S_AXI_rvalid"},
+						"WDATA": { "actual": "S_AXI_wdata[31:0]"},
+						"WREADY": { "actual": "S_AXI_wready"},
+						"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
+						"WVALID": { "actual": "S_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m01_couplers/M_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M_ACLK"},
+						"ARADDR": { "actual": "M_AXI_araddr[63:32]"},
+						"ARESETN": { "actual": "M_ARESETN"},
+						"ARREADY": { "actual": "M_AXI_arready"},
+						"ARVALID": { "actual": "M_AXI_arvalid"},
+						"AWADDR": { "actual": "M_AXI_awaddr[63:32]"},
+						"AWREADY": { "actual": "M_AXI_awready"},
+						"AWVALID": { "actual": "M_AXI_awvalid"},
+						"BREADY": { "actual": "M_AXI_bready"},
+						"BRESP": { "actual": "M_AXI_bresp[3:2]"},
+						"BVALID": { "actual": "M_AXI_bvalid"},
+						"RDATA": { "actual": "M_AXI_rdata[63:32]"},
+						"RREADY": { "actual": "M_AXI_rready"},
+						"RRESP": { "actual": "M_AXI_rresp[3:2]"},
+						"RVALID": { "actual": "M_AXI_rvalid"},
+						"WDATA": { "actual": "M_AXI_wdata[63:32]"},
+						"WREADY": { "actual": "M_AXI_wready"},
+						"WSTRB": { "actual": "M_AXI_wstrb[7:4]"},
+						"WVALID": { "actual": "M_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m01_couplers/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_ACLK"},
+						"ARADDR": { "actual": "S_AXI_araddr[63:32]"},
+						"ARESETN": { "actual": "S_ARESETN"},
+						"ARREADY": { "actual": "S_AXI_arready"},
+						"ARVALID": { "actual": "S_AXI_arvalid"},
+						"AWADDR": { "actual": "S_AXI_awaddr[63:32]"},
+						"AWREADY": { "actual": "S_AXI_awready"},
+						"AWVALID": { "actual": "S_AXI_awvalid"},
+						"BREADY": { "actual": "S_AXI_bready"},
+						"BRESP": { "actual": "S_AXI_bresp[3:2]"},
+						"BVALID": { "actual": "S_AXI_bvalid"},
+						"RDATA": { "actual": "S_AXI_rdata[63:32]"},
+						"RREADY": { "actual": "S_AXI_rready"},
+						"RRESP": { "actual": "S_AXI_rresp[3:2]"},
+						"RVALID": { "actual": "S_AXI_rvalid"},
+						"WDATA": { "actual": "S_AXI_wdata[63:32]"},
+						"WREADY": { "actual": "S_AXI_wready"},
+						"WSTRB": { "actual": "S_AXI_wstrb[7:4]"},
+						"WVALID": { "actual": "S_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m02_couplers/M_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M_ACLK"},
+						"ARADDR": { "actual": "M_AXI_araddr[95:64]"},
+						"ARESETN": { "actual": "M_ARESETN"},
+						"ARREADY": { "actual": "M_AXI_arready"},
+						"ARVALID": { "actual": "M_AXI_arvalid"},
+						"AWADDR": { "actual": "M_AXI_awaddr[95:64]"},
+						"AWREADY": { "actual": "M_AXI_awready"},
+						"AWVALID": { "actual": "M_AXI_awvalid"},
+						"BREADY": { "actual": "M_AXI_bready"},
+						"BRESP": { "actual": "M_AXI_bresp[5:4]"},
+						"BVALID": { "actual": "M_AXI_bvalid"},
+						"RDATA": { "actual": "M_AXI_rdata[95:64]"},
+						"RREADY": { "actual": "M_AXI_rready"},
+						"RRESP": { "actual": "M_AXI_rresp[5:4]"},
+						"RVALID": { "actual": "M_AXI_rvalid"},
+						"WDATA": { "actual": "M_AXI_wdata[95:64]"},
+						"WREADY": { "actual": "M_AXI_wready"},
+						"WSTRB": { "actual": "M_AXI_wstrb[11:8]"},
+						"WVALID": { "actual": "M_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m02_couplers/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_ACLK"},
+						"ARADDR": { "actual": "S_AXI_araddr[95:64]"},
+						"ARESETN": { "actual": "S_ARESETN"},
+						"ARREADY": { "actual": "S_AXI_arready"},
+						"ARVALID": { "actual": "S_AXI_arvalid"},
+						"AWADDR": { "actual": "S_AXI_awaddr[95:64]"},
+						"AWREADY": { "actual": "S_AXI_awready"},
+						"AWVALID": { "actual": "S_AXI_awvalid"},
+						"BREADY": { "actual": "S_AXI_bready"},
+						"BRESP": { "actual": "S_AXI_bresp[5:4]"},
+						"BVALID": { "actual": "S_AXI_bvalid"},
+						"RDATA": { "actual": "S_AXI_rdata[95:64]"},
+						"RREADY": { "actual": "S_AXI_rready"},
+						"RRESP": { "actual": "S_AXI_rresp[5:4]"},
+						"RVALID": { "actual": "S_AXI_rvalid"},
+						"WDATA": { "actual": "S_AXI_wdata[95:64]"},
+						"WREADY": { "actual": "S_AXI_wready"},
+						"WSTRB": { "actual": "S_AXI_wstrb[11:8]"},
+						"WVALID": { "actual": "S_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m03_couplers/M_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M_ACLK"},
+						"ARADDR": { "actual": "M_AXI_araddr[127:96]"},
+						"ARESETN": { "actual": "M_ARESETN"},
+						"ARREADY": { "actual": "M_AXI_arready"},
+						"ARVALID": { "actual": "M_AXI_arvalid"},
+						"AWADDR": { "actual": "M_AXI_awaddr[127:96]"},
+						"AWREADY": { "actual": "M_AXI_awready"},
+						"AWVALID": { "actual": "M_AXI_awvalid"},
+						"BREADY": { "actual": "M_AXI_bready"},
+						"BRESP": { "actual": "M_AXI_bresp[7:6]"},
+						"BVALID": { "actual": "M_AXI_bvalid"},
+						"RDATA": { "actual": "M_AXI_rdata[127:96]"},
+						"RREADY": { "actual": "M_AXI_rready"},
+						"RRESP": { "actual": "M_AXI_rresp[7:6]"},
+						"RVALID": { "actual": "M_AXI_rvalid"},
+						"WDATA": { "actual": "M_AXI_wdata[127:96]"},
+						"WREADY": { "actual": "M_AXI_wready"},
+						"WSTRB": { "actual": "M_AXI_wstrb[15:12]"},
+						"WVALID": { "actual": "M_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m03_couplers/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_ACLK"},
+						"ARADDR": { "actual": "S_AXI_araddr[127:96]"},
+						"ARESETN": { "actual": "S_ARESETN"},
+						"ARREADY": { "actual": "S_AXI_arready"},
+						"ARVALID": { "actual": "S_AXI_arvalid"},
+						"AWADDR": { "actual": "S_AXI_awaddr[127:96]"},
+						"AWREADY": { "actual": "S_AXI_awready"},
+						"AWVALID": { "actual": "S_AXI_awvalid"},
+						"BREADY": { "actual": "S_AXI_bready"},
+						"BRESP": { "actual": "S_AXI_bresp[7:6]"},
+						"BVALID": { "actual": "S_AXI_bvalid"},
+						"RDATA": { "actual": "S_AXI_rdata[127:96]"},
+						"RREADY": { "actual": "S_AXI_rready"},
+						"RRESP": { "actual": "S_AXI_rresp[7:6]"},
+						"RVALID": { "actual": "S_AXI_rvalid"},
+						"WDATA": { "actual": "S_AXI_wdata[127:96]"},
+						"WREADY": { "actual": "S_AXI_wready"},
+						"WSTRB": { "actual": "S_AXI_wstrb[15:12]"},
+						"WVALID": { "actual": "S_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m04_couplers/M_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M_ACLK"},
+						"ARADDR": { "actual": "M_AXI_araddr[159:128]"},
+						"ARESETN": { "actual": "M_ARESETN"},
+						"ARREADY": { "actual": "M_AXI_arready"},
+						"ARVALID": { "actual": "M_AXI_arvalid"},
+						"AWADDR": { "actual": "M_AXI_awaddr[159:128]"},
+						"AWREADY": { "actual": "M_AXI_awready"},
+						"AWVALID": { "actual": "M_AXI_awvalid"},
+						"BREADY": { "actual": "M_AXI_bready"},
+						"BRESP": { "actual": "M_AXI_bresp[9:8]"},
+						"BVALID": { "actual": "M_AXI_bvalid"},
+						"RDATA": { "actual": "M_AXI_rdata[159:128]"},
+						"RREADY": { "actual": "M_AXI_rready"},
+						"RRESP": { "actual": "M_AXI_rresp[9:8]"},
+						"RVALID": { "actual": "M_AXI_rvalid"},
+						"WDATA": { "actual": "M_AXI_wdata[159:128]"},
+						"WREADY": { "actual": "M_AXI_wready"},
+						"WSTRB": { "actual": "M_AXI_wstrb[19:16]"},
+						"WVALID": { "actual": "M_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/m04_couplers/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_ACLK"},
+						"ARADDR": { "actual": "S_AXI_araddr[159:128]"},
+						"ARESETN": { "actual": "S_ARESETN"},
+						"ARREADY": { "actual": "S_AXI_arready"},
+						"ARVALID": { "actual": "S_AXI_arvalid"},
+						"AWADDR": { "actual": "S_AXI_awaddr[159:128]"},
+						"AWREADY": { "actual": "S_AXI_awready"},
+						"AWVALID": { "actual": "S_AXI_awvalid"},
+						"BREADY": { "actual": "S_AXI_bready"},
+						"BRESP": { "actual": "S_AXI_bresp[9:8]"},
+						"BVALID": { "actual": "S_AXI_bvalid"},
+						"RDATA": { "actual": "S_AXI_rdata[159:128]"},
+						"RREADY": { "actual": "S_AXI_rready"},
+						"RRESP": { "actual": "S_AXI_rresp[9:8]"},
+						"RVALID": { "actual": "S_AXI_rvalid"},
+						"WDATA": { "actual": "S_AXI_wdata[159:128]"},
+						"WREADY": { "actual": "S_AXI_wready"},
+						"WSTRB": { "actual": "S_AXI_wstrb[19:16]"},
+						"WVALID": { "actual": "S_AXI_wvalid"}
+					}
+				},
+				"/axi_interconnect_0/s00_couplers/M_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "M_ACLK"},
+						"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
+						"ARESETN": { "actual": "M_ARESETN"},
+						"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
+						"ARREADY": { "actual": "M_AXI_arready[0:0]"},
+						"ARVALID": { "actual": "M_AXI_arvalid[0:0]"},
+						"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
+						"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
+						"AWREADY": { "actual": "M_AXI_awready[0:0]"},
+						"AWVALID": { "actual": "M_AXI_awvalid[0:0]"},
+						"BREADY": { "actual": "M_AXI_bready[0:0]"},
+						"BRESP": { "actual": "M_AXI_bresp[1:0]"},
+						"BVALID": { "actual": "M_AXI_bvalid[0:0]"},
+						"RDATA": { "actual": "M_AXI_rdata[31:0]"},
+						"RREADY": { "actual": "M_AXI_rready[0:0]"},
+						"RRESP": { "actual": "M_AXI_rresp[1:0]"},
+						"RVALID": { "actual": "M_AXI_rvalid[0:0]"},
+						"WDATA": { "actual": "M_AXI_wdata[31:0]"},
+						"WREADY": { "actual": "M_AXI_wready[0:0]"},
+						"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
+						"WVALID": { "actual": "M_AXI_wvalid[0:0]"}
+					}
+				},
+				"/axi_interconnect_0/s00_couplers/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_ACLK"},
+						"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
+						"ARESETN": { "actual": "S_ARESETN"},
+						"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
+						"ARREADY": { "actual": "S_AXI_arready[0:0]"},
+						"ARVALID": { "actual": "S_AXI_arvalid[0:0]"},
+						"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
+						"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
+						"AWREADY": { "actual": "S_AXI_awready[0:0]"},
+						"AWVALID": { "actual": "S_AXI_awvalid[0:0]"},
+						"BREADY": { "actual": "S_AXI_bready[0:0]"},
+						"BRESP": { "actual": "S_AXI_bresp[1:0]"},
+						"BVALID": { "actual": "S_AXI_bvalid[0:0]"},
+						"RDATA": { "actual": "S_AXI_rdata[31:0]"},
+						"RREADY": { "actual": "S_AXI_rready[0:0]"},
+						"RRESP": { "actual": "S_AXI_rresp[1:0]"},
+						"RVALID": { "actual": "S_AXI_rvalid[0:0]"},
+						"WDATA": { "actual": "S_AXI_wdata[31:0]"},
+						"WREADY": { "actual": "S_AXI_wready[0:0]"},
+						"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
+						"WVALID": { "actual": "S_AXI_wvalid[0:0]"}
+					}
+				},
+				"/axi_interconnect_0/xbar/M00_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "aclk"},
+						"ARADDR": { "actual": "m_axi_araddr[31:0]"},
+						"ARESETN": { "actual": "aresetn"},
+						"ARPROT": { "actual": "m_axi_arprot[2:0]"},
+						"ARREADY": { "actual": "m_axi_arready[0:0]"},
+						"ARVALID": { "actual": "m_axi_arvalid[0:0]"},
+						"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
+						"AWPROT": { "actual": "m_axi_awprot[2:0]"},
+						"AWREADY": { "actual": "m_axi_awready[0:0]"},
+						"AWVALID": { "actual": "m_axi_awvalid[0:0]"},
+						"BREADY": { "actual": "m_axi_bready[0:0]"},
+						"BRESP": { "actual": "m_axi_bresp[1:0]"},
+						"BVALID": { "actual": "m_axi_bvalid[0:0]"},
+						"RDATA": { "actual": "m_axi_rdata[31:0]"},
+						"RREADY": { "actual": "m_axi_rready[0:0]"},
+						"RRESP": { "actual": "m_axi_rresp[1:0]"},
+						"RVALID": { "actual": "m_axi_rvalid[0:0]"},
+						"WDATA": { "actual": "m_axi_wdata[31:0]"},
+						"WREADY": { "actual": "m_axi_wready[0:0]"},
+						"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
+						"WVALID": { "actual": "m_axi_wvalid[0:0]"}
+					}
+				},
+				"/axi_interconnect_0/xbar/M01_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "aclk"},
+						"ARADDR": { "actual": "m_axi_araddr[63:32]"},
+						"ARESETN": { "actual": "aresetn"},
+						"ARPROT": { "actual": "m_axi_arprot[5:3]"},
+						"ARREADY": { "actual": "m_axi_arready[1:1]"},
+						"ARVALID": { "actual": "m_axi_arvalid[1:1]"},
+						"AWADDR": { "actual": "m_axi_awaddr[63:32]"},
+						"AWPROT": { "actual": "m_axi_awprot[5:3]"},
+						"AWREADY": { "actual": "m_axi_awready[1:1]"},
+						"AWVALID": { "actual": "m_axi_awvalid[1:1]"},
+						"BREADY": { "actual": "m_axi_bready[1:1]"},
+						"BRESP": { "actual": "m_axi_bresp[3:2]"},
+						"BVALID": { "actual": "m_axi_bvalid[1:1]"},
+						"RDATA": { "actual": "m_axi_rdata[63:32]"},
+						"RREADY": { "actual": "m_axi_rready[1:1]"},
+						"RRESP": { "actual": "m_axi_rresp[3:2]"},
+						"RVALID": { "actual": "m_axi_rvalid[1:1]"},
+						"WDATA": { "actual": "m_axi_wdata[63:32]"},
+						"WREADY": { "actual": "m_axi_wready[1:1]"},
+						"WSTRB": { "actual": "m_axi_wstrb[7:4]"},
+						"WVALID": { "actual": "m_axi_wvalid[1:1]"}
+					}
+				},
+				"/axi_interconnect_0/xbar/M02_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "aclk"},
+						"ARADDR": { "actual": "m_axi_araddr[95:64]"},
+						"ARESETN": { "actual": "aresetn"},
+						"ARPROT": { "actual": "m_axi_arprot[8:6]"},
+						"ARREADY": { "actual": "m_axi_arready[2:2]"},
+						"ARVALID": { "actual": "m_axi_arvalid[2:2]"},
+						"AWADDR": { "actual": "m_axi_awaddr[95:64]"},
+						"AWPROT": { "actual": "m_axi_awprot[8:6]"},
+						"AWREADY": { "actual": "m_axi_awready[2:2]"},
+						"AWVALID": { "actual": "m_axi_awvalid[2:2]"},
+						"BREADY": { "actual": "m_axi_bready[2:2]"},
+						"BRESP": { "actual": "m_axi_bresp[5:4]"},
+						"BVALID": { "actual": "m_axi_bvalid[2:2]"},
+						"RDATA": { "actual": "m_axi_rdata[95:64]"},
+						"RREADY": { "actual": "m_axi_rready[2:2]"},
+						"RRESP": { "actual": "m_axi_rresp[5:4]"},
+						"RVALID": { "actual": "m_axi_rvalid[2:2]"},
+						"WDATA": { "actual": "m_axi_wdata[95:64]"},
+						"WREADY": { "actual": "m_axi_wready[2:2]"},
+						"WSTRB": { "actual": "m_axi_wstrb[11:8]"},
+						"WVALID": { "actual": "m_axi_wvalid[2:2]"}
+					}
+				},
+				"/axi_interconnect_0/xbar/M03_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "aclk"},
+						"ARADDR": { "actual": "m_axi_araddr[127:96]"},
+						"ARESETN": { "actual": "aresetn"},
+						"ARPROT": { "actual": "m_axi_arprot[11:9]"},
+						"ARREADY": { "actual": "m_axi_arready[3:3]"},
+						"ARVALID": { "actual": "m_axi_arvalid[3:3]"},
+						"AWADDR": { "actual": "m_axi_awaddr[127:96]"},
+						"AWPROT": { "actual": "m_axi_awprot[11:9]"},
+						"AWREADY": { "actual": "m_axi_awready[3:3]"},
+						"AWVALID": { "actual": "m_axi_awvalid[3:3]"},
+						"BREADY": { "actual": "m_axi_bready[3:3]"},
+						"BRESP": { "actual": "m_axi_bresp[7:6]"},
+						"BVALID": { "actual": "m_axi_bvalid[3:3]"},
+						"RDATA": { "actual": "m_axi_rdata[127:96]"},
+						"RREADY": { "actual": "m_axi_rready[3:3]"},
+						"RRESP": { "actual": "m_axi_rresp[7:6]"},
+						"RVALID": { "actual": "m_axi_rvalid[3:3]"},
+						"WDATA": { "actual": "m_axi_wdata[127:96]"},
+						"WREADY": { "actual": "m_axi_wready[3:3]"},
+						"WSTRB": { "actual": "m_axi_wstrb[15:12]"},
+						"WVALID": { "actual": "m_axi_wvalid[3:3]"}
+					}
+				},
+				"/axi_interconnect_0/xbar/M04_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "aclk"},
+						"ARADDR": { "actual": "m_axi_araddr[159:128]"},
+						"ARESETN": { "actual": "aresetn"},
+						"ARPROT": { "actual": "m_axi_arprot[14:12]"},
+						"ARREADY": { "actual": "m_axi_arready[4:4]"},
+						"ARVALID": { "actual": "m_axi_arvalid[4:4]"},
+						"AWADDR": { "actual": "m_axi_awaddr[159:128]"},
+						"AWPROT": { "actual": "m_axi_awprot[14:12]"},
+						"AWREADY": { "actual": "m_axi_awready[4:4]"},
+						"AWVALID": { "actual": "m_axi_awvalid[4:4]"},
+						"BREADY": { "actual": "m_axi_bready[4:4]"},
+						"BRESP": { "actual": "m_axi_bresp[9:8]"},
+						"BVALID": { "actual": "m_axi_bvalid[4:4]"},
+						"RDATA": { "actual": "m_axi_rdata[159:128]"},
+						"RREADY": { "actual": "m_axi_rready[4:4]"},
+						"RRESP": { "actual": "m_axi_rresp[9:8]"},
+						"RVALID": { "actual": "m_axi_rvalid[4:4]"},
+						"WDATA": { "actual": "m_axi_wdata[159:128]"},
+						"WREADY": { "actual": "m_axi_wready[4:4]"},
+						"WSTRB": { "actual": "m_axi_wstrb[19:16]"},
+						"WVALID": { "actual": "m_axi_wvalid[4:4]"}
+					}
+				},
+				"/axi_interconnect_0/xbar/S00_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "aclk"},
+						"ARADDR": { "actual": "s_axi_araddr[31:0]"},
+						"ARESETN": { "actual": "aresetn"},
+						"ARPROT": { "actual": "s_axi_arprot[2:0]"},
+						"ARREADY": { "actual": "s_axi_arready[0:0]"},
+						"ARVALID": { "actual": "s_axi_arvalid[0:0]"},
+						"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
+						"AWPROT": { "actual": "s_axi_awprot[2:0]"},
+						"AWREADY": { "actual": "s_axi_awready[0:0]"},
+						"AWVALID": { "actual": "s_axi_awvalid[0:0]"},
+						"BREADY": { "actual": "s_axi_bready[0:0]"},
+						"BRESP": { "actual": "s_axi_bresp[1:0]"},
+						"BVALID": { "actual": "s_axi_bvalid[0:0]"},
+						"RDATA": { "actual": "s_axi_rdata[31:0]"},
+						"RREADY": { "actual": "s_axi_rready[0:0]"},
+						"RRESP": { "actual": "s_axi_rresp[1:0]"},
+						"RVALID": { "actual": "s_axi_rvalid[0:0]"},
+						"WDATA": { "actual": "s_axi_wdata[31:0]"},
+						"WREADY": { "actual": "s_axi_wready[0:0]"},
+						"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+						"WVALID": { "actual": "s_axi_wvalid[0:0]"}
+					}
+				},
+				"/axi_timer_0/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "s_axi_aclk"},
+						"ARADDR": { "actual": "s_axi_araddr[4:0]"},
+						"ARESETN": { "actual": "s_axi_aresetn"},
+						"ARREADY": { "actual": "s_axi_arready"},
+						"ARVALID": { "actual": "s_axi_arvalid"},
+						"AWADDR": { "actual": "s_axi_awaddr[4:0]"},
+						"AWREADY": { "actual": "s_axi_awready"},
+						"AWVALID": { "actual": "s_axi_awvalid"},
+						"BREADY": { "actual": "s_axi_bready"},
+						"BRESP": { "actual": "s_axi_bresp[1:0]"},
+						"BVALID": { "actual": "s_axi_bvalid"},
+						"RDATA": { "actual": "s_axi_rdata[31:0]"},
+						"RREADY": { "actual": "s_axi_rready"},
+						"RRESP": { "actual": "s_axi_rresp[1:0]"},
+						"RVALID": { "actual": "s_axi_rvalid"},
+						"WDATA": { "actual": "s_axi_wdata[31:0]"},
+						"WREADY": { "actual": "s_axi_wready"},
+						"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+						"WVALID": { "actual": "s_axi_wvalid"}
+					}
+				},
+				"/mdm_0/S_AXI": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "S_AXI_ACLK"},
+						"ARADDR": { "actual": "S_AXI_ARADDR[3:0]"},
+						"ARESETN": { "actual": "S_AXI_ARESETN"},
+						"ARREADY": { "actual": "S_AXI_ARREADY"},
+						"ARVALID": { "actual": "S_AXI_ARVALID"},
+						"AWADDR": { "actual": "S_AXI_AWADDR[3:0]"},
+						"AWREADY": { "actual": "S_AXI_AWREADY"},
+						"AWVALID": { "actual": "S_AXI_AWVALID"},
+						"BREADY": { "actual": "S_AXI_BREADY"},
+						"BRESP": { "actual": "S_AXI_BRESP[1:0]"},
+						"BVALID": { "actual": "S_AXI_BVALID"},
+						"RDATA": { "actual": "S_AXI_RDATA[31:0]"},
+						"RREADY": { "actual": "S_AXI_RREADY"},
+						"RRESP": { "actual": "S_AXI_RRESP[1:0]"},
+						"RVALID": { "actual": "S_AXI_RVALID"},
+						"WDATA": { "actual": "S_AXI_WDATA[31:0]"},
+						"WREADY": { "actual": "S_AXI_WREADY"},
+						"WSTRB": { "actual": "S_AXI_WSTRB[3:0]"},
+						"WVALID": { "actual": "S_AXI_WVALID"}
+					}
+				},
+				"/microblaze_0/M_AXI_DP": {
+					"interface": "xilinx.com:interface:aximm:1.0",
+					"ports": {
+						"ACLK": { "actual": "Clk"},
+						"ARADDR": { "actual": "M_AXI_DP_ARADDR[31:0]"},
+						"ARESET": { "actual": "Reset"},
+						"ARPROT": { "actual": "M_AXI_DP_ARPROT[2:0]"},
+						"ARREADY": { "actual": "M_AXI_DP_ARREADY"},
+						"ARVALID": { "actual": "M_AXI_DP_ARVALID"},
+						"AWADDR": { "actual": "M_AXI_DP_AWADDR[31:0]"},
+						"AWPROT": { "actual": "M_AXI_DP_AWPROT[2:0]"},
+						"AWREADY": { "actual": "M_AXI_DP_AWREADY"},
+						"AWVALID": { "actual": "M_AXI_DP_AWVALID"},
+						"BREADY": { "actual": "M_AXI_DP_BREADY"},
+						"BRESP": { "actual": "M_AXI_DP_BRESP[1:0]"},
+						"BVALID": { "actual": "M_AXI_DP_BVALID"},
+						"RDATA": { "actual": "M_AXI_DP_RDATA[31:0]"},
+						"RREADY": { "actual": "M_AXI_DP_RREADY"},
+						"RRESP": { "actual": "M_AXI_DP_RRESP[1:0]"},
+						"RVALID": { "actual": "M_AXI_DP_RVALID"},
+						"WDATA": { "actual": "M_AXI_DP_WDATA[31:0]"},
+						"WREADY": { "actual": "M_AXI_DP_WREADY"},
+						"WSTRB": { "actual": "M_AXI_DP_WSTRB[3:0]"},
+						"WVALID": { "actual": "M_AXI_DP_WVALID"}
+					}
+				}
+			}
+		}
+	}
+}
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b335fa1bf9f3a5acf54c568a927264a7d50963f9
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
@@ -0,0 +1,2741 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+--Date        : Sun Mar 23 23:26:53 2025
+--Host        : hogtest running 64-bit unknown
+--Command     : generate_target mb_design_1.bd
+--Design      : mb_design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m00_couplers_imp_L30N86 is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m00_couplers_imp_L30N86;
+
+architecture STRUCTURE of m00_couplers_imp_L30N86 is
+  signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
+  M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
+  M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
+  S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
+  S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
+  S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
+  m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
+  m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
+  m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
+  m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
+  m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
+  m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
+  m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
+  m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
+  m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
+  m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m01_couplers_imp_1MV3QBS is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m01_couplers_imp_1MV3QBS;
+
+architecture STRUCTURE of m01_couplers_imp_1MV3QBS is
+  signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
+  M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
+  M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
+  S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
+  S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
+  S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
+  m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
+  m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
+  m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
+  m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
+  m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
+  m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
+  m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
+  m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
+  m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
+  m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m02_couplers_imp_1CM8QGB is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m02_couplers_imp_1CM8QGB;
+
+architecture STRUCTURE of m02_couplers_imp_1CM8QGB is
+  signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
+  M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
+  M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
+  S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
+  S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
+  S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
+  m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
+  m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
+  m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
+  m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
+  m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
+  m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
+  m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
+  m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
+  m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
+  m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m03_couplers_imp_DKAE7P is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m03_couplers_imp_DKAE7P;
+
+architecture STRUCTURE of m03_couplers_imp_DKAE7P is
+  signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
+  M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
+  M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
+  S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
+  S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
+  S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
+  m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
+  m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
+  m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
+  m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
+  m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
+  m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
+  m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
+  m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
+  m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
+  m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m04_couplers_imp_OP7ZFX is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m04_couplers_imp_OP7ZFX;
+
+architecture STRUCTURE of m04_couplers_imp_OP7ZFX is
+  signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
+  M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
+  M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
+  S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
+  S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
+  S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
+  m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
+  m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
+  m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
+  m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
+  m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
+  m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
+  m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
+  m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
+  m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
+  m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity s00_couplers_imp_1AM08ZQ is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end s00_couplers_imp_1AM08ZQ;
+
+architecture STRUCTURE of s00_couplers_imp_1AM08ZQ is
+  signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
+  M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
+  M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
+  M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
+  M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
+  M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
+  M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
+  M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
+  M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
+  S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
+  S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
+  S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
+  S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
+  S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
+  s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
+  s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
+  s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
+  s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
+  s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
+  s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
+  s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
+  s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
+  s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
+  s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
+  s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
+  s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi_interconnect_0_0 is
+  port (
+    ACLK : in STD_LOGIC;
+    ARESETN : in STD_LOGIC;
+    M00_ACLK : in STD_LOGIC;
+    M00_ARESETN : in STD_LOGIC;
+    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_arready : in STD_LOGIC;
+    M00_AXI_arvalid : out STD_LOGIC;
+    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_awready : in STD_LOGIC;
+    M00_AXI_awvalid : out STD_LOGIC;
+    M00_AXI_bready : out STD_LOGIC;
+    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_bvalid : in STD_LOGIC;
+    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_rready : out STD_LOGIC;
+    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_rvalid : in STD_LOGIC;
+    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_wready : in STD_LOGIC;
+    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_wvalid : out STD_LOGIC;
+    M01_ACLK : in STD_LOGIC;
+    M01_ARESETN : in STD_LOGIC;
+    M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_arready : in STD_LOGIC;
+    M01_AXI_arvalid : out STD_LOGIC;
+    M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_awready : in STD_LOGIC;
+    M01_AXI_awvalid : out STD_LOGIC;
+    M01_AXI_bready : out STD_LOGIC;
+    M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M01_AXI_bvalid : in STD_LOGIC;
+    M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_rready : out STD_LOGIC;
+    M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M01_AXI_rvalid : in STD_LOGIC;
+    M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_wready : in STD_LOGIC;
+    M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M01_AXI_wvalid : out STD_LOGIC;
+    M02_ACLK : in STD_LOGIC;
+    M02_ARESETN : in STD_LOGIC;
+    M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_arready : in STD_LOGIC;
+    M02_AXI_arvalid : out STD_LOGIC;
+    M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_awready : in STD_LOGIC;
+    M02_AXI_awvalid : out STD_LOGIC;
+    M02_AXI_bready : out STD_LOGIC;
+    M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M02_AXI_bvalid : in STD_LOGIC;
+    M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_rready : out STD_LOGIC;
+    M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M02_AXI_rvalid : in STD_LOGIC;
+    M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_wready : in STD_LOGIC;
+    M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M02_AXI_wvalid : out STD_LOGIC;
+    M03_ACLK : in STD_LOGIC;
+    M03_ARESETN : in STD_LOGIC;
+    M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_arready : in STD_LOGIC;
+    M03_AXI_arvalid : out STD_LOGIC;
+    M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_awready : in STD_LOGIC;
+    M03_AXI_awvalid : out STD_LOGIC;
+    M03_AXI_bready : out STD_LOGIC;
+    M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M03_AXI_bvalid : in STD_LOGIC;
+    M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_rready : out STD_LOGIC;
+    M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M03_AXI_rvalid : in STD_LOGIC;
+    M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_wready : in STD_LOGIC;
+    M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M03_AXI_wvalid : out STD_LOGIC;
+    M04_ACLK : in STD_LOGIC;
+    M04_ARESETN : in STD_LOGIC;
+    M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_arready : in STD_LOGIC;
+    M04_AXI_arvalid : out STD_LOGIC;
+    M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_awready : in STD_LOGIC;
+    M04_AXI_awvalid : out STD_LOGIC;
+    M04_AXI_bready : out STD_LOGIC;
+    M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M04_AXI_bvalid : in STD_LOGIC;
+    M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_rready : out STD_LOGIC;
+    M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M04_AXI_rvalid : in STD_LOGIC;
+    M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_wready : in STD_LOGIC;
+    M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M04_AXI_wvalid : out STD_LOGIC;
+    S00_ACLK : in STD_LOGIC;
+    S00_ARESETN : in STD_LOGIC;
+    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end mb_design_1_axi_interconnect_0_0;
+
+architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
+  component mb_design_1_xbar_0 is
+  port (
+    aclk : in STD_LOGIC;
+    aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+    m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+    m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+    m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+    m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+    m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
+  );
+  end component mb_design_1_xbar_0;
+  signal M00_ACLK_1 : STD_LOGIC;
+  signal M00_ARESETN_1 : STD_LOGIC;
+  signal M01_ACLK_1 : STD_LOGIC;
+  signal M01_ARESETN_1 : STD_LOGIC;
+  signal M02_ACLK_1 : STD_LOGIC;
+  signal M02_ARESETN_1 : STD_LOGIC;
+  signal M03_ACLK_1 : STD_LOGIC;
+  signal M03_ARESETN_1 : STD_LOGIC;
+  signal M04_ACLK_1 : STD_LOGIC;
+  signal M04_ARESETN_1 : STD_LOGIC;
+  signal S00_ACLK_1 : STD_LOGIC;
+  signal S00_ARESETN_1 : STD_LOGIC;
+  signal axi_interconnect_0_ACLK_net : STD_LOGIC;
+  signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
+  signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
+  signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
+  signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
+  signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
+  signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
+  signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
+  signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
+  signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
+  signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
+  signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
+  signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
+  signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
+  signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+  signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+  signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
+  signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
+  signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+  signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+begin
+  M00_ACLK_1 <= M00_ACLK;
+  M00_ARESETN_1 <= M00_ARESETN;
+  M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
+  M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
+  M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
+  M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
+  M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
+  M01_ACLK_1 <= M01_ACLK;
+  M01_ARESETN_1 <= M01_ARESETN;
+  M01_AXI_araddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
+  M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
+  M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
+  M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
+  M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
+  M02_ACLK_1 <= M02_ACLK;
+  M02_ARESETN_1 <= M02_ARESETN;
+  M02_AXI_araddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M02_AXI_arvalid <= m02_couplers_to_axi_interconnect_0_ARVALID;
+  M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M02_AXI_awvalid <= m02_couplers_to_axi_interconnect_0_AWVALID;
+  M02_AXI_bready <= m02_couplers_to_axi_interconnect_0_BREADY;
+  M02_AXI_rready <= m02_couplers_to_axi_interconnect_0_RREADY;
+  M02_AXI_wdata(31 downto 0) <= m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M02_AXI_wvalid <= m02_couplers_to_axi_interconnect_0_WVALID;
+  M03_ACLK_1 <= M03_ACLK;
+  M03_ARESETN_1 <= M03_ARESETN;
+  M03_AXI_araddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M03_AXI_arvalid <= m03_couplers_to_axi_interconnect_0_ARVALID;
+  M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M03_AXI_awvalid <= m03_couplers_to_axi_interconnect_0_AWVALID;
+  M03_AXI_bready <= m03_couplers_to_axi_interconnect_0_BREADY;
+  M03_AXI_rready <= m03_couplers_to_axi_interconnect_0_RREADY;
+  M03_AXI_wdata(31 downto 0) <= m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M03_AXI_wvalid <= m03_couplers_to_axi_interconnect_0_WVALID;
+  M04_ACLK_1 <= M04_ACLK;
+  M04_ARESETN_1 <= M04_ARESETN;
+  M04_AXI_araddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M04_AXI_arvalid <= m04_couplers_to_axi_interconnect_0_ARVALID;
+  M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M04_AXI_awvalid <= m04_couplers_to_axi_interconnect_0_AWVALID;
+  M04_AXI_bready <= m04_couplers_to_axi_interconnect_0_BREADY;
+  M04_AXI_rready <= m04_couplers_to_axi_interconnect_0_RREADY;
+  M04_AXI_wdata(31 downto 0) <= m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M04_AXI_wvalid <= m04_couplers_to_axi_interconnect_0_WVALID;
+  S00_ACLK_1 <= S00_ACLK;
+  S00_ARESETN_1 <= S00_ARESETN;
+  S00_AXI_arready(0) <= axi_interconnect_0_to_s00_couplers_ARREADY(0);
+  S00_AXI_awready(0) <= axi_interconnect_0_to_s00_couplers_AWREADY(0);
+  S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
+  S00_AXI_bvalid(0) <= axi_interconnect_0_to_s00_couplers_BVALID(0);
+  S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
+  S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
+  S00_AXI_rvalid(0) <= axi_interconnect_0_to_s00_couplers_RVALID(0);
+  S00_AXI_wready(0) <= axi_interconnect_0_to_s00_couplers_WREADY(0);
+  axi_interconnect_0_ACLK_net <= ACLK;
+  axi_interconnect_0_ARESETN_net <= ARESETN;
+  axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
+  axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
+  axi_interconnect_0_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
+  axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
+  axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
+  axi_interconnect_0_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
+  axi_interconnect_0_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
+  axi_interconnect_0_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
+  axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
+  axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
+  axi_interconnect_0_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
+  m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
+  m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
+  m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
+  m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
+  m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
+  m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
+  m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
+  m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
+  m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
+  m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
+  m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
+  m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
+  m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
+  m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
+  m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
+  m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
+  m02_couplers_to_axi_interconnect_0_ARREADY <= M02_AXI_arready;
+  m02_couplers_to_axi_interconnect_0_AWREADY <= M02_AXI_awready;
+  m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
+  m02_couplers_to_axi_interconnect_0_BVALID <= M02_AXI_bvalid;
+  m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
+  m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
+  m02_couplers_to_axi_interconnect_0_RVALID <= M02_AXI_rvalid;
+  m02_couplers_to_axi_interconnect_0_WREADY <= M02_AXI_wready;
+  m03_couplers_to_axi_interconnect_0_ARREADY <= M03_AXI_arready;
+  m03_couplers_to_axi_interconnect_0_AWREADY <= M03_AXI_awready;
+  m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
+  m03_couplers_to_axi_interconnect_0_BVALID <= M03_AXI_bvalid;
+  m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
+  m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
+  m03_couplers_to_axi_interconnect_0_RVALID <= M03_AXI_rvalid;
+  m03_couplers_to_axi_interconnect_0_WREADY <= M03_AXI_wready;
+  m04_couplers_to_axi_interconnect_0_ARREADY <= M04_AXI_arready;
+  m04_couplers_to_axi_interconnect_0_AWREADY <= M04_AXI_awready;
+  m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
+  m04_couplers_to_axi_interconnect_0_BVALID <= M04_AXI_bvalid;
+  m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
+  m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
+  m04_couplers_to_axi_interconnect_0_RVALID <= M04_AXI_rvalid;
+  m04_couplers_to_axi_interconnect_0_WREADY <= M04_AXI_wready;
+m00_couplers: entity work.m00_couplers_imp_L30N86
+     port map (
+      M_ACLK => M00_ACLK_1,
+      M_ARESETN => M00_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
+      S_AXI_arready => xbar_to_m00_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
+      S_AXI_awready => xbar_to_m00_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
+      S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
+      S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
+      S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
+      S_AXI_wready => xbar_to_m00_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
+      S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
+    );
+m01_couplers: entity work.m01_couplers_imp_1MV3QBS
+     port map (
+      M_ACLK => M01_ACLK_1,
+      M_ARESETN => M01_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
+      S_AXI_arready => xbar_to_m01_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
+      S_AXI_awready => xbar_to_m01_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
+      S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
+      S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
+      S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
+      S_AXI_wready => xbar_to_m01_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
+      S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
+    );
+m02_couplers: entity work.m02_couplers_imp_1CM8QGB
+     port map (
+      M_ACLK => M02_ACLK_1,
+      M_ARESETN => M02_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m02_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m02_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m02_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m02_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m02_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m02_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m02_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m02_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m02_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m02_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
+      S_AXI_arready => xbar_to_m02_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
+      S_AXI_awready => xbar_to_m02_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
+      S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
+      S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
+      S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
+      S_AXI_wready => xbar_to_m02_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
+      S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
+    );
+m03_couplers: entity work.m03_couplers_imp_DKAE7P
+     port map (
+      M_ACLK => M03_ACLK_1,
+      M_ARESETN => M03_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m03_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m03_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m03_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m03_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m03_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m03_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m03_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m03_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m03_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m03_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
+      S_AXI_arready => xbar_to_m03_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
+      S_AXI_awready => xbar_to_m03_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
+      S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
+      S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
+      S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
+      S_AXI_wready => xbar_to_m03_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
+      S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
+    );
+m04_couplers: entity work.m04_couplers_imp_OP7ZFX
+     port map (
+      M_ACLK => M04_ACLK_1,
+      M_ARESETN => M04_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m04_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m04_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m04_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m04_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m04_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m04_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m04_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m04_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m04_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m04_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
+      S_AXI_arready => xbar_to_m04_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
+      S_AXI_awready => xbar_to_m04_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
+      S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
+      S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
+      S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
+      S_AXI_wready => xbar_to_m04_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
+      S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
+    );
+s00_couplers: entity work.s00_couplers_imp_1AM08ZQ
+     port map (
+      M_ACLK => axi_interconnect_0_ACLK_net,
+      M_ARESETN => axi_interconnect_0_ARESETN_net,
+      M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
+      M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
+      M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
+      M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
+      M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
+      M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
+      M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
+      M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
+      M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
+      M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
+      M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
+      M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
+      M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
+      M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
+      M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
+      M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
+      M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
+      M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
+      M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
+      S_ACLK => S00_ACLK_1,
+      S_ARESETN => S00_ARESETN_1,
+      S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
+      S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
+      S_AXI_arready(0) => axi_interconnect_0_to_s00_couplers_ARREADY(0),
+      S_AXI_arvalid(0) => axi_interconnect_0_to_s00_couplers_ARVALID(0),
+      S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
+      S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
+      S_AXI_awready(0) => axi_interconnect_0_to_s00_couplers_AWREADY(0),
+      S_AXI_awvalid(0) => axi_interconnect_0_to_s00_couplers_AWVALID(0),
+      S_AXI_bready(0) => axi_interconnect_0_to_s00_couplers_BREADY(0),
+      S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid(0) => axi_interconnect_0_to_s00_couplers_BVALID(0),
+      S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
+      S_AXI_rready(0) => axi_interconnect_0_to_s00_couplers_RREADY(0),
+      S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid(0) => axi_interconnect_0_to_s00_couplers_RVALID(0),
+      S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
+      S_AXI_wready(0) => axi_interconnect_0_to_s00_couplers_WREADY(0),
+      S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
+      S_AXI_wvalid(0) => axi_interconnect_0_to_s00_couplers_WVALID(0)
+    );
+xbar: component mb_design_1_xbar_0
+     port map (
+      aclk => axi_interconnect_0_ACLK_net,
+      aresetn => axi_interconnect_0_ARESETN_net,
+      m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
+      m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
+      m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
+      m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
+      m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
+      m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0),
+      m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
+      m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
+      m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
+      m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
+      m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
+      m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
+      m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
+      m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
+      m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
+      m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
+      m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
+      m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
+      m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
+      m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
+      m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
+      m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0),
+      m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
+      m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
+      m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
+      m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
+      m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
+      m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
+      m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
+      m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
+      m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
+      m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
+      m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
+      m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
+      m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
+      m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
+      m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
+      m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
+      m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
+      m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
+      m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
+      m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
+      m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
+      m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
+      m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
+      m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
+      m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
+      m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
+      m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
+      m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
+      m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
+      m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
+      m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
+      m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
+      m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
+      m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
+      m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
+      m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
+      m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
+      m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
+      m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
+      m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
+      m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
+      m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
+      m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
+      m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
+      m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
+      m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
+      m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
+      m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
+      m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
+      m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
+      m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
+      m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
+      m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
+      m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
+      m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
+      m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
+      m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
+      m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
+      m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
+      m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
+      m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
+      m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
+      m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
+      m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
+      m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
+      s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
+      s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
+      s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
+      s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
+      s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
+      s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
+      s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
+      s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
+      s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
+      s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
+      s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
+      s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
+      s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
+      s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
+      s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
+      s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
+      s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
+      s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
+      s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1 is
+  port (
+    GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_in1 : in STD_LOGIC;
+    hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    reset : in STD_LOGIC
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=15,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of mb_design_1 : entity is "mb_design_1.hwdef";
+end mb_design_1;
+
+architecture STRUCTURE of mb_design_1 is
+  component mb_design_1_microblaze_0_0 is
+  port (
+    Clk : in STD_LOGIC;
+    Reset : in STD_LOGIC;
+    Interrupt : in STD_LOGIC;
+    Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
+    Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
+    IFetch : out STD_LOGIC;
+    I_AS : out STD_LOGIC;
+    IReady : in STD_LOGIC;
+    IWAIT : in STD_LOGIC;
+    ICE : in STD_LOGIC;
+    IUE : in STD_LOGIC;
+    Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
+    D_AS : out STD_LOGIC;
+    Read_Strobe : out STD_LOGIC;
+    Write_Strobe : out STD_LOGIC;
+    DReady : in STD_LOGIC;
+    DWait : in STD_LOGIC;
+    DCE : in STD_LOGIC;
+    DUE : in STD_LOGIC;
+    Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
+    M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_DP_AWVALID : out STD_LOGIC;
+    M_AXI_DP_AWREADY : in STD_LOGIC;
+    M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_DP_WVALID : out STD_LOGIC;
+    M_AXI_DP_WREADY : in STD_LOGIC;
+    M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_DP_BVALID : in STD_LOGIC;
+    M_AXI_DP_BREADY : out STD_LOGIC;
+    M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_DP_ARVALID : out STD_LOGIC;
+    M_AXI_DP_ARREADY : in STD_LOGIC;
+    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_DP_RVALID : in STD_LOGIC;
+    M_AXI_DP_RREADY : out STD_LOGIC;
+    Dbg_Clk : in STD_LOGIC;
+    Dbg_TDI : in STD_LOGIC;
+    Dbg_TDO : out STD_LOGIC;
+    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
+    Dbg_Shift : in STD_LOGIC;
+    Dbg_Capture : in STD_LOGIC;
+    Dbg_Update : in STD_LOGIC;
+    Debug_Rst : in STD_LOGIC;
+    Dbg_Disable : in STD_LOGIC
+  );
+  end component mb_design_1_microblaze_0_0;
+  component mb_design_1_clk_wiz_0_0 is
+  port (
+    reset : in STD_LOGIC;
+    clk_in1 : in STD_LOGIC;
+    clk_100mhz : out STD_LOGIC;
+    locked : out STD_LOGIC
+  );
+  end component mb_design_1_clk_wiz_0_0;
+  component mb_design_1_proc_sys_reset_0_0 is
+  port (
+    slowest_sync_clk : in STD_LOGIC;
+    ext_reset_in : in STD_LOGIC;
+    aux_reset_in : in STD_LOGIC;
+    mb_debug_sys_rst : in STD_LOGIC;
+    dcm_locked : in STD_LOGIC;
+    mb_reset : out STD_LOGIC;
+    bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
+    peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
+    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component mb_design_1_proc_sys_reset_0_0;
+  component mb_design_1_lmb_v10_0_0 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    SYS_Rst : in STD_LOGIC;
+    LMB_Rst : out STD_LOGIC;
+    M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_ReadStrobe : in STD_LOGIC;
+    M_WriteStrobe : in STD_LOGIC;
+    M_AddrStrobe : in STD_LOGIC;
+    M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_ReadStrobe : out STD_LOGIC;
+    LMB_WriteStrobe : out STD_LOGIC;
+    LMB_AddrStrobe : out STD_LOGIC;
+    LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_Ready : out STD_LOGIC;
+    LMB_Wait : out STD_LOGIC;
+    LMB_UE : out STD_LOGIC;
+    LMB_CE : out STD_LOGIC;
+    LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
+  );
+  end component mb_design_1_lmb_v10_0_0;
+  component mb_design_1_ilmb_v10_0_0 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    SYS_Rst : in STD_LOGIC;
+    LMB_Rst : out STD_LOGIC;
+    M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_ReadStrobe : in STD_LOGIC;
+    M_WriteStrobe : in STD_LOGIC;
+    M_AddrStrobe : in STD_LOGIC;
+    M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_ReadStrobe : out STD_LOGIC;
+    LMB_WriteStrobe : out STD_LOGIC;
+    LMB_AddrStrobe : out STD_LOGIC;
+    LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_Ready : out STD_LOGIC;
+    LMB_Wait : out STD_LOGIC;
+    LMB_UE : out STD_LOGIC;
+    LMB_CE : out STD_LOGIC;
+    LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
+  );
+  end component mb_design_1_ilmb_v10_0_0;
+  component mb_design_1_lmb_bram_if_cntlr_0_0 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    LMB_Rst : in STD_LOGIC;
+    LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_AddrStrobe : in STD_LOGIC;
+    LMB_ReadStrobe : in STD_LOGIC;
+    LMB_WriteStrobe : in STD_LOGIC;
+    LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : out STD_LOGIC;
+    Sl_Wait : out STD_LOGIC;
+    Sl_UE : out STD_LOGIC;
+    Sl_CE : out STD_LOGIC;
+    BRAM_Rst_A : out STD_LOGIC;
+    BRAM_Clk_A : out STD_LOGIC;
+    BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_EN_A : out STD_LOGIC;
+    BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
+    BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
+  );
+  end component mb_design_1_lmb_bram_if_cntlr_0_0;
+  component mb_design_1_lmb_bram_if_cntlr_0_1 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    LMB_Rst : in STD_LOGIC;
+    LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_AddrStrobe : in STD_LOGIC;
+    LMB_ReadStrobe : in STD_LOGIC;
+    LMB_WriteStrobe : in STD_LOGIC;
+    LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : out STD_LOGIC;
+    Sl_Wait : out STD_LOGIC;
+    Sl_UE : out STD_LOGIC;
+    Sl_CE : out STD_LOGIC;
+    BRAM_Rst_A : out STD_LOGIC;
+    BRAM_Clk_A : out STD_LOGIC;
+    BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_EN_A : out STD_LOGIC;
+    BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
+    BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
+  );
+  end component mb_design_1_lmb_bram_if_cntlr_0_1;
+  component mb_design_1_blk_mem_gen_0_0 is
+  port (
+    clka : in STD_LOGIC;
+    rsta : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clkb : in STD_LOGIC;
+    rstb : in STD_LOGIC;
+    enb : in STD_LOGIC;
+    web : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    rsta_busy : out STD_LOGIC;
+    rstb_busy : out STD_LOGIC
+  );
+  end component mb_design_1_blk_mem_gen_0_0;
+  component mb_design_1_mdm_0_0 is
+  port (
+    S_AXI_ACLK : in STD_LOGIC;
+    S_AXI_ARESETN : in STD_LOGIC;
+    Interrupt : out STD_LOGIC;
+    Debug_SYS_Rst : out STD_LOGIC;
+    S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_AWVALID : in STD_LOGIC;
+    S_AXI_AWREADY : out STD_LOGIC;
+    S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_WVALID : in STD_LOGIC;
+    S_AXI_WREADY : out STD_LOGIC;
+    S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_BVALID : out STD_LOGIC;
+    S_AXI_BREADY : in STD_LOGIC;
+    S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_ARVALID : in STD_LOGIC;
+    S_AXI_ARREADY : out STD_LOGIC;
+    S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_RVALID : out STD_LOGIC;
+    S_AXI_RREADY : in STD_LOGIC;
+    Dbg_Clk_0 : out STD_LOGIC;
+    Dbg_TDI_0 : out STD_LOGIC;
+    Dbg_TDO_0 : in STD_LOGIC;
+    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
+    Dbg_Capture_0 : out STD_LOGIC;
+    Dbg_Shift_0 : out STD_LOGIC;
+    Dbg_Update_0 : out STD_LOGIC;
+    Dbg_Rst_0 : out STD_LOGIC;
+    Dbg_Disable_0 : out STD_LOGIC
+  );
+  end component mb_design_1_mdm_0_0;
+  component mb_design_1_axi_gpio_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component mb_design_1_axi_gpio_0_0;
+  component mb_design_1_axi_timer_0_0 is
+  port (
+    capturetrig0 : in STD_LOGIC;
+    capturetrig1 : in STD_LOGIC;
+    generateout0 : out STD_LOGIC;
+    generateout1 : out STD_LOGIC;
+    pwm0 : out STD_LOGIC;
+    interrupt : out STD_LOGIC;
+    freeze : in STD_LOGIC;
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC
+  );
+  end component mb_design_1_axi_timer_0_0;
+  component mb_design_1_axi_intc_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    intr : in STD_LOGIC_VECTOR ( 0 to 0 );
+    irq : out STD_LOGIC
+  );
+  end component mb_design_1_axi_intc_0_0;
+  component mb_design_1_xlconcat_0_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component mb_design_1_xlconcat_0_0;
+  component mb_design_1_axi4lite_hog_build_i_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+  end component mb_design_1_axi4lite_hog_build_i_0_0;
+  signal Conn1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn1_ADDRSTROBE : STD_LOGIC;
+  signal Conn1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal Conn1_CE : STD_LOGIC;
+  signal Conn1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn1_READSTROBE : STD_LOGIC;
+  signal Conn1_READY : STD_LOGIC;
+  signal Conn1_UE : STD_LOGIC;
+  signal Conn1_WAIT : STD_LOGIC;
+  signal Conn1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn1_WRITESTROBE : STD_LOGIC;
+  signal Conn_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn_ADDRSTROBE : STD_LOGIC;
+  signal Conn_BE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal Conn_CE : STD_LOGIC;
+  signal Conn_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn_READSTROBE : STD_LOGIC;
+  signal Conn_READY : STD_LOGIC;
+  signal Conn_UE : STD_LOGIC;
+  signal Conn_WAIT : STD_LOGIC;
+  signal Conn_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn_WRITESTROBE : STD_LOGIC;
+  signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal S00_AXI_1_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_ARVALID : STD_LOGIC;
+  signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal S00_AXI_1_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_AWVALID : STD_LOGIC;
+  signal S00_AXI_1_BREADY : STD_LOGIC;
+  signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal S00_AXI_1_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_RREADY : STD_LOGIC;
+  signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal S00_AXI_1_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal S00_AXI_1_WVALID : STD_LOGIC;
+  signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal axi_intc_0_interrupt_INTERRUPT : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
+  signal axi_timer_0_interrupt : STD_LOGIC;
+  signal clk_in1_0_1 : STD_LOGIC;
+  signal clk_wiz_0_clk_100mhz : STD_LOGIC;
+  signal clk_wiz_0_locked : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal hog_global_date_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal hog_global_sha_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal hog_global_time_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal hog_global_ver_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal mdm_0_Debug_SYS_Rst : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_CAPTURE : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_CLK : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_DISABLE : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
+  signal mdm_0_MBDEBUG_0_RST : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_SHIFT : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_TDI : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_TDO : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_UPDATE : STD_LOGIC;
+  signal microblaze_0_DLMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_DLMB_ADDRSTROBE : STD_LOGIC;
+  signal microblaze_0_DLMB_BE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal microblaze_0_DLMB_CE : STD_LOGIC;
+  signal microblaze_0_DLMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_DLMB_READSTROBE : STD_LOGIC;
+  signal microblaze_0_DLMB_READY : STD_LOGIC;
+  signal microblaze_0_DLMB_UE : STD_LOGIC;
+  signal microblaze_0_DLMB_WAIT : STD_LOGIC;
+  signal microblaze_0_DLMB_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_DLMB_WRITESTROBE : STD_LOGIC;
+  signal microblaze_0_ILMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_ILMB_ADDRSTROBE : STD_LOGIC;
+  signal microblaze_0_ILMB_CE : STD_LOGIC;
+  signal microblaze_0_ILMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_ILMB_READSTROBE : STD_LOGIC;
+  signal microblaze_0_ILMB_READY : STD_LOGIC;
+  signal microblaze_0_ILMB_UE : STD_LOGIC;
+  signal microblaze_0_ILMB_WAIT : STD_LOGIC;
+  signal proc_sys_reset_0_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal proc_sys_reset_0_mb_reset : STD_LOGIC;
+  signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal reset_0_1 : STD_LOGIC;
+  signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
+  signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
+  signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
+  signal NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
+  signal NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
+  signal NLW_mdm_0_Interrupt_UNCONNECTED : STD_LOGIC;
+  signal NLW_microblaze_0_Interrupt_Ack_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 1 );
+  signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+  attribute BMM_INFO_ADDRESS_SPACE : string;
+  attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr_0 : label is "byte  0x00000000 32 > mb_design_1 blk_mem_gen_0";
+  attribute KEEP_HIERARCHY : string;
+  attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr_0 : label is "yes";
+  attribute BMM_INFO_PROCESSOR : string;
+  attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > mb_design_1 dlmb_bram_if_cntlr_0";
+  attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of clk_in1 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_IN1 CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk_in1 : signal is "XIL_INTERFACENAME CLK.CLK_IN1, ASSOCIATED_RESET reset, CLK_DOMAIN mb_design_1_clk_in1_0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
+  attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 RST.RESET RST";
+  attribute X_INTERFACE_PARAMETER of reset : signal is "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
+  attribute X_INTERFACE_INFO of GPIO_0_tri_o : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O";
+begin
+  GPIO_0_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
+  clk_in1_0_1 <= clk_in1;
+  hog_global_date_i_0_1(31 downto 0) <= hog_global_date_i_0(31 downto 0);
+  hog_global_sha_i_0_1(31 downto 0) <= hog_global_sha_i_0(31 downto 0);
+  hog_global_time_i_0_1(31 downto 0) <= hog_global_time_i_0(31 downto 0);
+  hog_global_ver_i_0_1(31 downto 0) <= hog_global_ver_i_0(31 downto 0);
+  reset_0_1 <= reset;
+axi4lite_hog_build_i_0: component mb_design_1_axi4lite_hog_build_i_0_0
+     port map (
+      hog_global_date_i(31 downto 0) => hog_global_date_i_0_1(31 downto 0),
+      hog_global_sha_i(31 downto 0) => hog_global_sha_i_0_1(31 downto 0),
+      hog_global_time_i(31 downto 0) => hog_global_time_i_0_1(31 downto 0),
+      hog_global_ver_i(31 downto 0) => hog_global_ver_i_0_1(31 downto 0),
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M04_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+      s_axi_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+      s_axi_awready => axi_interconnect_0_M04_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M04_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M04_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M04_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M04_AXI_WVALID
+    );
+axi_gpio_0: component mb_design_1_axi_gpio_0_0
+     port map (
+      gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
+      s_axi_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
+      s_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
+    );
+axi_intc_0: component mb_design_1_axi_intc_0_0
+     port map (
+      intr(0) => xlconcat_0_dout(0),
+      irq => axi_intc_0_interrupt_INTERRUPT,
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(8 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(8 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+      s_axi_awaddr(8 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(8 downto 0),
+      s_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
+    );
+axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
+     port map (
+      ACLK => clk_wiz_0_clk_100mhz,
+      ARESETN => proc_sys_reset_0_interconnect_aresetn(0),
+      M00_ACLK => clk_wiz_0_clk_100mhz,
+      M00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
+      M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
+      M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
+      M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
+      M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
+      M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
+      M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
+      M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
+      M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
+      M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
+      M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
+      M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
+      M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
+      M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
+      M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
+      M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
+      M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
+      M01_ACLK => clk_wiz_0_clk_100mhz,
+      M01_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
+      M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
+      M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
+      M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
+      M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
+      M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
+      M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
+      M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
+      M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
+      M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
+      M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
+      M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
+      M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
+      M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
+      M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
+      M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
+      M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
+      M02_ACLK => clk_wiz_0_clk_100mhz,
+      M02_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
+      M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
+      M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
+      M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
+      M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
+      M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
+      M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
+      M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
+      M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
+      M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
+      M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
+      M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
+      M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
+      M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
+      M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
+      M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
+      M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
+      M03_ACLK => clk_wiz_0_clk_100mhz,
+      M03_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
+      M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
+      M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+      M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
+      M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
+      M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+      M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
+      M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+      M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+      M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+      M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
+      M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+      M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+      M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+      M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
+      M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+      M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
+      M04_ACLK => clk_wiz_0_clk_100mhz,
+      M04_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+      M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
+      M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+      M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+      M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
+      M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+      M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
+      M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+      M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+      M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+      M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
+      M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+      M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+      M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+      M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
+      M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+      M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
+      S00_ACLK => clk_wiz_0_clk_100mhz,
+      S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
+      S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
+      S00_AXI_arready(0) => S00_AXI_1_ARREADY(0),
+      S00_AXI_arvalid(0) => S00_AXI_1_ARVALID,
+      S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
+      S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
+      S00_AXI_awready(0) => S00_AXI_1_AWREADY(0),
+      S00_AXI_awvalid(0) => S00_AXI_1_AWVALID,
+      S00_AXI_bready(0) => S00_AXI_1_BREADY,
+      S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
+      S00_AXI_bvalid(0) => S00_AXI_1_BVALID(0),
+      S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
+      S00_AXI_rready(0) => S00_AXI_1_RREADY,
+      S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
+      S00_AXI_rvalid(0) => S00_AXI_1_RVALID(0),
+      S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
+      S00_AXI_wready(0) => S00_AXI_1_WREADY(0),
+      S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
+      S00_AXI_wvalid(0) => S00_AXI_1_WVALID
+    );
+axi_timer_0: component mb_design_1_axi_timer_0_0
+     port map (
+      capturetrig0 => '0',
+      capturetrig1 => '0',
+      freeze => '0',
+      generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
+      generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
+      interrupt => axi_timer_0_interrupt,
+      pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(4 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(4 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
+      s_axi_awaddr(4 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(4 downto 0),
+      s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
+    );
+blk_mem_gen_0: component mb_design_1_blk_mem_gen_0_0
+     port map (
+      addra(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
+      addra(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
+      addra(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
+      addra(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
+      addra(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
+      addra(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
+      addra(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
+      addra(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
+      addra(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
+      addra(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
+      addra(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
+      addra(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
+      addra(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
+      addra(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
+      addra(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
+      addra(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
+      addra(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
+      addra(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
+      addra(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
+      addra(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
+      addra(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
+      addra(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
+      addra(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
+      addra(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
+      addra(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
+      addra(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
+      addra(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
+      addra(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
+      addra(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
+      addra(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
+      addra(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
+      addra(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
+      addrb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
+      addrb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
+      addrb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
+      addrb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
+      addrb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
+      addrb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
+      addrb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
+      addrb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
+      addrb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
+      addrb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
+      addrb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
+      addrb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
+      addrb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
+      addrb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
+      addrb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
+      addrb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
+      addrb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
+      addrb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
+      addrb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
+      addrb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
+      addrb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
+      addrb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
+      addrb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
+      addrb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
+      addrb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
+      addrb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
+      addrb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
+      addrb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
+      addrb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
+      addrb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
+      addrb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
+      addrb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
+      clka => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      clkb => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      dina(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
+      dina(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
+      dina(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
+      dina(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
+      dina(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
+      dina(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
+      dina(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
+      dina(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
+      dina(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
+      dina(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
+      dina(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
+      dina(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
+      dina(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
+      dina(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
+      dina(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
+      dina(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
+      dina(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
+      dina(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
+      dina(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
+      dina(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
+      dina(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
+      dina(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
+      dina(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
+      dina(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
+      dina(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
+      dina(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
+      dina(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
+      dina(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
+      dina(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
+      dina(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
+      dina(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
+      dina(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
+      dinb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
+      dinb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
+      dinb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
+      dinb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
+      dinb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
+      dinb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
+      dinb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
+      dinb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
+      dinb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
+      dinb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
+      dinb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
+      dinb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
+      dinb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
+      dinb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
+      dinb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
+      dinb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
+      dinb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
+      dinb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
+      dinb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
+      dinb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
+      dinb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
+      dinb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
+      dinb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
+      dinb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
+      dinb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
+      dinb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
+      dinb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
+      dinb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
+      dinb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
+      dinb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
+      dinb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
+      dinb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
+      douta(31 downto 0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
+      doutb(31 downto 0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
+      ena => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      enb => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      rsta => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      rsta_busy => NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED,
+      rstb => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      rstb_busy => NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED,
+      wea(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
+      wea(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
+      wea(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
+      wea(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(3),
+      web(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
+      web(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
+      web(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
+      web(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(3)
+    );
+clk_wiz_0: component mb_design_1_clk_wiz_0_0
+     port map (
+      clk_100mhz => clk_wiz_0_clk_100mhz,
+      clk_in1 => clk_in1_0_1,
+      locked => clk_wiz_0_locked,
+      reset => reset_0_1
+    );
+dlmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_0
+     port map (
+      BRAM_Addr_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
+      BRAM_Clk_A => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      BRAM_Din_A(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
+      BRAM_Din_A(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
+      BRAM_Din_A(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
+      BRAM_Din_A(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
+      BRAM_Din_A(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
+      BRAM_Din_A(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
+      BRAM_Din_A(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
+      BRAM_Din_A(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
+      BRAM_Din_A(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
+      BRAM_Din_A(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
+      BRAM_Din_A(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
+      BRAM_Din_A(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
+      BRAM_Din_A(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
+      BRAM_Din_A(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
+      BRAM_Din_A(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
+      BRAM_Din_A(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
+      BRAM_Din_A(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
+      BRAM_Din_A(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
+      BRAM_Din_A(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
+      BRAM_Din_A(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
+      BRAM_Din_A(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
+      BRAM_Din_A(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
+      BRAM_Din_A(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
+      BRAM_Din_A(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
+      BRAM_Din_A(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
+      BRAM_Din_A(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
+      BRAM_Din_A(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
+      BRAM_Din_A(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
+      BRAM_Din_A(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
+      BRAM_Din_A(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
+      BRAM_Din_A(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
+      BRAM_Din_A(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
+      BRAM_Dout_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
+      BRAM_EN_A => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      BRAM_Rst_A => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      BRAM_WEN_A(0 to 3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
+      LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn1_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn1_BE(0 to 3),
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadStrobe => Conn1_READSTROBE,
+      LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn1_WRITESTROBE,
+      Sl_CE => Conn1_CE,
+      Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
+      Sl_Ready => Conn1_READY,
+      Sl_UE => Conn1_UE,
+      Sl_Wait => Conn1_WAIT
+    );
+dlmb_v10_0: component mb_design_1_ilmb_v10_0_0
+     port map (
+      LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn1_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn1_BE(0 to 3),
+      LMB_CE => microblaze_0_DLMB_CE,
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadDBus(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
+      LMB_ReadStrobe => Conn1_READSTROBE,
+      LMB_Ready => microblaze_0_DLMB_READY,
+      LMB_Rst => NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED,
+      LMB_UE => microblaze_0_DLMB_UE,
+      LMB_Wait => microblaze_0_DLMB_WAIT,
+      LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn1_WRITESTROBE,
+      M_ABus(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
+      M_AddrStrobe => microblaze_0_DLMB_ADDRSTROBE,
+      M_BE(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
+      M_DBus(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
+      M_ReadStrobe => microblaze_0_DLMB_READSTROBE,
+      M_WriteStrobe => microblaze_0_DLMB_WRITESTROBE,
+      SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      Sl_CE(0) => Conn1_CE,
+      Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
+      Sl_Ready(0) => Conn1_READY,
+      Sl_UE(0) => Conn1_UE,
+      Sl_Wait(0) => Conn1_WAIT
+    );
+ilmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_1
+     port map (
+      BRAM_Addr_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
+      BRAM_Clk_A => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      BRAM_Din_A(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
+      BRAM_Din_A(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
+      BRAM_Din_A(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
+      BRAM_Din_A(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
+      BRAM_Din_A(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
+      BRAM_Din_A(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
+      BRAM_Din_A(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
+      BRAM_Din_A(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
+      BRAM_Din_A(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
+      BRAM_Din_A(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
+      BRAM_Din_A(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
+      BRAM_Din_A(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
+      BRAM_Din_A(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
+      BRAM_Din_A(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
+      BRAM_Din_A(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
+      BRAM_Din_A(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
+      BRAM_Din_A(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
+      BRAM_Din_A(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
+      BRAM_Din_A(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
+      BRAM_Din_A(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
+      BRAM_Din_A(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
+      BRAM_Din_A(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
+      BRAM_Din_A(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
+      BRAM_Din_A(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
+      BRAM_Din_A(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
+      BRAM_Din_A(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
+      BRAM_Din_A(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
+      BRAM_Din_A(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
+      BRAM_Din_A(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
+      BRAM_Din_A(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
+      BRAM_Din_A(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
+      BRAM_Din_A(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
+      BRAM_Dout_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
+      BRAM_EN_A => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      BRAM_Rst_A => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      BRAM_WEN_A(0 to 3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
+      LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn_BE(0 to 3),
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadStrobe => Conn_READSTROBE,
+      LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn_WRITESTROBE,
+      Sl_CE => Conn_CE,
+      Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
+      Sl_Ready => Conn_READY,
+      Sl_UE => Conn_UE,
+      Sl_Wait => Conn_WAIT
+    );
+ilmb_v10_0: component mb_design_1_lmb_v10_0_0
+     port map (
+      LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn_BE(0 to 3),
+      LMB_CE => microblaze_0_ILMB_CE,
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadDBus(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
+      LMB_ReadStrobe => Conn_READSTROBE,
+      LMB_Ready => microblaze_0_ILMB_READY,
+      LMB_Rst => NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED,
+      LMB_UE => microblaze_0_ILMB_UE,
+      LMB_Wait => microblaze_0_ILMB_WAIT,
+      LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn_WRITESTROBE,
+      M_ABus(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
+      M_AddrStrobe => microblaze_0_ILMB_ADDRSTROBE,
+      M_BE(0 to 3) => B"0000",
+      M_DBus(0 to 31) => B"00000000000000000000000000000000",
+      M_ReadStrobe => microblaze_0_ILMB_READSTROBE,
+      M_WriteStrobe => '0',
+      SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      Sl_CE(0) => Conn_CE,
+      Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
+      Sl_Ready(0) => Conn_READY,
+      Sl_UE(0) => Conn_UE,
+      Sl_Wait(0) => Conn_WAIT
+    );
+mdm_0: component mb_design_1_mdm_0_0
+     port map (
+      Dbg_Capture_0 => mdm_0_MBDEBUG_0_CAPTURE,
+      Dbg_Clk_0 => mdm_0_MBDEBUG_0_CLK,
+      Dbg_Disable_0 => mdm_0_MBDEBUG_0_DISABLE,
+      Dbg_Reg_En_0(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
+      Dbg_Rst_0 => mdm_0_MBDEBUG_0_RST,
+      Dbg_Shift_0 => mdm_0_MBDEBUG_0_SHIFT,
+      Dbg_TDI_0 => mdm_0_MBDEBUG_0_TDI,
+      Dbg_TDO_0 => mdm_0_MBDEBUG_0_TDO,
+      Dbg_Update_0 => mdm_0_MBDEBUG_0_UPDATE,
+      Debug_SYS_Rst => mdm_0_Debug_SYS_Rst,
+      Interrupt => NLW_mdm_0_Interrupt_UNCONNECTED,
+      S_AXI_ACLK => clk_wiz_0_clk_100mhz,
+      S_AXI_ARADDR(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
+      S_AXI_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      S_AXI_ARREADY => axi_interconnect_0_M00_AXI_ARREADY,
+      S_AXI_ARVALID => axi_interconnect_0_M00_AXI_ARVALID,
+      S_AXI_AWADDR(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
+      S_AXI_AWREADY => axi_interconnect_0_M00_AXI_AWREADY,
+      S_AXI_AWVALID => axi_interconnect_0_M00_AXI_AWVALID,
+      S_AXI_BREADY => axi_interconnect_0_M00_AXI_BREADY,
+      S_AXI_BRESP(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
+      S_AXI_BVALID => axi_interconnect_0_M00_AXI_BVALID,
+      S_AXI_RDATA(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
+      S_AXI_RREADY => axi_interconnect_0_M00_AXI_RREADY,
+      S_AXI_RRESP(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
+      S_AXI_RVALID => axi_interconnect_0_M00_AXI_RVALID,
+      S_AXI_WDATA(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
+      S_AXI_WREADY => axi_interconnect_0_M00_AXI_WREADY,
+      S_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
+      S_AXI_WVALID => axi_interconnect_0_M00_AXI_WVALID
+    );
+microblaze_0: component mb_design_1_microblaze_0_0
+     port map (
+      Byte_Enable(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
+      Clk => clk_wiz_0_clk_100mhz,
+      DCE => microblaze_0_DLMB_CE,
+      DReady => microblaze_0_DLMB_READY,
+      DUE => microblaze_0_DLMB_UE,
+      DWait => microblaze_0_DLMB_WAIT,
+      D_AS => microblaze_0_DLMB_ADDRSTROBE,
+      Data_Addr(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
+      Data_Read(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
+      Data_Write(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
+      Dbg_Capture => mdm_0_MBDEBUG_0_CAPTURE,
+      Dbg_Clk => mdm_0_MBDEBUG_0_CLK,
+      Dbg_Disable => mdm_0_MBDEBUG_0_DISABLE,
+      Dbg_Reg_En(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
+      Dbg_Shift => mdm_0_MBDEBUG_0_SHIFT,
+      Dbg_TDI => mdm_0_MBDEBUG_0_TDI,
+      Dbg_TDO => mdm_0_MBDEBUG_0_TDO,
+      Dbg_Update => mdm_0_MBDEBUG_0_UPDATE,
+      Debug_Rst => mdm_0_MBDEBUG_0_RST,
+      ICE => microblaze_0_ILMB_CE,
+      IFetch => microblaze_0_ILMB_READSTROBE,
+      IReady => microblaze_0_ILMB_READY,
+      IUE => microblaze_0_ILMB_UE,
+      IWAIT => microblaze_0_ILMB_WAIT,
+      I_AS => microblaze_0_ILMB_ADDRSTROBE,
+      Instr(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
+      Instr_Addr(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
+      Interrupt => axi_intc_0_interrupt_INTERRUPT,
+      Interrupt_Ack(0 to 1) => NLW_microblaze_0_Interrupt_Ack_UNCONNECTED(0 to 1),
+      Interrupt_Address(0 to 31) => B"00000000000000000000000000000000",
+      M_AXI_DP_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
+      M_AXI_DP_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
+      M_AXI_DP_ARREADY => S00_AXI_1_ARREADY(0),
+      M_AXI_DP_ARVALID => S00_AXI_1_ARVALID,
+      M_AXI_DP_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
+      M_AXI_DP_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
+      M_AXI_DP_AWREADY => S00_AXI_1_AWREADY(0),
+      M_AXI_DP_AWVALID => S00_AXI_1_AWVALID,
+      M_AXI_DP_BREADY => S00_AXI_1_BREADY,
+      M_AXI_DP_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
+      M_AXI_DP_BVALID => S00_AXI_1_BVALID(0),
+      M_AXI_DP_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
+      M_AXI_DP_RREADY => S00_AXI_1_RREADY,
+      M_AXI_DP_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
+      M_AXI_DP_RVALID => S00_AXI_1_RVALID(0),
+      M_AXI_DP_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
+      M_AXI_DP_WREADY => S00_AXI_1_WREADY(0),
+      M_AXI_DP_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
+      M_AXI_DP_WVALID => S00_AXI_1_WVALID,
+      Read_Strobe => microblaze_0_DLMB_READSTROBE,
+      Reset => proc_sys_reset_0_mb_reset,
+      Write_Strobe => microblaze_0_DLMB_WRITESTROBE
+    );
+proc_sys_reset_0: component mb_design_1_proc_sys_reset_0_0
+     port map (
+      aux_reset_in => '1',
+      bus_struct_reset(0) => proc_sys_reset_0_bus_struct_reset(0),
+      dcm_locked => clk_wiz_0_locked,
+      ext_reset_in => reset_0_1,
+      interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
+      mb_debug_sys_rst => mdm_0_Debug_SYS_Rst,
+      mb_reset => proc_sys_reset_0_mb_reset,
+      peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
+      peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
+      slowest_sync_clk => clk_wiz_0_clk_100mhz
+    );
+xlconcat_0: component mb_design_1_xlconcat_0_0
+     port map (
+      In0(0) => axi_timer_0_interrupt,
+      dout(0) => xlconcat_0_dout(0)
+    );
+end STRUCTURE;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef
new file mode 100644
index 0000000000000000000000000000000000000000..d42322b095c2e4a24d9d8ec9bc6fffd500aab560
Binary files /dev/null and b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef differ
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b335fa1bf9f3a5acf54c568a927264a7d50963f9
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
@@ -0,0 +1,2741 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+--Date        : Sun Mar 23 23:26:53 2025
+--Host        : hogtest running 64-bit unknown
+--Command     : generate_target mb_design_1.bd
+--Design      : mb_design_1
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m00_couplers_imp_L30N86 is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m00_couplers_imp_L30N86;
+
+architecture STRUCTURE of m00_couplers_imp_L30N86 is
+  signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
+  signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
+  M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
+  M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
+  S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
+  S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
+  S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
+  m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
+  m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
+  m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
+  m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
+  m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
+  m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
+  m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
+  m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
+  m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
+  m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m01_couplers_imp_1MV3QBS is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m01_couplers_imp_1MV3QBS;
+
+architecture STRUCTURE of m01_couplers_imp_1MV3QBS is
+  signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
+  signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
+  M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
+  M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
+  S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
+  S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
+  S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
+  m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
+  m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
+  m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
+  m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
+  m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
+  m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
+  m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
+  m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
+  m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
+  m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m02_couplers_imp_1CM8QGB is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m02_couplers_imp_1CM8QGB;
+
+architecture STRUCTURE of m02_couplers_imp_1CM8QGB is
+  signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
+  signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
+  M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
+  M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
+  S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
+  S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
+  S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
+  m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
+  m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
+  m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
+  m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
+  m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
+  m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
+  m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
+  m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
+  m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
+  m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m03_couplers_imp_DKAE7P is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m03_couplers_imp_DKAE7P;
+
+architecture STRUCTURE of m03_couplers_imp_DKAE7P is
+  signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
+  signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
+  M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
+  M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
+  S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
+  S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
+  S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
+  m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
+  m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
+  m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
+  m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
+  m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
+  m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
+  m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
+  m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
+  m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
+  m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity m04_couplers_imp_OP7ZFX is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arready : in STD_LOGIC;
+    M_AXI_arvalid : out STD_LOGIC;
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awready : in STD_LOGIC;
+    M_AXI_awvalid : out STD_LOGIC;
+    M_AXI_bready : out STD_LOGIC;
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC;
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC;
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC;
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC;
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC;
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arready : out STD_LOGIC;
+    S_AXI_arvalid : in STD_LOGIC;
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awready : out STD_LOGIC;
+    S_AXI_awvalid : in STD_LOGIC;
+    S_AXI_bready : in STD_LOGIC;
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC;
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC;
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC;
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC;
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC
+  );
+end m04_couplers_imp_OP7ZFX;
+
+architecture STRUCTURE of m04_couplers_imp_OP7ZFX is
+  signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
+  signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
+begin
+  M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
+  M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
+  M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
+  M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
+  M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
+  M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
+  M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
+  S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
+  S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
+  S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
+  S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
+  S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
+  m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
+  m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
+  m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
+  m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
+  m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
+  m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
+  m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
+  m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
+  m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
+  m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity s00_couplers_imp_1AM08ZQ is
+  port (
+    M_ACLK : in STD_LOGIC;
+    M_ARESETN : in STD_LOGIC;
+    M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_ACLK : in STD_LOGIC;
+    S_ARESETN : in STD_LOGIC;
+    S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end s00_couplers_imp_1AM08ZQ;
+
+architecture STRUCTURE of s00_couplers_imp_1AM08ZQ is
+  signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+  M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
+  M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
+  M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
+  M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
+  M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
+  M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
+  M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
+  M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
+  M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
+  M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
+  M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
+  S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
+  S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
+  S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
+  S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
+  S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
+  S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
+  S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
+  S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
+  s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+  s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
+  s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
+  s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
+  s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+  s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
+  s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
+  s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
+  s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
+  s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+  s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
+  s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+  s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
+  s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+  s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
+  s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+  s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
+  s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+  s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi_interconnect_0_0 is
+  port (
+    ACLK : in STD_LOGIC;
+    ARESETN : in STD_LOGIC;
+    M00_ACLK : in STD_LOGIC;
+    M00_ARESETN : in STD_LOGIC;
+    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_arready : in STD_LOGIC;
+    M00_AXI_arvalid : out STD_LOGIC;
+    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_awready : in STD_LOGIC;
+    M00_AXI_awvalid : out STD_LOGIC;
+    M00_AXI_bready : out STD_LOGIC;
+    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_bvalid : in STD_LOGIC;
+    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_rready : out STD_LOGIC;
+    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M00_AXI_rvalid : in STD_LOGIC;
+    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M00_AXI_wready : in STD_LOGIC;
+    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M00_AXI_wvalid : out STD_LOGIC;
+    M01_ACLK : in STD_LOGIC;
+    M01_ARESETN : in STD_LOGIC;
+    M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_arready : in STD_LOGIC;
+    M01_AXI_arvalid : out STD_LOGIC;
+    M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_awready : in STD_LOGIC;
+    M01_AXI_awvalid : out STD_LOGIC;
+    M01_AXI_bready : out STD_LOGIC;
+    M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M01_AXI_bvalid : in STD_LOGIC;
+    M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_rready : out STD_LOGIC;
+    M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M01_AXI_rvalid : in STD_LOGIC;
+    M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M01_AXI_wready : in STD_LOGIC;
+    M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M01_AXI_wvalid : out STD_LOGIC;
+    M02_ACLK : in STD_LOGIC;
+    M02_ARESETN : in STD_LOGIC;
+    M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_arready : in STD_LOGIC;
+    M02_AXI_arvalid : out STD_LOGIC;
+    M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_awready : in STD_LOGIC;
+    M02_AXI_awvalid : out STD_LOGIC;
+    M02_AXI_bready : out STD_LOGIC;
+    M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M02_AXI_bvalid : in STD_LOGIC;
+    M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_rready : out STD_LOGIC;
+    M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M02_AXI_rvalid : in STD_LOGIC;
+    M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M02_AXI_wready : in STD_LOGIC;
+    M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M02_AXI_wvalid : out STD_LOGIC;
+    M03_ACLK : in STD_LOGIC;
+    M03_ARESETN : in STD_LOGIC;
+    M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_arready : in STD_LOGIC;
+    M03_AXI_arvalid : out STD_LOGIC;
+    M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_awready : in STD_LOGIC;
+    M03_AXI_awvalid : out STD_LOGIC;
+    M03_AXI_bready : out STD_LOGIC;
+    M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M03_AXI_bvalid : in STD_LOGIC;
+    M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_rready : out STD_LOGIC;
+    M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M03_AXI_rvalid : in STD_LOGIC;
+    M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M03_AXI_wready : in STD_LOGIC;
+    M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M03_AXI_wvalid : out STD_LOGIC;
+    M04_ACLK : in STD_LOGIC;
+    M04_ARESETN : in STD_LOGIC;
+    M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_arready : in STD_LOGIC;
+    M04_AXI_arvalid : out STD_LOGIC;
+    M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_awready : in STD_LOGIC;
+    M04_AXI_awvalid : out STD_LOGIC;
+    M04_AXI_bready : out STD_LOGIC;
+    M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M04_AXI_bvalid : in STD_LOGIC;
+    M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_rready : out STD_LOGIC;
+    M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M04_AXI_rvalid : in STD_LOGIC;
+    M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M04_AXI_wready : in STD_LOGIC;
+    M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M04_AXI_wvalid : out STD_LOGIC;
+    S00_ACLK : in STD_LOGIC;
+    S00_ARESETN : in STD_LOGIC;
+    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+end mb_design_1_axi_interconnect_0_0;
+
+architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
+  component mb_design_1_xbar_0 is
+  port (
+    aclk : in STD_LOGIC;
+    aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+    m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+    m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+    m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+    m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+    m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+    m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
+  );
+  end component mb_design_1_xbar_0;
+  signal M00_ACLK_1 : STD_LOGIC;
+  signal M00_ARESETN_1 : STD_LOGIC;
+  signal M01_ACLK_1 : STD_LOGIC;
+  signal M01_ARESETN_1 : STD_LOGIC;
+  signal M02_ACLK_1 : STD_LOGIC;
+  signal M02_ARESETN_1 : STD_LOGIC;
+  signal M03_ACLK_1 : STD_LOGIC;
+  signal M03_ARESETN_1 : STD_LOGIC;
+  signal M04_ACLK_1 : STD_LOGIC;
+  signal M04_ARESETN_1 : STD_LOGIC;
+  signal S00_ACLK_1 : STD_LOGIC;
+  signal S00_ARESETN_1 : STD_LOGIC;
+  signal axi_interconnect_0_ACLK_net : STD_LOGIC;
+  signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
+  signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m01_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m02_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m02_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m03_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+  signal m04_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal m04_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+  signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
+  signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
+  signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
+  signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
+  signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
+  signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
+  signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
+  signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
+  signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
+  signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
+  signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
+  signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
+  signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
+  signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
+  signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
+  signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+  signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
+  signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+  signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
+  signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
+  signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
+  signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
+  signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
+  signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
+  signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+  signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+  signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+begin
+  M00_ACLK_1 <= M00_ACLK;
+  M00_ARESETN_1 <= M00_ARESETN;
+  M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
+  M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
+  M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
+  M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
+  M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
+  M01_ACLK_1 <= M01_ACLK;
+  M01_ARESETN_1 <= M01_ARESETN;
+  M01_AXI_araddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
+  M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
+  M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
+  M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
+  M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
+  M02_ACLK_1 <= M02_ACLK;
+  M02_ARESETN_1 <= M02_ARESETN;
+  M02_AXI_araddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M02_AXI_arvalid <= m02_couplers_to_axi_interconnect_0_ARVALID;
+  M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M02_AXI_awvalid <= m02_couplers_to_axi_interconnect_0_AWVALID;
+  M02_AXI_bready <= m02_couplers_to_axi_interconnect_0_BREADY;
+  M02_AXI_rready <= m02_couplers_to_axi_interconnect_0_RREADY;
+  M02_AXI_wdata(31 downto 0) <= m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M02_AXI_wvalid <= m02_couplers_to_axi_interconnect_0_WVALID;
+  M03_ACLK_1 <= M03_ACLK;
+  M03_ARESETN_1 <= M03_ARESETN;
+  M03_AXI_araddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M03_AXI_arvalid <= m03_couplers_to_axi_interconnect_0_ARVALID;
+  M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M03_AXI_awvalid <= m03_couplers_to_axi_interconnect_0_AWVALID;
+  M03_AXI_bready <= m03_couplers_to_axi_interconnect_0_BREADY;
+  M03_AXI_rready <= m03_couplers_to_axi_interconnect_0_RREADY;
+  M03_AXI_wdata(31 downto 0) <= m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M03_AXI_wvalid <= m03_couplers_to_axi_interconnect_0_WVALID;
+  M04_ACLK_1 <= M04_ACLK;
+  M04_ARESETN_1 <= M04_ARESETN;
+  M04_AXI_araddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+  M04_AXI_arvalid <= m04_couplers_to_axi_interconnect_0_ARVALID;
+  M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+  M04_AXI_awvalid <= m04_couplers_to_axi_interconnect_0_AWVALID;
+  M04_AXI_bready <= m04_couplers_to_axi_interconnect_0_BREADY;
+  M04_AXI_rready <= m04_couplers_to_axi_interconnect_0_RREADY;
+  M04_AXI_wdata(31 downto 0) <= m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+  M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+  M04_AXI_wvalid <= m04_couplers_to_axi_interconnect_0_WVALID;
+  S00_ACLK_1 <= S00_ACLK;
+  S00_ARESETN_1 <= S00_ARESETN;
+  S00_AXI_arready(0) <= axi_interconnect_0_to_s00_couplers_ARREADY(0);
+  S00_AXI_awready(0) <= axi_interconnect_0_to_s00_couplers_AWREADY(0);
+  S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
+  S00_AXI_bvalid(0) <= axi_interconnect_0_to_s00_couplers_BVALID(0);
+  S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
+  S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
+  S00_AXI_rvalid(0) <= axi_interconnect_0_to_s00_couplers_RVALID(0);
+  S00_AXI_wready(0) <= axi_interconnect_0_to_s00_couplers_WREADY(0);
+  axi_interconnect_0_ACLK_net <= ACLK;
+  axi_interconnect_0_ARESETN_net <= ARESETN;
+  axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
+  axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
+  axi_interconnect_0_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
+  axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
+  axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
+  axi_interconnect_0_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
+  axi_interconnect_0_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
+  axi_interconnect_0_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
+  axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
+  axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
+  axi_interconnect_0_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
+  m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
+  m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
+  m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
+  m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
+  m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
+  m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
+  m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
+  m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
+  m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
+  m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
+  m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
+  m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
+  m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
+  m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
+  m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
+  m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
+  m02_couplers_to_axi_interconnect_0_ARREADY <= M02_AXI_arready;
+  m02_couplers_to_axi_interconnect_0_AWREADY <= M02_AXI_awready;
+  m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
+  m02_couplers_to_axi_interconnect_0_BVALID <= M02_AXI_bvalid;
+  m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
+  m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
+  m02_couplers_to_axi_interconnect_0_RVALID <= M02_AXI_rvalid;
+  m02_couplers_to_axi_interconnect_0_WREADY <= M02_AXI_wready;
+  m03_couplers_to_axi_interconnect_0_ARREADY <= M03_AXI_arready;
+  m03_couplers_to_axi_interconnect_0_AWREADY <= M03_AXI_awready;
+  m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
+  m03_couplers_to_axi_interconnect_0_BVALID <= M03_AXI_bvalid;
+  m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
+  m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
+  m03_couplers_to_axi_interconnect_0_RVALID <= M03_AXI_rvalid;
+  m03_couplers_to_axi_interconnect_0_WREADY <= M03_AXI_wready;
+  m04_couplers_to_axi_interconnect_0_ARREADY <= M04_AXI_arready;
+  m04_couplers_to_axi_interconnect_0_AWREADY <= M04_AXI_awready;
+  m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
+  m04_couplers_to_axi_interconnect_0_BVALID <= M04_AXI_bvalid;
+  m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
+  m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
+  m04_couplers_to_axi_interconnect_0_RVALID <= M04_AXI_rvalid;
+  m04_couplers_to_axi_interconnect_0_WREADY <= M04_AXI_wready;
+m00_couplers: entity work.m00_couplers_imp_L30N86
+     port map (
+      M_ACLK => M00_ACLK_1,
+      M_ARESETN => M00_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
+      S_AXI_arready => xbar_to_m00_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
+      S_AXI_awready => xbar_to_m00_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
+      S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
+      S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
+      S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
+      S_AXI_wready => xbar_to_m00_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
+      S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
+    );
+m01_couplers: entity work.m01_couplers_imp_1MV3QBS
+     port map (
+      M_ACLK => M01_ACLK_1,
+      M_ARESETN => M01_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
+      S_AXI_arready => xbar_to_m01_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
+      S_AXI_awready => xbar_to_m01_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
+      S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
+      S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
+      S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
+      S_AXI_wready => xbar_to_m01_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
+      S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
+    );
+m02_couplers: entity work.m02_couplers_imp_1CM8QGB
+     port map (
+      M_ACLK => M02_ACLK_1,
+      M_ARESETN => M02_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m02_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m02_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m02_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m02_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m02_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m02_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m02_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m02_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m02_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m02_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
+      S_AXI_arready => xbar_to_m02_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
+      S_AXI_awready => xbar_to_m02_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
+      S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
+      S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
+      S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
+      S_AXI_wready => xbar_to_m02_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
+      S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
+    );
+m03_couplers: entity work.m03_couplers_imp_DKAE7P
+     port map (
+      M_ACLK => M03_ACLK_1,
+      M_ARESETN => M03_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m03_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m03_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m03_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m03_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m03_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m03_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m03_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m03_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m03_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m03_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
+      S_AXI_arready => xbar_to_m03_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
+      S_AXI_awready => xbar_to_m03_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
+      S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
+      S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
+      S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
+      S_AXI_wready => xbar_to_m03_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
+      S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
+    );
+m04_couplers: entity work.m04_couplers_imp_OP7ZFX
+     port map (
+      M_ACLK => M04_ACLK_1,
+      M_ARESETN => M04_ARESETN_1,
+      M_AXI_araddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+      M_AXI_arready => m04_couplers_to_axi_interconnect_0_ARREADY,
+      M_AXI_arvalid => m04_couplers_to_axi_interconnect_0_ARVALID,
+      M_AXI_awaddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+      M_AXI_awready => m04_couplers_to_axi_interconnect_0_AWREADY,
+      M_AXI_awvalid => m04_couplers_to_axi_interconnect_0_AWVALID,
+      M_AXI_bready => m04_couplers_to_axi_interconnect_0_BREADY,
+      M_AXI_bresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+      M_AXI_bvalid => m04_couplers_to_axi_interconnect_0_BVALID,
+      M_AXI_rdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+      M_AXI_rready => m04_couplers_to_axi_interconnect_0_RREADY,
+      M_AXI_rresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+      M_AXI_rvalid => m04_couplers_to_axi_interconnect_0_RVALID,
+      M_AXI_wdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+      M_AXI_wready => m04_couplers_to_axi_interconnect_0_WREADY,
+      M_AXI_wstrb(3 downto 0) => m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+      M_AXI_wvalid => m04_couplers_to_axi_interconnect_0_WVALID,
+      S_ACLK => axi_interconnect_0_ACLK_net,
+      S_ARESETN => axi_interconnect_0_ARESETN_net,
+      S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
+      S_AXI_arready => xbar_to_m04_couplers_ARREADY,
+      S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
+      S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
+      S_AXI_awready => xbar_to_m04_couplers_AWREADY,
+      S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
+      S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
+      S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
+      S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
+      S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
+      S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
+      S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
+      S_AXI_wready => xbar_to_m04_couplers_WREADY,
+      S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
+      S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
+    );
+s00_couplers: entity work.s00_couplers_imp_1AM08ZQ
+     port map (
+      M_ACLK => axi_interconnect_0_ACLK_net,
+      M_ARESETN => axi_interconnect_0_ARESETN_net,
+      M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
+      M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
+      M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
+      M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
+      M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
+      M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
+      M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
+      M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
+      M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
+      M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
+      M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
+      M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
+      M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
+      M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
+      M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
+      M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
+      M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
+      M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
+      M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
+      S_ACLK => S00_ACLK_1,
+      S_ARESETN => S00_ARESETN_1,
+      S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
+      S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
+      S_AXI_arready(0) => axi_interconnect_0_to_s00_couplers_ARREADY(0),
+      S_AXI_arvalid(0) => axi_interconnect_0_to_s00_couplers_ARVALID(0),
+      S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
+      S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
+      S_AXI_awready(0) => axi_interconnect_0_to_s00_couplers_AWREADY(0),
+      S_AXI_awvalid(0) => axi_interconnect_0_to_s00_couplers_AWVALID(0),
+      S_AXI_bready(0) => axi_interconnect_0_to_s00_couplers_BREADY(0),
+      S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
+      S_AXI_bvalid(0) => axi_interconnect_0_to_s00_couplers_BVALID(0),
+      S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
+      S_AXI_rready(0) => axi_interconnect_0_to_s00_couplers_RREADY(0),
+      S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
+      S_AXI_rvalid(0) => axi_interconnect_0_to_s00_couplers_RVALID(0),
+      S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
+      S_AXI_wready(0) => axi_interconnect_0_to_s00_couplers_WREADY(0),
+      S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
+      S_AXI_wvalid(0) => axi_interconnect_0_to_s00_couplers_WVALID(0)
+    );
+xbar: component mb_design_1_xbar_0
+     port map (
+      aclk => axi_interconnect_0_ACLK_net,
+      aresetn => axi_interconnect_0_ARESETN_net,
+      m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
+      m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
+      m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
+      m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
+      m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
+      m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0),
+      m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
+      m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
+      m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
+      m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
+      m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
+      m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
+      m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
+      m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
+      m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
+      m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
+      m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
+      m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
+      m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
+      m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
+      m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
+      m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0),
+      m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
+      m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
+      m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
+      m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
+      m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
+      m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
+      m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
+      m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
+      m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
+      m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
+      m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
+      m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
+      m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
+      m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
+      m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
+      m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
+      m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
+      m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
+      m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
+      m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
+      m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
+      m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
+      m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
+      m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
+      m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
+      m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
+      m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
+      m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
+      m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
+      m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
+      m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
+      m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
+      m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
+      m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
+      m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
+      m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
+      m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
+      m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
+      m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
+      m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
+      m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
+      m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
+      m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
+      m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
+      m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
+      m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
+      m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
+      m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
+      m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
+      m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
+      m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
+      m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
+      m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
+      m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
+      m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
+      m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
+      m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
+      m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
+      m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
+      m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
+      m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
+      m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
+      m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
+      m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
+      m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
+      s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
+      s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
+      s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
+      s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
+      s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
+      s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
+      s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
+      s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
+      s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
+      s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
+      s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
+      s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
+      s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
+      s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
+      s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
+      s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
+      s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
+      s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
+      s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1 is
+  port (
+    GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    clk_in1 : in STD_LOGIC;
+    hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    reset : in STD_LOGIC
+  );
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=15,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
+  attribute HW_HANDOFF : string;
+  attribute HW_HANDOFF of mb_design_1 : entity is "mb_design_1.hwdef";
+end mb_design_1;
+
+architecture STRUCTURE of mb_design_1 is
+  component mb_design_1_microblaze_0_0 is
+  port (
+    Clk : in STD_LOGIC;
+    Reset : in STD_LOGIC;
+    Interrupt : in STD_LOGIC;
+    Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
+    Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
+    IFetch : out STD_LOGIC;
+    I_AS : out STD_LOGIC;
+    IReady : in STD_LOGIC;
+    IWAIT : in STD_LOGIC;
+    ICE : in STD_LOGIC;
+    IUE : in STD_LOGIC;
+    Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
+    D_AS : out STD_LOGIC;
+    Read_Strobe : out STD_LOGIC;
+    Write_Strobe : out STD_LOGIC;
+    DReady : in STD_LOGIC;
+    DWait : in STD_LOGIC;
+    DCE : in STD_LOGIC;
+    DUE : in STD_LOGIC;
+    Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
+    M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_DP_AWVALID : out STD_LOGIC;
+    M_AXI_DP_AWREADY : in STD_LOGIC;
+    M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    M_AXI_DP_WVALID : out STD_LOGIC;
+    M_AXI_DP_WREADY : in STD_LOGIC;
+    M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_DP_BVALID : in STD_LOGIC;
+    M_AXI_DP_BREADY : out STD_LOGIC;
+    M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    M_AXI_DP_ARVALID : out STD_LOGIC;
+    M_AXI_DP_ARREADY : in STD_LOGIC;
+    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    M_AXI_DP_RVALID : in STD_LOGIC;
+    M_AXI_DP_RREADY : out STD_LOGIC;
+    Dbg_Clk : in STD_LOGIC;
+    Dbg_TDI : in STD_LOGIC;
+    Dbg_TDO : out STD_LOGIC;
+    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
+    Dbg_Shift : in STD_LOGIC;
+    Dbg_Capture : in STD_LOGIC;
+    Dbg_Update : in STD_LOGIC;
+    Debug_Rst : in STD_LOGIC;
+    Dbg_Disable : in STD_LOGIC
+  );
+  end component mb_design_1_microblaze_0_0;
+  component mb_design_1_clk_wiz_0_0 is
+  port (
+    reset : in STD_LOGIC;
+    clk_in1 : in STD_LOGIC;
+    clk_100mhz : out STD_LOGIC;
+    locked : out STD_LOGIC
+  );
+  end component mb_design_1_clk_wiz_0_0;
+  component mb_design_1_proc_sys_reset_0_0 is
+  port (
+    slowest_sync_clk : in STD_LOGIC;
+    ext_reset_in : in STD_LOGIC;
+    aux_reset_in : in STD_LOGIC;
+    mb_debug_sys_rst : in STD_LOGIC;
+    dcm_locked : in STD_LOGIC;
+    mb_reset : out STD_LOGIC;
+    bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
+    peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
+    interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
+    peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component mb_design_1_proc_sys_reset_0_0;
+  component mb_design_1_lmb_v10_0_0 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    SYS_Rst : in STD_LOGIC;
+    LMB_Rst : out STD_LOGIC;
+    M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_ReadStrobe : in STD_LOGIC;
+    M_WriteStrobe : in STD_LOGIC;
+    M_AddrStrobe : in STD_LOGIC;
+    M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_ReadStrobe : out STD_LOGIC;
+    LMB_WriteStrobe : out STD_LOGIC;
+    LMB_AddrStrobe : out STD_LOGIC;
+    LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_Ready : out STD_LOGIC;
+    LMB_Wait : out STD_LOGIC;
+    LMB_UE : out STD_LOGIC;
+    LMB_CE : out STD_LOGIC;
+    LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
+  );
+  end component mb_design_1_lmb_v10_0_0;
+  component mb_design_1_ilmb_v10_0_0 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    SYS_Rst : in STD_LOGIC;
+    LMB_Rst : out STD_LOGIC;
+    M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_ReadStrobe : in STD_LOGIC;
+    M_WriteStrobe : in STD_LOGIC;
+    M_AddrStrobe : in STD_LOGIC;
+    M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_ReadStrobe : out STD_LOGIC;
+    LMB_WriteStrobe : out STD_LOGIC;
+    LMB_AddrStrobe : out STD_LOGIC;
+    LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_Ready : out STD_LOGIC;
+    LMB_Wait : out STD_LOGIC;
+    LMB_UE : out STD_LOGIC;
+    LMB_CE : out STD_LOGIC;
+    LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
+  );
+  end component mb_design_1_ilmb_v10_0_0;
+  component mb_design_1_lmb_bram_if_cntlr_0_0 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    LMB_Rst : in STD_LOGIC;
+    LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_AddrStrobe : in STD_LOGIC;
+    LMB_ReadStrobe : in STD_LOGIC;
+    LMB_WriteStrobe : in STD_LOGIC;
+    LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : out STD_LOGIC;
+    Sl_Wait : out STD_LOGIC;
+    Sl_UE : out STD_LOGIC;
+    Sl_CE : out STD_LOGIC;
+    BRAM_Rst_A : out STD_LOGIC;
+    BRAM_Clk_A : out STD_LOGIC;
+    BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_EN_A : out STD_LOGIC;
+    BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
+    BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
+  );
+  end component mb_design_1_lmb_bram_if_cntlr_0_0;
+  component mb_design_1_lmb_bram_if_cntlr_0_1 is
+  port (
+    LMB_Clk : in STD_LOGIC;
+    LMB_Rst : in STD_LOGIC;
+    LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_AddrStrobe : in STD_LOGIC;
+    LMB_ReadStrobe : in STD_LOGIC;
+    LMB_WriteStrobe : in STD_LOGIC;
+    LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : out STD_LOGIC;
+    Sl_Wait : out STD_LOGIC;
+    Sl_UE : out STD_LOGIC;
+    Sl_CE : out STD_LOGIC;
+    BRAM_Rst_A : out STD_LOGIC;
+    BRAM_Clk_A : out STD_LOGIC;
+    BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_EN_A : out STD_LOGIC;
+    BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
+    BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
+  );
+  end component mb_design_1_lmb_bram_if_cntlr_0_1;
+  component mb_design_1_blk_mem_gen_0_0 is
+  port (
+    clka : in STD_LOGIC;
+    rsta : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clkb : in STD_LOGIC;
+    rstb : in STD_LOGIC;
+    enb : in STD_LOGIC;
+    web : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    rsta_busy : out STD_LOGIC;
+    rstb_busy : out STD_LOGIC
+  );
+  end component mb_design_1_blk_mem_gen_0_0;
+  component mb_design_1_mdm_0_0 is
+  port (
+    S_AXI_ACLK : in STD_LOGIC;
+    S_AXI_ARESETN : in STD_LOGIC;
+    Interrupt : out STD_LOGIC;
+    Debug_SYS_Rst : out STD_LOGIC;
+    S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_AWVALID : in STD_LOGIC;
+    S_AXI_AWREADY : out STD_LOGIC;
+    S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_WVALID : in STD_LOGIC;
+    S_AXI_WREADY : out STD_LOGIC;
+    S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_BVALID : out STD_LOGIC;
+    S_AXI_BREADY : in STD_LOGIC;
+    S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    S_AXI_ARVALID : in STD_LOGIC;
+    S_AXI_ARREADY : out STD_LOGIC;
+    S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    S_AXI_RVALID : out STD_LOGIC;
+    S_AXI_RREADY : in STD_LOGIC;
+    Dbg_Clk_0 : out STD_LOGIC;
+    Dbg_TDI_0 : out STD_LOGIC;
+    Dbg_TDO_0 : in STD_LOGIC;
+    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
+    Dbg_Capture_0 : out STD_LOGIC;
+    Dbg_Shift_0 : out STD_LOGIC;
+    Dbg_Update_0 : out STD_LOGIC;
+    Dbg_Rst_0 : out STD_LOGIC;
+    Dbg_Disable_0 : out STD_LOGIC
+  );
+  end component mb_design_1_mdm_0_0;
+  component mb_design_1_axi_gpio_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+  end component mb_design_1_axi_gpio_0_0;
+  component mb_design_1_axi_timer_0_0 is
+  port (
+    capturetrig0 : in STD_LOGIC;
+    capturetrig1 : in STD_LOGIC;
+    generateout0 : out STD_LOGIC;
+    generateout1 : out STD_LOGIC;
+    pwm0 : out STD_LOGIC;
+    interrupt : out STD_LOGIC;
+    freeze : in STD_LOGIC;
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC
+  );
+  end component mb_design_1_axi_timer_0_0;
+  component mb_design_1_axi_intc_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    intr : in STD_LOGIC_VECTOR ( 0 to 0 );
+    irq : out STD_LOGIC
+  );
+  end component mb_design_1_axi_intc_0_0;
+  component mb_design_1_xlconcat_0_0 is
+  port (
+    In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    dout : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+  end component mb_design_1_xlconcat_0_0;
+  component mb_design_1_axi4lite_hog_build_i_0_0 is
+  port (
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+  end component mb_design_1_axi4lite_hog_build_i_0_0;
+  signal Conn1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn1_ADDRSTROBE : STD_LOGIC;
+  signal Conn1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal Conn1_CE : STD_LOGIC;
+  signal Conn1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn1_READSTROBE : STD_LOGIC;
+  signal Conn1_READY : STD_LOGIC;
+  signal Conn1_UE : STD_LOGIC;
+  signal Conn1_WAIT : STD_LOGIC;
+  signal Conn1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn1_WRITESTROBE : STD_LOGIC;
+  signal Conn_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn_ADDRSTROBE : STD_LOGIC;
+  signal Conn_BE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal Conn_CE : STD_LOGIC;
+  signal Conn_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn_READSTROBE : STD_LOGIC;
+  signal Conn_READY : STD_LOGIC;
+  signal Conn_UE : STD_LOGIC;
+  signal Conn_WAIT : STD_LOGIC;
+  signal Conn_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal Conn_WRITESTROBE : STD_LOGIC;
+  signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal S00_AXI_1_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_ARVALID : STD_LOGIC;
+  signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
+  signal S00_AXI_1_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_AWVALID : STD_LOGIC;
+  signal S00_AXI_1_BREADY : STD_LOGIC;
+  signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal S00_AXI_1_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_RREADY : STD_LOGIC;
+  signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal S00_AXI_1_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal S00_AXI_1_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal S00_AXI_1_WVALID : STD_LOGIC;
+  signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
+  signal axi_intc_0_interrupt_INTERRUPT : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
+  signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
+  signal axi_timer_0_interrupt : STD_LOGIC;
+  signal clk_in1_0_1 : STD_LOGIC;
+  signal clk_wiz_0_clk_100mhz : STD_LOGIC;
+  signal clk_wiz_0_locked : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
+  signal dlmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal hog_global_date_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal hog_global_sha_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal hog_global_time_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal hog_global_ver_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
+  signal ilmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal mdm_0_Debug_SYS_Rst : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_CAPTURE : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_CLK : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_DISABLE : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
+  signal mdm_0_MBDEBUG_0_RST : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_SHIFT : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_TDI : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_TDO : STD_LOGIC;
+  signal mdm_0_MBDEBUG_0_UPDATE : STD_LOGIC;
+  signal microblaze_0_DLMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_DLMB_ADDRSTROBE : STD_LOGIC;
+  signal microblaze_0_DLMB_BE : STD_LOGIC_VECTOR ( 0 to 3 );
+  signal microblaze_0_DLMB_CE : STD_LOGIC;
+  signal microblaze_0_DLMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_DLMB_READSTROBE : STD_LOGIC;
+  signal microblaze_0_DLMB_READY : STD_LOGIC;
+  signal microblaze_0_DLMB_UE : STD_LOGIC;
+  signal microblaze_0_DLMB_WAIT : STD_LOGIC;
+  signal microblaze_0_DLMB_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_DLMB_WRITESTROBE : STD_LOGIC;
+  signal microblaze_0_ILMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_ILMB_ADDRSTROBE : STD_LOGIC;
+  signal microblaze_0_ILMB_CE : STD_LOGIC;
+  signal microblaze_0_ILMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
+  signal microblaze_0_ILMB_READSTROBE : STD_LOGIC;
+  signal microblaze_0_ILMB_READY : STD_LOGIC;
+  signal microblaze_0_ILMB_UE : STD_LOGIC;
+  signal microblaze_0_ILMB_WAIT : STD_LOGIC;
+  signal proc_sys_reset_0_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal proc_sys_reset_0_mb_reset : STD_LOGIC;
+  signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal reset_0_1 : STD_LOGIC;
+  signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
+  signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
+  signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
+  signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
+  signal NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
+  signal NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
+  signal NLW_mdm_0_Interrupt_UNCONNECTED : STD_LOGIC;
+  signal NLW_microblaze_0_Interrupt_Ack_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 1 );
+  signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
+  attribute BMM_INFO_ADDRESS_SPACE : string;
+  attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr_0 : label is "byte  0x00000000 32 > mb_design_1 blk_mem_gen_0";
+  attribute KEEP_HIERARCHY : string;
+  attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr_0 : label is "yes";
+  attribute BMM_INFO_PROCESSOR : string;
+  attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > mb_design_1 dlmb_bram_if_cntlr_0";
+  attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
+  attribute X_INTERFACE_INFO : string;
+  attribute X_INTERFACE_INFO of clk_in1 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_IN1 CLK";
+  attribute X_INTERFACE_PARAMETER : string;
+  attribute X_INTERFACE_PARAMETER of clk_in1 : signal is "XIL_INTERFACENAME CLK.CLK_IN1, ASSOCIATED_RESET reset, CLK_DOMAIN mb_design_1_clk_in1_0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
+  attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 RST.RESET RST";
+  attribute X_INTERFACE_PARAMETER of reset : signal is "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
+  attribute X_INTERFACE_INFO of GPIO_0_tri_o : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O";
+begin
+  GPIO_0_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
+  clk_in1_0_1 <= clk_in1;
+  hog_global_date_i_0_1(31 downto 0) <= hog_global_date_i_0(31 downto 0);
+  hog_global_sha_i_0_1(31 downto 0) <= hog_global_sha_i_0(31 downto 0);
+  hog_global_time_i_0_1(31 downto 0) <= hog_global_time_i_0(31 downto 0);
+  hog_global_ver_i_0_1(31 downto 0) <= hog_global_ver_i_0(31 downto 0);
+  reset_0_1 <= reset;
+axi4lite_hog_build_i_0: component mb_design_1_axi4lite_hog_build_i_0_0
+     port map (
+      hog_global_date_i(31 downto 0) => hog_global_date_i_0_1(31 downto 0),
+      hog_global_sha_i(31 downto 0) => hog_global_sha_i_0_1(31 downto 0),
+      hog_global_time_i(31 downto 0) => hog_global_time_i_0_1(31 downto 0),
+      hog_global_ver_i(31 downto 0) => hog_global_ver_i_0_1(31 downto 0),
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M04_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+      s_axi_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+      s_axi_awready => axi_interconnect_0_M04_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M04_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M04_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M04_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M04_AXI_WVALID
+    );
+axi_gpio_0: component mb_design_1_axi_gpio_0_0
+     port map (
+      gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
+      s_axi_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
+      s_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
+    );
+axi_intc_0: component mb_design_1_axi_intc_0_0
+     port map (
+      intr(0) => xlconcat_0_dout(0),
+      irq => axi_intc_0_interrupt_INTERRUPT,
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(8 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(8 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+      s_axi_awaddr(8 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(8 downto 0),
+      s_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
+    );
+axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
+     port map (
+      ACLK => clk_wiz_0_clk_100mhz,
+      ARESETN => proc_sys_reset_0_interconnect_aresetn(0),
+      M00_ACLK => clk_wiz_0_clk_100mhz,
+      M00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
+      M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
+      M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
+      M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
+      M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
+      M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
+      M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
+      M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
+      M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
+      M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
+      M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
+      M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
+      M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
+      M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
+      M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
+      M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
+      M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
+      M01_ACLK => clk_wiz_0_clk_100mhz,
+      M01_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
+      M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
+      M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
+      M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
+      M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
+      M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
+      M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
+      M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
+      M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
+      M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
+      M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
+      M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
+      M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
+      M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
+      M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
+      M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
+      M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
+      M02_ACLK => clk_wiz_0_clk_100mhz,
+      M02_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
+      M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
+      M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
+      M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
+      M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
+      M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
+      M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
+      M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
+      M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
+      M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
+      M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
+      M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
+      M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
+      M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
+      M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
+      M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
+      M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
+      M03_ACLK => clk_wiz_0_clk_100mhz,
+      M03_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
+      M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
+      M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+      M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
+      M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
+      M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+      M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
+      M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+      M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+      M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+      M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
+      M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+      M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+      M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+      M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
+      M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+      M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
+      M04_ACLK => clk_wiz_0_clk_100mhz,
+      M04_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+      M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
+      M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+      M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+      M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
+      M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+      M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
+      M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+      M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+      M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+      M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
+      M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+      M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+      M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+      M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
+      M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+      M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
+      S00_ACLK => clk_wiz_0_clk_100mhz,
+      S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
+      S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
+      S00_AXI_arready(0) => S00_AXI_1_ARREADY(0),
+      S00_AXI_arvalid(0) => S00_AXI_1_ARVALID,
+      S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
+      S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
+      S00_AXI_awready(0) => S00_AXI_1_AWREADY(0),
+      S00_AXI_awvalid(0) => S00_AXI_1_AWVALID,
+      S00_AXI_bready(0) => S00_AXI_1_BREADY,
+      S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
+      S00_AXI_bvalid(0) => S00_AXI_1_BVALID(0),
+      S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
+      S00_AXI_rready(0) => S00_AXI_1_RREADY,
+      S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
+      S00_AXI_rvalid(0) => S00_AXI_1_RVALID(0),
+      S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
+      S00_AXI_wready(0) => S00_AXI_1_WREADY(0),
+      S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
+      S00_AXI_wvalid(0) => S00_AXI_1_WVALID
+    );
+axi_timer_0: component mb_design_1_axi_timer_0_0
+     port map (
+      capturetrig0 => '0',
+      capturetrig1 => '0',
+      freeze => '0',
+      generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
+      generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
+      interrupt => axi_timer_0_interrupt,
+      pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
+      s_axi_aclk => clk_wiz_0_clk_100mhz,
+      s_axi_araddr(4 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(4 downto 0),
+      s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+      s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
+      s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
+      s_axi_awaddr(4 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(4 downto 0),
+      s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
+      s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
+      s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
+      s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
+      s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
+      s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
+      s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
+      s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
+      s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
+      s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
+      s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
+      s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
+      s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
+    );
+blk_mem_gen_0: component mb_design_1_blk_mem_gen_0_0
+     port map (
+      addra(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
+      addra(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
+      addra(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
+      addra(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
+      addra(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
+      addra(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
+      addra(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
+      addra(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
+      addra(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
+      addra(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
+      addra(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
+      addra(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
+      addra(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
+      addra(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
+      addra(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
+      addra(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
+      addra(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
+      addra(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
+      addra(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
+      addra(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
+      addra(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
+      addra(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
+      addra(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
+      addra(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
+      addra(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
+      addra(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
+      addra(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
+      addra(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
+      addra(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
+      addra(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
+      addra(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
+      addra(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
+      addrb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
+      addrb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
+      addrb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
+      addrb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
+      addrb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
+      addrb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
+      addrb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
+      addrb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
+      addrb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
+      addrb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
+      addrb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
+      addrb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
+      addrb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
+      addrb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
+      addrb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
+      addrb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
+      addrb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
+      addrb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
+      addrb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
+      addrb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
+      addrb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
+      addrb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
+      addrb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
+      addrb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
+      addrb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
+      addrb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
+      addrb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
+      addrb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
+      addrb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
+      addrb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
+      addrb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
+      addrb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
+      clka => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      clkb => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      dina(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
+      dina(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
+      dina(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
+      dina(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
+      dina(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
+      dina(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
+      dina(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
+      dina(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
+      dina(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
+      dina(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
+      dina(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
+      dina(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
+      dina(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
+      dina(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
+      dina(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
+      dina(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
+      dina(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
+      dina(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
+      dina(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
+      dina(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
+      dina(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
+      dina(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
+      dina(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
+      dina(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
+      dina(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
+      dina(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
+      dina(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
+      dina(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
+      dina(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
+      dina(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
+      dina(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
+      dina(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
+      dinb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
+      dinb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
+      dinb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
+      dinb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
+      dinb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
+      dinb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
+      dinb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
+      dinb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
+      dinb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
+      dinb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
+      dinb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
+      dinb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
+      dinb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
+      dinb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
+      dinb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
+      dinb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
+      dinb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
+      dinb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
+      dinb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
+      dinb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
+      dinb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
+      dinb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
+      dinb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
+      dinb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
+      dinb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
+      dinb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
+      dinb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
+      dinb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
+      dinb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
+      dinb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
+      dinb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
+      dinb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
+      douta(31 downto 0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
+      doutb(31 downto 0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
+      ena => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      enb => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      rsta => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      rsta_busy => NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED,
+      rstb => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      rstb_busy => NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED,
+      wea(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
+      wea(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
+      wea(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
+      wea(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(3),
+      web(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
+      web(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
+      web(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
+      web(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(3)
+    );
+clk_wiz_0: component mb_design_1_clk_wiz_0_0
+     port map (
+      clk_100mhz => clk_wiz_0_clk_100mhz,
+      clk_in1 => clk_in1_0_1,
+      locked => clk_wiz_0_locked,
+      reset => reset_0_1
+    );
+dlmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_0
+     port map (
+      BRAM_Addr_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
+      BRAM_Clk_A => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      BRAM_Din_A(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
+      BRAM_Din_A(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
+      BRAM_Din_A(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
+      BRAM_Din_A(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
+      BRAM_Din_A(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
+      BRAM_Din_A(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
+      BRAM_Din_A(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
+      BRAM_Din_A(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
+      BRAM_Din_A(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
+      BRAM_Din_A(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
+      BRAM_Din_A(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
+      BRAM_Din_A(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
+      BRAM_Din_A(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
+      BRAM_Din_A(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
+      BRAM_Din_A(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
+      BRAM_Din_A(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
+      BRAM_Din_A(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
+      BRAM_Din_A(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
+      BRAM_Din_A(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
+      BRAM_Din_A(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
+      BRAM_Din_A(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
+      BRAM_Din_A(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
+      BRAM_Din_A(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
+      BRAM_Din_A(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
+      BRAM_Din_A(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
+      BRAM_Din_A(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
+      BRAM_Din_A(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
+      BRAM_Din_A(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
+      BRAM_Din_A(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
+      BRAM_Din_A(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
+      BRAM_Din_A(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
+      BRAM_Din_A(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
+      BRAM_Dout_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
+      BRAM_EN_A => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      BRAM_Rst_A => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      BRAM_WEN_A(0 to 3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
+      LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn1_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn1_BE(0 to 3),
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadStrobe => Conn1_READSTROBE,
+      LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn1_WRITESTROBE,
+      Sl_CE => Conn1_CE,
+      Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
+      Sl_Ready => Conn1_READY,
+      Sl_UE => Conn1_UE,
+      Sl_Wait => Conn1_WAIT
+    );
+dlmb_v10_0: component mb_design_1_ilmb_v10_0_0
+     port map (
+      LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn1_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn1_BE(0 to 3),
+      LMB_CE => microblaze_0_DLMB_CE,
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadDBus(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
+      LMB_ReadStrobe => Conn1_READSTROBE,
+      LMB_Ready => microblaze_0_DLMB_READY,
+      LMB_Rst => NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED,
+      LMB_UE => microblaze_0_DLMB_UE,
+      LMB_Wait => microblaze_0_DLMB_WAIT,
+      LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn1_WRITESTROBE,
+      M_ABus(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
+      M_AddrStrobe => microblaze_0_DLMB_ADDRSTROBE,
+      M_BE(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
+      M_DBus(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
+      M_ReadStrobe => microblaze_0_DLMB_READSTROBE,
+      M_WriteStrobe => microblaze_0_DLMB_WRITESTROBE,
+      SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      Sl_CE(0) => Conn1_CE,
+      Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
+      Sl_Ready(0) => Conn1_READY,
+      Sl_UE(0) => Conn1_UE,
+      Sl_Wait(0) => Conn1_WAIT
+    );
+ilmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_1
+     port map (
+      BRAM_Addr_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
+      BRAM_Clk_A => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
+      BRAM_Din_A(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
+      BRAM_Din_A(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
+      BRAM_Din_A(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
+      BRAM_Din_A(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
+      BRAM_Din_A(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
+      BRAM_Din_A(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
+      BRAM_Din_A(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
+      BRAM_Din_A(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
+      BRAM_Din_A(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
+      BRAM_Din_A(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
+      BRAM_Din_A(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
+      BRAM_Din_A(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
+      BRAM_Din_A(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
+      BRAM_Din_A(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
+      BRAM_Din_A(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
+      BRAM_Din_A(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
+      BRAM_Din_A(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
+      BRAM_Din_A(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
+      BRAM_Din_A(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
+      BRAM_Din_A(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
+      BRAM_Din_A(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
+      BRAM_Din_A(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
+      BRAM_Din_A(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
+      BRAM_Din_A(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
+      BRAM_Din_A(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
+      BRAM_Din_A(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
+      BRAM_Din_A(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
+      BRAM_Din_A(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
+      BRAM_Din_A(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
+      BRAM_Din_A(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
+      BRAM_Din_A(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
+      BRAM_Din_A(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
+      BRAM_Dout_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
+      BRAM_EN_A => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
+      BRAM_Rst_A => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
+      BRAM_WEN_A(0 to 3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
+      LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn_BE(0 to 3),
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadStrobe => Conn_READSTROBE,
+      LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn_WRITESTROBE,
+      Sl_CE => Conn_CE,
+      Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
+      Sl_Ready => Conn_READY,
+      Sl_UE => Conn_UE,
+      Sl_Wait => Conn_WAIT
+    );
+ilmb_v10_0: component mb_design_1_lmb_v10_0_0
+     port map (
+      LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
+      LMB_AddrStrobe => Conn_ADDRSTROBE,
+      LMB_BE(0 to 3) => Conn_BE(0 to 3),
+      LMB_CE => microblaze_0_ILMB_CE,
+      LMB_Clk => clk_wiz_0_clk_100mhz,
+      LMB_ReadDBus(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
+      LMB_ReadStrobe => Conn_READSTROBE,
+      LMB_Ready => microblaze_0_ILMB_READY,
+      LMB_Rst => NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED,
+      LMB_UE => microblaze_0_ILMB_UE,
+      LMB_Wait => microblaze_0_ILMB_WAIT,
+      LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
+      LMB_WriteStrobe => Conn_WRITESTROBE,
+      M_ABus(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
+      M_AddrStrobe => microblaze_0_ILMB_ADDRSTROBE,
+      M_BE(0 to 3) => B"0000",
+      M_DBus(0 to 31) => B"00000000000000000000000000000000",
+      M_ReadStrobe => microblaze_0_ILMB_READSTROBE,
+      M_WriteStrobe => '0',
+      SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
+      Sl_CE(0) => Conn_CE,
+      Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
+      Sl_Ready(0) => Conn_READY,
+      Sl_UE(0) => Conn_UE,
+      Sl_Wait(0) => Conn_WAIT
+    );
+mdm_0: component mb_design_1_mdm_0_0
+     port map (
+      Dbg_Capture_0 => mdm_0_MBDEBUG_0_CAPTURE,
+      Dbg_Clk_0 => mdm_0_MBDEBUG_0_CLK,
+      Dbg_Disable_0 => mdm_0_MBDEBUG_0_DISABLE,
+      Dbg_Reg_En_0(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
+      Dbg_Rst_0 => mdm_0_MBDEBUG_0_RST,
+      Dbg_Shift_0 => mdm_0_MBDEBUG_0_SHIFT,
+      Dbg_TDI_0 => mdm_0_MBDEBUG_0_TDI,
+      Dbg_TDO_0 => mdm_0_MBDEBUG_0_TDO,
+      Dbg_Update_0 => mdm_0_MBDEBUG_0_UPDATE,
+      Debug_SYS_Rst => mdm_0_Debug_SYS_Rst,
+      Interrupt => NLW_mdm_0_Interrupt_UNCONNECTED,
+      S_AXI_ACLK => clk_wiz_0_clk_100mhz,
+      S_AXI_ARADDR(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
+      S_AXI_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+      S_AXI_ARREADY => axi_interconnect_0_M00_AXI_ARREADY,
+      S_AXI_ARVALID => axi_interconnect_0_M00_AXI_ARVALID,
+      S_AXI_AWADDR(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
+      S_AXI_AWREADY => axi_interconnect_0_M00_AXI_AWREADY,
+      S_AXI_AWVALID => axi_interconnect_0_M00_AXI_AWVALID,
+      S_AXI_BREADY => axi_interconnect_0_M00_AXI_BREADY,
+      S_AXI_BRESP(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
+      S_AXI_BVALID => axi_interconnect_0_M00_AXI_BVALID,
+      S_AXI_RDATA(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
+      S_AXI_RREADY => axi_interconnect_0_M00_AXI_RREADY,
+      S_AXI_RRESP(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
+      S_AXI_RVALID => axi_interconnect_0_M00_AXI_RVALID,
+      S_AXI_WDATA(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
+      S_AXI_WREADY => axi_interconnect_0_M00_AXI_WREADY,
+      S_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
+      S_AXI_WVALID => axi_interconnect_0_M00_AXI_WVALID
+    );
+microblaze_0: component mb_design_1_microblaze_0_0
+     port map (
+      Byte_Enable(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
+      Clk => clk_wiz_0_clk_100mhz,
+      DCE => microblaze_0_DLMB_CE,
+      DReady => microblaze_0_DLMB_READY,
+      DUE => microblaze_0_DLMB_UE,
+      DWait => microblaze_0_DLMB_WAIT,
+      D_AS => microblaze_0_DLMB_ADDRSTROBE,
+      Data_Addr(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
+      Data_Read(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
+      Data_Write(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
+      Dbg_Capture => mdm_0_MBDEBUG_0_CAPTURE,
+      Dbg_Clk => mdm_0_MBDEBUG_0_CLK,
+      Dbg_Disable => mdm_0_MBDEBUG_0_DISABLE,
+      Dbg_Reg_En(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
+      Dbg_Shift => mdm_0_MBDEBUG_0_SHIFT,
+      Dbg_TDI => mdm_0_MBDEBUG_0_TDI,
+      Dbg_TDO => mdm_0_MBDEBUG_0_TDO,
+      Dbg_Update => mdm_0_MBDEBUG_0_UPDATE,
+      Debug_Rst => mdm_0_MBDEBUG_0_RST,
+      ICE => microblaze_0_ILMB_CE,
+      IFetch => microblaze_0_ILMB_READSTROBE,
+      IReady => microblaze_0_ILMB_READY,
+      IUE => microblaze_0_ILMB_UE,
+      IWAIT => microblaze_0_ILMB_WAIT,
+      I_AS => microblaze_0_ILMB_ADDRSTROBE,
+      Instr(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
+      Instr_Addr(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
+      Interrupt => axi_intc_0_interrupt_INTERRUPT,
+      Interrupt_Ack(0 to 1) => NLW_microblaze_0_Interrupt_Ack_UNCONNECTED(0 to 1),
+      Interrupt_Address(0 to 31) => B"00000000000000000000000000000000",
+      M_AXI_DP_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
+      M_AXI_DP_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
+      M_AXI_DP_ARREADY => S00_AXI_1_ARREADY(0),
+      M_AXI_DP_ARVALID => S00_AXI_1_ARVALID,
+      M_AXI_DP_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
+      M_AXI_DP_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
+      M_AXI_DP_AWREADY => S00_AXI_1_AWREADY(0),
+      M_AXI_DP_AWVALID => S00_AXI_1_AWVALID,
+      M_AXI_DP_BREADY => S00_AXI_1_BREADY,
+      M_AXI_DP_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
+      M_AXI_DP_BVALID => S00_AXI_1_BVALID(0),
+      M_AXI_DP_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
+      M_AXI_DP_RREADY => S00_AXI_1_RREADY,
+      M_AXI_DP_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
+      M_AXI_DP_RVALID => S00_AXI_1_RVALID(0),
+      M_AXI_DP_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
+      M_AXI_DP_WREADY => S00_AXI_1_WREADY(0),
+      M_AXI_DP_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
+      M_AXI_DP_WVALID => S00_AXI_1_WVALID,
+      Read_Strobe => microblaze_0_DLMB_READSTROBE,
+      Reset => proc_sys_reset_0_mb_reset,
+      Write_Strobe => microblaze_0_DLMB_WRITESTROBE
+    );
+proc_sys_reset_0: component mb_design_1_proc_sys_reset_0_0
+     port map (
+      aux_reset_in => '1',
+      bus_struct_reset(0) => proc_sys_reset_0_bus_struct_reset(0),
+      dcm_locked => clk_wiz_0_locked,
+      ext_reset_in => reset_0_1,
+      interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
+      mb_debug_sys_rst => mdm_0_Debug_SYS_Rst,
+      mb_reset => proc_sys_reset_0_mb_reset,
+      peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
+      peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
+      slowest_sync_clk => clk_wiz_0_clk_100mhz
+    );
+xlconcat_0: component mb_design_1_xlconcat_0_0
+     port map (
+      In0(0) => axi_timer_0_interrupt,
+      dout(0) => xlconcat_0_dout(0)
+    );
+end STRUCTURE;
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
index b196236be9f4bab66907b002933eb8dcbdef7ac3..ffdc55f937e95b63cbbcc94cae51f90e2e05854f 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
@@ -97,7 +97,7 @@
             "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -146,7 +146,7 @@
             "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
           },
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
index 18d319d1e141e3ebec8b84f732d08b7007f6aab5..36a40902869c2d663a8f43f16e049f24f99f3e25 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
@@ -7,7 +7,8 @@
       "name": "mb_design_1",
       "rev_ctrl_bd_flag": "RevCtrlBdOff",
       "synth_flow_mode": "Hierarchical",
-      "tool_version": "2024.1.2"
+      "tool_version": "2024.1.2",
+      "validated": "true"
     },
     "design_tree": {
       "microblaze_0": "",
@@ -56,6 +57,26 @@
         "parameters": {
           "ASSOCIATED_RESET": {
             "value": "reset"
+          },
+          "CLK_DOMAIN": {
+            "value": "mb_design_1_clk_in1_0",
+            "value_src": "default"
+          },
+          "FREQ_HZ": {
+            "value": "100000000",
+            "value_src": "default"
+          },
+          "FREQ_TOLERANCE_HZ": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
+          "PHASE": {
+            "value": "0.0",
+            "value_src": "default"
           }
         }
       },
@@ -63,6 +84,10 @@
         "type": "rst",
         "direction": "I",
         "parameters": {
+          "INSERT_VIP": {
+            "value": "0",
+            "value_src": "default"
+          },
           "POLARITY": {
             "value": "ACTIVE_HIGH"
           }