diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd b/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd index 632c5223d709142957d0a7d14625cb39b3dbaf7b..d5059da2086d4a1494d108995ddfe128f9deab87 100644 --- a/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd +++ b/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd @@ -13,26 +13,41 @@ use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity mb_design_1_wrapper is + Generic ( + -- Hog build info + GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0'); + GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0'); + GLOBAL_VER : std_logic_vector(31 downto 0) := (others => '0'); + GLOBAL_SHA : std_logic_vector(31 downto 0) := (others => '0'); + ); port ( GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 ); clk_in1 : in STD_LOGIC; reset : in STD_LOGIC - ); + ); end mb_design_1_wrapper; architecture STRUCTURE of mb_design_1_wrapper is component mb_design_1 is - port ( - clk_in1 : in STD_LOGIC; - reset : in STD_LOGIC; - GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 ) - ); + port ( + GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 ); + clk_in1 : in STD_LOGIC; + reset : in STD_LOGIC; + hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 ) + ); end component mb_design_1; begin -mb_design_1_i: component mb_design_1 - port map ( + mb_design_1_i: component mb_design_1 + port map ( GPIO_0_tri_o(7 downto 0) => GPIO_0_tri_o(7 downto 0), clk_in1 => clk_in1, - reset => reset - ); -end STRUCTURE; \ No newline at end of file + reset => reset, + hog_global_date_i_0 => GLOBAL_DATE, + hog_global_time_i_0 => GLOBAL_TIME, + hog_global_ver_i_0 => GLOBAL_VER, + hog_global_sha_i_0 => GLOBAL_SHA + ); +end STRUCTURE;