diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
index 918c957ee331ec11bf84f5ea0845391d31484830..138254d821a81d62532ec5cc9fc2969b32308211 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
---Date : Thu Mar 20 16:44:45 2025
+--Date : Thu Mar 20 18:24:28 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1_wrapper.bd
--Design : mb_design_1_wrapper
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh
index 5fe8cfc252d36d050afc07119d8c423e3ac86e31..c9d20427db4edb3dd56fcc08285a43df6140725e 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Mar 4 22:34:16 2025" VIVADOVERSION="2024.1.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Mar 20 18:24:29 2025" VIVADOVERSION="2024.1.2">
<SYSTEMINFO ARCH="artix7" BOARD="digilentinc.com:nexys_video:part0:1.2" DEVICE="7a200t" NAME="mb_design_1" PACKAGE="sbg484" SPEEDGRADE="-1"/>
@@ -14,6 +14,26 @@
<CONNECTION INSTANCE="clk_wiz_0" PORT="clk_in1"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_date_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_date_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_date_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_sha_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_sha_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_sha_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_time_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_time_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_time_i"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_ver_i_0" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_ver_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="hog_global_ver_i"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" NAME="reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="External_Ports_reset">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_wiz_0" PORT="reset"/>
@@ -31,6 +51,190 @@
</EXTERNALINTERFACES>
<MODULES>
+ <MODULE COREREVISION="1" FULLNAME="/axi4lite_hog_build_i_0" HWVERSION="1.0" INSTANCE="axi4lite_hog_build_i_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi4lite_hog_build_info" VLNV="xilinx.com:module_ref:axi4lite_hog_build_info:1.0">
+ <DOCUMENTS/>
+ <ADDRESSBLOCKS>
+ <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="0x100000000" USAGE="register"/>
+ </ADDRESSBLOCKS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="Component_Name" VALUE="mb_design_1_axi4lite_hog_build_i_0_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_BASEADDR" VALUE="0x80000000"/>
+ <PARAMETER NAME="C_HIGHADDR" VALUE="0x8000007F"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_date_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_date_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="hog_global_date_i_0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_sha_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_sha_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="hog_global_sha_i_0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_time_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_time_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="hog_global_time_i_0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="hog_global_ver_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_hog_global_ver_i_0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="External_Ports" PORT="hog_global_ver_i_0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="axi_interconnect_0_M04_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="/clk_wiz_0_clk_out1"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="PHASE" VALUE="0.0"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
<MODULE COREREVISION="34" FULLNAME="/axi_gpio_0" HWVERSION="2.0" INSTANCE="axi_gpio_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio" VLNV="xilinx.com:ip:axi_gpio:2.0">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_gpio;v=v2_0;d=pg144-axi-gpio.pdf"/>
@@ -1943,7 +2147,7 @@
</PORT>
<PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_araddr"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
@@ -1953,87 +2157,87 @@
</PORT>
<PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_arready"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_arvalid"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awaddr"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awready"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awvalid"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bready"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bresp"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bvalid"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rdata"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rready"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rresp"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rvalid"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wdata"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wready"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wstrb"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wvalid"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M03_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi_interconnect_0_M02_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_interconnect_0_M03_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="ADDR_WIDTH" VALUE="9"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
@@ -2358,7 +2562,7 @@
<PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
<PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
<PARAMETER NAME="M63_SECURE" VALUE="0"/>
- <PARAMETER NAME="NUM_MI" VALUE="4"/>
+ <PARAMETER NAME="NUM_MI" VALUE="5"/>
<PARAMETER NAME="NUM_SI" VALUE="1"/>
<PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
<PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
@@ -2627,89 +2831,89 @@
<CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
+ <PORT DIR="O" LEFT="31" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
+ <PORT DIR="I" NAME="M02_AXI_arready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
+ <PORT DIR="O" NAME="M02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
+ <PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
+ <PORT DIR="I" NAME="M02_AXI_awready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
+ <PORT DIR="O" NAME="M02_AXI_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
+ <PORT DIR="O" NAME="M02_AXI_bready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
+ <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
+ <PORT DIR="I" NAME="M02_AXI_bvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
+ <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
+ <PORT DIR="O" NAME="M02_AXI_rready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
+ <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
+ <PORT DIR="I" NAME="M02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
+ <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
+ <PORT DIR="I" NAME="M02_AXI_wready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
+ <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wstrb"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
+ <PORT DIR="O" NAME="M02_AXI_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
+ <CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M03_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
@@ -2722,159 +2926,304 @@
<CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M03_AXI_araddr" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_arready" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_arvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_awready" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_rdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_rready" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_rresp" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_rvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="M03_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="O" NAME="M03_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+ <PORT DIR="O" LEFT="31" NAME="M03_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+ <PORT DIR="I" NAME="M03_AXI_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_araddr">
+ <PORT DIR="O" NAME="M03_AXI_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arprot">
+ <PORT DIR="O" LEFT="31" NAME="M03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arready">
+ <PORT DIR="I" NAME="M03_AXI_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arvalid">
+ <PORT DIR="O" NAME="M03_AXI_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awaddr">
+ <PORT DIR="O" NAME="M03_AXI_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awprot">
+ <PORT DIR="I" LEFT="1" NAME="M03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awready">
+ <PORT DIR="I" NAME="M03_AXI_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awvalid">
+ <PORT DIR="I" LEFT="31" NAME="M03_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bready">
+ <PORT DIR="O" NAME="M03_AXI_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bresp">
+ <PORT DIR="I" LEFT="1" NAME="M03_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bvalid">
+ <PORT DIR="I" NAME="M03_AXI_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rdata">
+ <PORT DIR="O" LEFT="31" NAME="M03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rready">
+ <PORT DIR="I" NAME="M03_AXI_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rresp">
+ <PORT DIR="O" LEFT="3" NAME="M03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rvalid">
+ <PORT DIR="O" NAME="M03_AXI_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
+ <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wdata">
+ <PORT DIR="I" NAME="M04_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
+ <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wready">
+ <PORT DIR="I" NAME="M04_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
+ <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wstrb">
+ <PORT DIR="O" LEFT="31" NAME="M04_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wvalid">
+ <PORT DIR="I" NAME="M04_AXI_arready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_arready"/>
</CONNECTIONS>
</PORT>
- </PORTS>
- <BUSINTERFACES>
- <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
- <PORTMAPS>
- <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
- <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
- <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
- <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
- <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
- <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
- <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
- <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
- <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+ <PORT DIR="O" NAME="M04_AXI_arvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M04_AXI_awready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M04_AXI_awvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M04_AXI_bready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M04_AXI_bvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M04_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M04_AXI_rready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M04_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M04_AXI_rvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M04_AXI_wready" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M04_AXI_wvalid" SIGIS="undef" SIGNAME="axi4lite_hog_build_i_0_s_axi_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="clk_wiz_0_clk_100mhz">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="S00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="S00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="S00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="S00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="S00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="S00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="S00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="S00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="S00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="S00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_S00_AXI_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="microblaze_0_M_AXI_DP" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
@@ -2950,51 +3299,390 @@
<PORTMAP LOGICAL="WVALID" PHYSICAL="M02_AXI_wvalid"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="__NOC__" NAME="M03_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_interconnect_0_M03_AXI" DATAWIDTH="32" NAME="M03_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M03_AXI_araddr"/>
- <PORTMAP LOGICAL="ARBURST" PHYSICAL="M03_AXI_arburst"/>
- <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M03_AXI_arcache"/>
- <PORTMAP LOGICAL="ARLEN" PHYSICAL="M03_AXI_arlen"/>
- <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M03_AXI_arlock"/>
- <PORTMAP LOGICAL="ARPROT" PHYSICAL="M03_AXI_arprot"/>
- <PORTMAP LOGICAL="ARQOS" PHYSICAL="M03_AXI_arqos"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M03_AXI_arready"/>
- <PORTMAP LOGICAL="ARREGION" PHYSICAL="M03_AXI_arregion"/>
- <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M03_AXI_arsize"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M03_AXI_arvalid"/>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M03_AXI_awaddr"/>
- <PORTMAP LOGICAL="AWBURST" PHYSICAL="M03_AXI_awburst"/>
- <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M03_AXI_awcache"/>
- <PORTMAP LOGICAL="AWLEN" PHYSICAL="M03_AXI_awlen"/>
- <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M03_AXI_awlock"/>
- <PORTMAP LOGICAL="AWPROT" PHYSICAL="M03_AXI_awprot"/>
- <PORTMAP LOGICAL="AWQOS" PHYSICAL="M03_AXI_awqos"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M03_AXI_awready"/>
- <PORTMAP LOGICAL="AWREGION" PHYSICAL="M03_AXI_awregion"/>
- <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M03_AXI_awsize"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M03_AXI_awvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M03_AXI_bready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M03_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M03_AXI_bvalid"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M03_AXI_rdata"/>
- <PORTMAP LOGICAL="RLAST" PHYSICAL="M03_AXI_rlast"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M03_AXI_rready"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M03_AXI_rresp"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M03_AXI_rvalid"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M03_AXI_wdata"/>
- <PORTMAP LOGICAL="WLAST" PHYSICAL="M03_AXI_wlast"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M03_AXI_wready"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M03_AXI_wstrb"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M03_AXI_wvalid"/>
</PORTMAPS>
</BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_interconnect_0_M04_AXI" DATAWIDTH="32" NAME="M04_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M04_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M04_AXI_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M04_AXI_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M04_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M04_AXI_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M04_AXI_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M04_AXI_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M04_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M04_AXI_bvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M04_AXI_rdata"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M04_AXI_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M04_AXI_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M04_AXI_rvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M04_AXI_wdata"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M04_AXI_wready"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M04_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M04_AXI_wvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE COREREVISION="34" FULLNAME="/axi_timer_0" HWVERSION="2.0" INSTANCE="axi_timer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_timer" VLNV="xilinx.com:ip:axi_timer:2.0">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_timer;v=v2_0;d=pg079-axi-timer.pdf"/>
</DOCUMENTS>
+ <ADDRESSBLOCKS>
+ <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="512" USAGE="register">
+ <REGISTERS>
+ <REGISTER NAME="TCSR0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Control and Status Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="MDT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Mode
0 - Timer mode is generate
1 - Timer mode is capture
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="UDT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Up/Down Count Timer 0
 0 - Timer functions as up counter
 1 - Timer functions as down counter
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="GENT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Generate Signal Timer 0
 0 - Disables external generate signal
 1 - Enables external generate signal
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="CAPT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Capture Trigger Timer 0
 0 - Disables external capture trigger
 1 - Enables external capture trigger
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ARHT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Auto Reload/Hold Timer 0.
When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. 
In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held. 0 = Hold counter or capture value. The TLR must be read before providing the external capture. 1 = Reload generate value or overwrite capture value
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="LOAD0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Load Timer 0 0 = No load 1 = Loads timer with value in TLR0 Setting this bit loads timer/counter register (TCR0) with a specified value in the timer/counter load register (TLR0). This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT0) bit in TCSR0.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ENIT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable Interrupt for Timer 0
Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T0INT) in TCSR0. 0 - Disable interrupt signal 1 - Enable interrupt signal
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ENT0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable Timer 0
 0 - Disable timer (counter halts)
 1 - Enable timer (counter runs)
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="T0INT">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Interrupt
Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.
Read: 0 - No interrupt has occurred 1 - Interrupt has occurred Write: 0 - No change in state of T0INT 1 - Clear T0INT (clear to 0)
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="PWMA0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable Pulse Width Modulation for Timer 0 0 - Disable pulse width modulation 1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0 and C_GEN0_ASSERT and C_GEN1_ASSERT must be 1.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ENALL">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable All Timers 0 - No effect on timers 1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. 
Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="CASC">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable cascade mode of timers 0 - Disable cascaded operation 1 - Enable cascaded operation Cascaded operation requires using Timer 0 and Timer 1 together as a pair. The counting event for the Timer 1 is when the Timer 0 rolls over from all 1s to all 0s or vice-versa when counting down.
TLR0 and TLR1 are used for lower 32-bit and higher 32-bit respectively. Similarly, TCR0 contains lower 32-bits for the 64-bit counter and TCR1 contains the higher 32-bits.
Only TCSR0 is valid for both the timer/counters in this mode.
This CASC bit must be set before enabling the timer/counter.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TLR0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Load Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TCLR0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Load Register
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TCR0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 0 Counter Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TCR0">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Register
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TCSR1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Control and Status Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="MDT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Mode
 0 - Timer mode is generate
 1 - Timer mode is capture
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="UDT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Up/Down Count Timer 1
 0 - Timer functions as up counter
 1 - Timer functions as down counter
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="GENT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Generate Signal Timer 1
 0 - Disables external generate signal
 1 - Enables external generate signal
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="CAPT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable External Capture Trigger Timer 1
 0 - Disables external capture trigger
 1 - Enables external capture trigger
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ARHT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Auto Reload/Hold Timer 1.
When the timer is in Generate mode, this bit determines whether the counter reloads the generate value and continues running or holds at the termination value. 
In Capture mode, this bit determines whether a new capture trigger overwrites the previous captured value or if the previous value is held.
0 = Hold counter or capture value. The TLR must be read before providing the external capture. 
1 = Reload generate value or overwrite capture value
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="LOAD1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Load Timer 1 0 = No load 1 = Loads timer with value in TLR1 Setting this bit loads timer/counter register (TCR1) with a specified value in the timer/counter load register (TLR1). This bit prevents the running of the timer/counter; hence, this should be cleared alongside setting Enable Timer/ Counter (ENT1) bit in TCSR1.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ENIT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable Interrupt for Timer 1
Enables the assertion of the interrupt signal for this timer. Has no effect on the interrupt flag (T1INT) in TCSR1. 0 - Disable interrupt signal 1 - Enable interrupt signal
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ENT1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable Timer 1
 0 - Disable timer (counter halts)
 1 - Enable timer (counter runs)
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="T1INT">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Interrupt
Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1.
Read: 0 - No interrupt has occurred 1 - Interrupt has occurred Write: 0 - No change in state of T0INT 1 - Clear T1INT (clear to 0)
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="PWMA1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable Pulse Width Modulation for Timer 1 0 - Disable pulse width modulation 1 - Enable pulse width modulation PWM requires using Timer 0 and Timer 1 together as a pair. Timer 0 sets the period of the PWM output, and Timer 1 sets the high time for the PWM output. For PWM mode, MDT0 and MDT1 must be 0.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="ENALL">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Enable All Timers 0 - No effect on timers 1 - Enable all timers (counters run) This bit is mirrored in all control/status registers and is used to enable all counters simultaneously. Writing a 1 to this bit sets ENALL, ENT0, and ENT1. Writing a 0 to this register clears ENALL but has no effect on ENT0 and ENT1. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TLR1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Load Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TCLR1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Load Register
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="TCR1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer 1 Counter Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="TCR1">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Timer/Counter Register
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ </REGISTERS>
+ </ADDRESSBLOCK>
+ </ADDRESSBLOCKS>
<PARAMETERS>
<PARAMETER NAME="C_COUNT_WIDTH" VALUE="32"/>
<PARAMETER NAME="C_FAMILY" VALUE="artix7"/>
@@ -3014,6 +3702,8 @@
<PARAMETER NAME="enable_timer2" VALUE="0"/>
<PARAMETER NAME="mode_64bit" VALUE="0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_BASEADDR" VALUE="0x41C00000"/>
+ <PARAMETER NAME="C_HIGHADDR" VALUE="0x41C0FFFF"/>
</PARAMETERS>
<PORTS>
<PORT DIR="I" NAME="capturetrig0" SIGIS="undef"/>
@@ -3032,31 +3722,99 @@
<CONNECTION INSTANCE="clk_wiz_0" PORT="clk_100mhz"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="4" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_0_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="proc_sys_reset_0" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef"/>
- <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef"/>
- <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef"/>
- <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="4" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_interconnect_0_M02_AXI_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M02_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
</PORTS>
<BUSINTERFACES>
- <BUSINTERFACE BUSNAME="__NOC__" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_interconnect_0_M02_AXI" DATAWIDTH="32" NAME="S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="ADDR_WIDTH" VALUE="5"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
@@ -3076,9 +3834,9 @@
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
- <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
- <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
@@ -3975,6 +4733,8 @@
<CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aclk"/>
<CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aclk"/>
<CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aclk"/>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_aclk"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_ACLK"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="100000000" DIR="I" NAME="clk_in1" SIGIS="clk" SIGNAME="External_Ports_clk_in1">
@@ -4017,7 +4777,7 @@
<PARAMETER NAME="C_LMB_AWIDTH" VALUE="32"/>
<PARAMETER NAME="C_LMB_DWIDTH" VALUE="32"/>
<PARAMETER NAME="C_LMB_PROTOCOL" VALUE="0"/>
- <PARAMETER NAME="C_MASK" VALUE="0x0000000040000000"/>
+ <PARAMETER NAME="C_MASK" VALUE="0x00000000c0000000"/>
<PARAMETER NAME="C_MASK1" VALUE="0x0000000000800000"/>
<PARAMETER NAME="C_MASK2" VALUE="0x0000000000800000"/>
<PARAMETER NAME="C_MASK3" VALUE="0x0000000000800000"/>
@@ -6331,6 +7091,8 @@
<MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000FFFF" INSTANCE="axi_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
<MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41200000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4120FFFF" INSTANCE="axi_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
<MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41400000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41400FFF" INSTANCE="mdm_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
+ <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41C00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41C0FFFF" INSTANCE="axi_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI"/>
+ <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8000007F" INSTANCE="axi4lite_hog_build_i_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" MASTERBUSINTERFACE="M_AXI_DP" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
</MEMORYMAP>
<PERIPHERALS>
<PERIPHERAL INSTANCE="dlmb_bram_if_cntlr_0"/>
@@ -6338,6 +7100,8 @@
<PERIPHERAL INSTANCE="axi_gpio_0"/>
<PERIPHERAL INSTANCE="axi_intc_0"/>
<PERIPHERAL INSTANCE="mdm_0"/>
+ <PERIPHERAL INSTANCE="axi_timer_0"/>
+ <PERIPHERAL INSTANCE="axi4lite_hog_build_i_0"/>
</PERIPHERALS>
</MODULE>
<MODULE COREREVISION="15" FULLNAME="/proc_sys_reset_0" HWVERSION="5.0" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
@@ -6405,6 +7169,8 @@
<CONNECTION INSTANCE="axi_gpio_0" PORT="s_axi_aresetn"/>
<CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aresetn"/>
<CONNECTION INSTANCE="axi_timer_0" PORT="s_axi_aresetn"/>
+ <CONNECTION INSTANCE="axi4lite_hog_build_i_0" PORT="s_axi_aresetn"/>
+ <CONNECTION INSTANCE="axi_interconnect_0" PORT="M04_ARESETN"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.dcp b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..ddc6d963be77a4e8bc180cc53757e88ee9854196
Binary files /dev/null and b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.dcp differ
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
index aa0b815b2ad5afc75307993cf62797ed8be29e6a..86e2c7b81f79ed55dd8d089c46694228b3c67533 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
@@ -559,6 +559,101 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:modelName>axi4lite_hog_build_info</spirit:modelName>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:216bf9af</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:modelName>axi4lite_hog_build_info</spirit:modelName>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:12918eb6</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_externalfiles</spirit:name>
+ <spirit:displayName>External Files</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Thu Mar 20 16:31:20 UTC 2025</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:12918eb6</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_synthesisconstraints</spirit:name>
+ <spirit:displayName>Synthesis Constraints</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:12918eb6</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
+ <spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>mb_design_1_axi4lite_hog_build_i_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:216bf9af</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
+ <spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>mb_design_1_axi4lite_hog_build_i_0_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>GENtimestamp</spirit:name>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>outputProductCRC</spirit:name>
+ <spirit:value>9:12918eb6</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>s_axi_aclk</spirit:name>
@@ -567,7 +662,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -579,7 +675,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -595,7 +692,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -610,7 +708,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -625,7 +724,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -641,7 +741,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -660,7 +761,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -675,7 +777,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -690,7 +793,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -706,7 +810,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -718,7 +823,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -730,7 +836,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -749,7 +856,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -764,7 +872,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -779,7 +888,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -795,7 +905,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -811,7 +922,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -823,7 +935,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -835,7 +948,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -854,7 +968,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -870,7 +985,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -886,7 +1002,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -902,7 +1019,8 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
- <spirit:viewNameRef>dummy_view</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -923,6 +1041,60 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axi4lite_hog_build_info:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
new file mode 100644
index 0000000000000000000000000000000000000000..80b954e6478908189231cdd54053b4db5f68f114
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
@@ -0,0 +1,2225 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Mar 20 18:25:04 2025
+// Host : hogtest running 64-bit unknown
+// Command : write_verilog -force -mode funcsim
+// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
+// Design : mb_design_1_axi4lite_hog_build_i_0_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
+(* x_core_info = "axi4lite_hog_build_info,Vivado 2024.1.2" *)
+(* NotValidForBitStream *)
+module mb_design_1_axi4lite_hog_build_i_0_0
+ (s_axi_aclk,
+ s_axi_aresetn,
+ s_axi_awaddr,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_araddr,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rvalid,
+ s_axi_rready,
+ hog_global_date_i,
+ hog_global_time_i,
+ hog_global_ver_i,
+ hog_global_sha_i);
+ (* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
+ (* x_interface_info = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]s_axi_awaddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [31:0]s_axi_araddr;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) output [31:0]s_axi_rdata;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
+ (* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
+ input [31:0]hog_global_date_i;
+ input [31:0]hog_global_time_i;
+ input [31:0]hog_global_ver_i;
+ input [31:0]hog_global_sha_i;
+
+ wire \<const0> ;
+ wire [31:0]hog_global_date_i;
+ wire [31:0]hog_global_sha_i;
+ wire [31:0]hog_global_time_i;
+ wire [31:0]hog_global_ver_i;
+ wire s_axi_aclk;
+ wire [31:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arready;
+ wire s_axi_arvalid;
+ wire s_axi_awready;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_bvalid;
+ wire [31:0]s_axi_rdata;
+ wire s_axi_rready;
+ wire s_axi_rvalid;
+ wire s_axi_wready;
+ wire s_axi_wvalid;
+
+ assign s_axi_bresp[1] = \<const0> ;
+ assign s_axi_bresp[0] = \<const0> ;
+ assign s_axi_rresp[1] = \<const0> ;
+ assign s_axi_rresp[0] = \<const0> ;
+ GND GND
+ (.G(\<const0> ));
+ mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info U0
+ (.hog_global_date_i(hog_global_date_i),
+ .hog_global_sha_i(hog_global_sha_i),
+ .hog_global_time_i(hog_global_time_i),
+ .hog_global_ver_i(hog_global_ver_i),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arready_s_reg(s_axi_arready),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_rdata(s_axi_rdata),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_hog_build_info" *)
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info
+ (s_axi_wready,
+ s_axi_awready,
+ s_axi_rdata,
+ s_axi_arready_s_reg,
+ s_axi_bvalid,
+ s_axi_rvalid,
+ s_axi_aclk,
+ s_axi_awvalid,
+ s_axi_wvalid,
+ s_axi_rready,
+ s_axi_aresetn,
+ s_axi_arvalid,
+ s_axi_araddr,
+ hog_global_ver_i,
+ hog_global_sha_i,
+ hog_global_date_i,
+ hog_global_time_i,
+ s_axi_bready);
+ output s_axi_wready;
+ output s_axi_awready;
+ output [31:0]s_axi_rdata;
+ output s_axi_arready_s_reg;
+ output s_axi_bvalid;
+ output s_axi_rvalid;
+ input s_axi_aclk;
+ input s_axi_awvalid;
+ input s_axi_wvalid;
+ input s_axi_rready;
+ input s_axi_aresetn;
+ input s_axi_arvalid;
+ input [31:0]s_axi_araddr;
+ input [31:0]hog_global_ver_i;
+ input [31:0]hog_global_sha_i;
+ input [31:0]hog_global_date_i;
+ input [31:0]hog_global_time_i;
+ input s_axi_bready;
+
+ wire [31:0]hog_global_date_i;
+ wire [31:0]hog_global_sha_i;
+ wire [31:0]hog_global_time_i;
+ wire [31:0]hog_global_ver_i;
+ wire p_0_in;
+ wire [31:0]p_1_in;
+ wire rd_valid_s;
+ wire s_axi_aclk;
+ wire [31:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arready_s_reg;
+ wire s_axi_arvalid;
+ wire s_axi_awready;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_bvalid;
+ wire [31:0]s_axi_rdata;
+ wire s_axi_rready;
+ wire s_axi_rvalid;
+ wire s_axi_wready;
+ wire s_axi_wvalid;
+
+ mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if axi4lite_if_inst
+ (.D(p_1_in),
+ .E(rd_valid_s),
+ .SR(p_0_in),
+ .hog_global_date_i(hog_global_date_i),
+ .hog_global_sha_i(hog_global_sha_i),
+ .hog_global_time_i(hog_global_time_i),
+ .hog_global_ver_i(hog_global_ver_i),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_arready_s_reg(s_axi_arready_s_reg),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_wvalid(s_axi_wvalid));
+ mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs hog_build_info_regs_inst
+ (.D(p_1_in),
+ .E(rd_valid_s),
+ .SR(p_0_in),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_rdata(s_axi_rdata));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_if" *)
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if
+ (s_axi_wready,
+ SR,
+ s_axi_awready,
+ s_axi_bvalid,
+ s_axi_arready_s_reg,
+ s_axi_rvalid,
+ D,
+ E,
+ s_axi_aclk,
+ s_axi_wvalid,
+ s_axi_bready,
+ s_axi_awvalid,
+ s_axi_arvalid,
+ s_axi_rready,
+ s_axi_aresetn,
+ s_axi_araddr,
+ hog_global_ver_i,
+ hog_global_sha_i,
+ hog_global_date_i,
+ hog_global_time_i);
+ output s_axi_wready;
+ output [0:0]SR;
+ output s_axi_awready;
+ output s_axi_bvalid;
+ output s_axi_arready_s_reg;
+ output s_axi_rvalid;
+ output [31:0]D;
+ output [0:0]E;
+ input s_axi_aclk;
+ input s_axi_wvalid;
+ input s_axi_bready;
+ input s_axi_awvalid;
+ input s_axi_arvalid;
+ input s_axi_rready;
+ input s_axi_aresetn;
+ input [31:0]s_axi_araddr;
+ input [31:0]hog_global_ver_i;
+ input [31:0]hog_global_sha_i;
+ input [31:0]hog_global_date_i;
+ input [31:0]hog_global_time_i;
+
+ wire [31:0]D;
+ wire [0:0]E;
+ wire [0:0]SR;
+ wire [31:0]hog_global_date_i;
+ wire [31:0]hog_global_sha_i;
+ wire [31:0]hog_global_time_i;
+ wire [31:0]hog_global_ver_i;
+ wire s_axi_aclk;
+ wire [31:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_arready_s_reg;
+ wire s_axi_arvalid;
+ wire s_axi_awready;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_bvalid;
+ wire s_axi_rready;
+ wire s_axi_rvalid;
+ wire s_axi_wready;
+ wire s_axi_wvalid;
+
+ mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if axi4lite_rd_channel_if_i
+ (.D(D),
+ .E(E),
+ .hog_global_date_i(hog_global_date_i),
+ .hog_global_sha_i(hog_global_sha_i),
+ .hog_global_time_i(hog_global_time_i),
+ .hog_global_ver_i(hog_global_ver_i),
+ .s_axi_aclk(s_axi_aclk),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_aresetn(s_axi_aresetn),
+ .s_axi_aresetn_0(SR),
+ .s_axi_arready_s_reg_0(s_axi_arready_s_reg),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rvalid(s_axi_rvalid));
+ mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if axi4lite_wr_channel_if_i
+ (.s_axi_aclk(s_axi_aclk),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awready_s_reg_0(SR),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_wvalid(s_axi_wvalid));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_rd_channel_if" *)
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if
+ (s_axi_aresetn_0,
+ s_axi_arready_s_reg_0,
+ s_axi_rvalid,
+ D,
+ E,
+ s_axi_aclk,
+ s_axi_arvalid,
+ s_axi_rready,
+ s_axi_aresetn,
+ s_axi_araddr,
+ hog_global_ver_i,
+ hog_global_sha_i,
+ hog_global_date_i,
+ hog_global_time_i);
+ output s_axi_aresetn_0;
+ output s_axi_arready_s_reg_0;
+ output s_axi_rvalid;
+ output [31:0]D;
+ output [0:0]E;
+ input s_axi_aclk;
+ input s_axi_arvalid;
+ input s_axi_rready;
+ input s_axi_aresetn;
+ input [31:0]s_axi_araddr;
+ input [31:0]hog_global_ver_i;
+ input [31:0]hog_global_sha_i;
+ input [31:0]hog_global_date_i;
+ input [31:0]hog_global_time_i;
+
+ wire [31:0]D;
+ wire [0:0]E;
+ wire [31:0]addr_s;
+ wire \addr_s[0]_i_1_n_0 ;
+ wire \addr_s[10]_i_1_n_0 ;
+ wire \addr_s[11]_i_1_n_0 ;
+ wire \addr_s[12]_i_1_n_0 ;
+ wire \addr_s[13]_i_1_n_0 ;
+ wire \addr_s[14]_i_1_n_0 ;
+ wire \addr_s[15]_i_1_n_0 ;
+ wire \addr_s[16]_i_1_n_0 ;
+ wire \addr_s[17]_i_1_n_0 ;
+ wire \addr_s[18]_i_1_n_0 ;
+ wire \addr_s[19]_i_1_n_0 ;
+ wire \addr_s[1]_i_1_n_0 ;
+ wire \addr_s[20]_i_1_n_0 ;
+ wire \addr_s[21]_i_1_n_0 ;
+ wire \addr_s[22]_i_1_n_0 ;
+ wire \addr_s[23]_i_1_n_0 ;
+ wire \addr_s[24]_i_1_n_0 ;
+ wire \addr_s[25]_i_1_n_0 ;
+ wire \addr_s[26]_i_1_n_0 ;
+ wire \addr_s[27]_i_1_n_0 ;
+ wire \addr_s[28]_i_1_n_0 ;
+ wire \addr_s[29]_i_1_n_0 ;
+ wire \addr_s[2]_i_1_n_0 ;
+ wire \addr_s[30]_i_1_n_0 ;
+ wire \addr_s[31]_i_1_n_0 ;
+ wire \addr_s[3]_i_1_n_0 ;
+ wire \addr_s[4]_i_1_n_0 ;
+ wire \addr_s[5]_i_1_n_0 ;
+ wire \addr_s[6]_i_1_n_0 ;
+ wire \addr_s[7]_i_1_n_0 ;
+ wire \addr_s[8]_i_1_n_0 ;
+ wire \addr_s[9]_i_1_n_0 ;
+ wire [31:0]hog_global_date_i;
+ wire [31:0]hog_global_sha_i;
+ wire [31:0]hog_global_time_i;
+ wire [31:0]hog_global_ver_i;
+ wire rd_addr_latched;
+ wire rd_addr_latched_i_1_n_0;
+ wire \rd_data_s[0]_i_2_n_0 ;
+ wire \rd_data_s[10]_i_2_n_0 ;
+ wire \rd_data_s[11]_i_2_n_0 ;
+ wire \rd_data_s[12]_i_2_n_0 ;
+ wire \rd_data_s[13]_i_2_n_0 ;
+ wire \rd_data_s[14]_i_2_n_0 ;
+ wire \rd_data_s[15]_i_2_n_0 ;
+ wire \rd_data_s[16]_i_2_n_0 ;
+ wire \rd_data_s[17]_i_2_n_0 ;
+ wire \rd_data_s[18]_i_2_n_0 ;
+ wire \rd_data_s[19]_i_2_n_0 ;
+ wire \rd_data_s[1]_i_2_n_0 ;
+ wire \rd_data_s[20]_i_2_n_0 ;
+ wire \rd_data_s[21]_i_2_n_0 ;
+ wire \rd_data_s[22]_i_2_n_0 ;
+ wire \rd_data_s[23]_i_2_n_0 ;
+ wire \rd_data_s[24]_i_2_n_0 ;
+ wire \rd_data_s[25]_i_2_n_0 ;
+ wire \rd_data_s[26]_i_2_n_0 ;
+ wire \rd_data_s[27]_i_2_n_0 ;
+ wire \rd_data_s[28]_i_2_n_0 ;
+ wire \rd_data_s[29]_i_2_n_0 ;
+ wire \rd_data_s[2]_i_2_n_0 ;
+ wire \rd_data_s[30]_i_2_n_0 ;
+ wire \rd_data_s[31]_i_10_n_0 ;
+ wire \rd_data_s[31]_i_11_n_0 ;
+ wire \rd_data_s[31]_i_12_n_0 ;
+ wire \rd_data_s[31]_i_13_n_0 ;
+ wire \rd_data_s[31]_i_14_n_0 ;
+ wire \rd_data_s[31]_i_15_n_0 ;
+ wire \rd_data_s[31]_i_16_n_0 ;
+ wire \rd_data_s[31]_i_17_n_0 ;
+ wire \rd_data_s[31]_i_18_n_0 ;
+ wire \rd_data_s[31]_i_19_n_0 ;
+ wire \rd_data_s[31]_i_20_n_0 ;
+ wire \rd_data_s[31]_i_21_n_0 ;
+ wire \rd_data_s[31]_i_22_n_0 ;
+ wire \rd_data_s[31]_i_3_n_0 ;
+ wire \rd_data_s[31]_i_4_n_0 ;
+ wire \rd_data_s[31]_i_5_n_0 ;
+ wire \rd_data_s[31]_i_6_n_0 ;
+ wire \rd_data_s[31]_i_7_n_0 ;
+ wire \rd_data_s[31]_i_8_n_0 ;
+ wire \rd_data_s[31]_i_9_n_0 ;
+ wire \rd_data_s[3]_i_2_n_0 ;
+ wire \rd_data_s[4]_i_2_n_0 ;
+ wire \rd_data_s[5]_i_2_n_0 ;
+ wire \rd_data_s[6]_i_2_n_0 ;
+ wire \rd_data_s[7]_i_2_n_0 ;
+ wire \rd_data_s[8]_i_2_n_0 ;
+ wire \rd_data_s[9]_i_2_n_0 ;
+ wire s_axi_aclk;
+ wire [31:0]s_axi_araddr;
+ wire s_axi_aresetn;
+ wire s_axi_aresetn_0;
+ wire s_axi_arready_s_i_1_n_0;
+ wire s_axi_arready_s_reg_0;
+ wire s_axi_arvalid;
+ wire s_axi_rready;
+ wire s_axi_rvalid;
+ wire s_axi_rvalid_s_i_1_n_0;
+
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[0]_i_1
+ (.I0(addr_s[0]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[0]),
+ .O(\addr_s[0]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[10]_i_1
+ (.I0(addr_s[10]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[10]),
+ .O(\addr_s[10]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[11]_i_1
+ (.I0(addr_s[11]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[11]),
+ .O(\addr_s[11]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[12]_i_1
+ (.I0(addr_s[12]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[12]),
+ .O(\addr_s[12]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[13]_i_1
+ (.I0(addr_s[13]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[13]),
+ .O(\addr_s[13]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[14]_i_1
+ (.I0(addr_s[14]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[14]),
+ .O(\addr_s[14]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[15]_i_1
+ (.I0(addr_s[15]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[15]),
+ .O(\addr_s[15]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[16]_i_1
+ (.I0(addr_s[16]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[16]),
+ .O(\addr_s[16]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[17]_i_1
+ (.I0(addr_s[17]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[17]),
+ .O(\addr_s[17]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[18]_i_1
+ (.I0(addr_s[18]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[18]),
+ .O(\addr_s[18]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[19]_i_1
+ (.I0(addr_s[19]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[19]),
+ .O(\addr_s[19]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[1]_i_1
+ (.I0(addr_s[1]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[1]),
+ .O(\addr_s[1]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[20]_i_1
+ (.I0(addr_s[20]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[20]),
+ .O(\addr_s[20]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[21]_i_1
+ (.I0(addr_s[21]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[21]),
+ .O(\addr_s[21]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[22]_i_1
+ (.I0(addr_s[22]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[22]),
+ .O(\addr_s[22]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[23]_i_1
+ (.I0(addr_s[23]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[23]),
+ .O(\addr_s[23]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[24]_i_1
+ (.I0(addr_s[24]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[24]),
+ .O(\addr_s[24]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[25]_i_1
+ (.I0(addr_s[25]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[25]),
+ .O(\addr_s[25]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[26]_i_1
+ (.I0(addr_s[26]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[26]),
+ .O(\addr_s[26]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[27]_i_1
+ (.I0(addr_s[27]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[27]),
+ .O(\addr_s[27]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[28]_i_1
+ (.I0(addr_s[28]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[28]),
+ .O(\addr_s[28]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[29]_i_1
+ (.I0(addr_s[29]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[29]),
+ .O(\addr_s[29]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hBF80))
+ \addr_s[2]_i_1
+ (.I0(s_axi_araddr[2]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_arready_s_reg_0),
+ .I3(addr_s[2]),
+ .O(\addr_s[2]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hBF80))
+ \addr_s[30]_i_1
+ (.I0(s_axi_araddr[30]),
+ .I1(s_axi_arvalid),
+ .I2(s_axi_arready_s_reg_0),
+ .I3(addr_s[30]),
+ .O(\addr_s[30]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[31]_i_1
+ (.I0(addr_s[31]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[31]),
+ .O(\addr_s[31]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[3]_i_1
+ (.I0(addr_s[3]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[3]),
+ .O(\addr_s[3]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[4]_i_1
+ (.I0(addr_s[4]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[4]),
+ .O(\addr_s[4]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[5]_i_1
+ (.I0(addr_s[5]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[5]),
+ .O(\addr_s[5]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[6]_i_1
+ (.I0(addr_s[6]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[6]),
+ .O(\addr_s[6]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[7]_i_1
+ (.I0(addr_s[7]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[7]),
+ .O(\addr_s[7]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[8]_i_1
+ (.I0(addr_s[8]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[8]),
+ .O(\addr_s[8]_i_1_n_0 ));
+ LUT4 #(
+ .INIT(16'hEA2A))
+ \addr_s[9]_i_1
+ (.I0(addr_s[9]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[9]),
+ .O(\addr_s[9]_i_1_n_0 ));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[0]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[0]_i_1_n_0 ),
+ .Q(addr_s[0]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[10]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[10]_i_1_n_0 ),
+ .Q(addr_s[10]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[11]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[11]_i_1_n_0 ),
+ .Q(addr_s[11]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[12]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[12]_i_1_n_0 ),
+ .Q(addr_s[12]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[13]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[13]_i_1_n_0 ),
+ .Q(addr_s[13]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[14]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[14]_i_1_n_0 ),
+ .Q(addr_s[14]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[15]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[15]_i_1_n_0 ),
+ .Q(addr_s[15]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[16]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[16]_i_1_n_0 ),
+ .Q(addr_s[16]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[17]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[17]_i_1_n_0 ),
+ .Q(addr_s[17]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[18]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[18]_i_1_n_0 ),
+ .Q(addr_s[18]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[19]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[19]_i_1_n_0 ),
+ .Q(addr_s[19]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[1]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[1]_i_1_n_0 ),
+ .Q(addr_s[1]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[20]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[20]_i_1_n_0 ),
+ .Q(addr_s[20]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[21]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[21]_i_1_n_0 ),
+ .Q(addr_s[21]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[22]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[22]_i_1_n_0 ),
+ .Q(addr_s[22]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[23]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[23]_i_1_n_0 ),
+ .Q(addr_s[23]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[24]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[24]_i_1_n_0 ),
+ .Q(addr_s[24]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[25]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[25]_i_1_n_0 ),
+ .Q(addr_s[25]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[26]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[26]_i_1_n_0 ),
+ .Q(addr_s[26]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[27]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[27]_i_1_n_0 ),
+ .Q(addr_s[27]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[28]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[28]_i_1_n_0 ),
+ .Q(addr_s[28]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[29]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[29]_i_1_n_0 ),
+ .Q(addr_s[29]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[2]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[2]_i_1_n_0 ),
+ .Q(addr_s[2]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[30]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[30]_i_1_n_0 ),
+ .Q(addr_s[30]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[31]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[31]_i_1_n_0 ),
+ .Q(addr_s[31]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[3]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[3]_i_1_n_0 ),
+ .Q(addr_s[3]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[4]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[4]_i_1_n_0 ),
+ .Q(addr_s[4]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[5]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[5]_i_1_n_0 ),
+ .Q(addr_s[5]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[6]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[6]_i_1_n_0 ),
+ .Q(addr_s[6]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[7]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[7]_i_1_n_0 ),
+ .Q(addr_s[7]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[8]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[8]_i_1_n_0 ),
+ .Q(addr_s[8]),
+ .R(s_axi_aresetn_0));
+ FDRE #(
+ .INIT(1'b0))
+ \addr_s_reg[9]
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(\addr_s[9]_i_1_n_0 ),
+ .Q(addr_s[9]),
+ .R(s_axi_aresetn_0));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'hEFAA))
+ rd_addr_latched_i_1
+ (.I0(s_axi_arvalid),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_rready),
+ .I3(rd_addr_latched),
+ .O(rd_addr_latched_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ rd_addr_latched_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(rd_addr_latched_i_1_n_0),
+ .Q(rd_addr_latched),
+ .R(s_axi_aresetn_0));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[0]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[0]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[0]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[0]_i_2
+ (.I0(hog_global_ver_i[0]),
+ .I1(hog_global_sha_i[0]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[0]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[0]),
+ .O(\rd_data_s[0]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[10]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[10]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[10]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[10]_i_2
+ (.I0(hog_global_ver_i[10]),
+ .I1(hog_global_sha_i[10]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[10]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[10]),
+ .O(\rd_data_s[10]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[11]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[11]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[11]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[11]_i_2
+ (.I0(hog_global_ver_i[11]),
+ .I1(hog_global_sha_i[11]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[11]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[11]),
+ .O(\rd_data_s[11]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[12]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[12]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[12]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[12]_i_2
+ (.I0(hog_global_ver_i[12]),
+ .I1(hog_global_sha_i[12]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[12]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[12]),
+ .O(\rd_data_s[12]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[13]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[13]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[13]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[13]_i_2
+ (.I0(hog_global_ver_i[13]),
+ .I1(hog_global_sha_i[13]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[13]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[13]),
+ .O(\rd_data_s[13]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[14]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[14]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[14]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[14]_i_2
+ (.I0(hog_global_ver_i[14]),
+ .I1(hog_global_sha_i[14]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[14]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[14]),
+ .O(\rd_data_s[14]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[15]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[15]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[15]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[15]_i_2
+ (.I0(hog_global_ver_i[15]),
+ .I1(hog_global_sha_i[15]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[15]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[15]),
+ .O(\rd_data_s[15]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[16]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[16]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[16]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[16]_i_2
+ (.I0(hog_global_ver_i[16]),
+ .I1(hog_global_sha_i[16]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[16]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[16]),
+ .O(\rd_data_s[16]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[17]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[17]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[17]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[17]_i_2
+ (.I0(hog_global_ver_i[17]),
+ .I1(hog_global_sha_i[17]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[17]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[17]),
+ .O(\rd_data_s[17]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[18]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[18]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[18]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[18]_i_2
+ (.I0(hog_global_ver_i[18]),
+ .I1(hog_global_sha_i[18]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[18]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[18]),
+ .O(\rd_data_s[18]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[19]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[19]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[19]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[19]_i_2
+ (.I0(hog_global_ver_i[19]),
+ .I1(hog_global_sha_i[19]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[19]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[19]),
+ .O(\rd_data_s[19]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[1]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[1]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[1]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[1]_i_2
+ (.I0(hog_global_ver_i[1]),
+ .I1(hog_global_sha_i[1]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[1]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[1]),
+ .O(\rd_data_s[1]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[20]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[20]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[20]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[20]_i_2
+ (.I0(hog_global_ver_i[20]),
+ .I1(hog_global_sha_i[20]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[20]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[20]),
+ .O(\rd_data_s[20]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[21]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[21]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[21]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[21]_i_2
+ (.I0(hog_global_ver_i[21]),
+ .I1(hog_global_sha_i[21]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[21]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[21]),
+ .O(\rd_data_s[21]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[22]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[22]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[22]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[22]_i_2
+ (.I0(hog_global_ver_i[22]),
+ .I1(hog_global_sha_i[22]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[22]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[22]),
+ .O(\rd_data_s[22]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[23]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[23]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[23]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[23]_i_2
+ (.I0(hog_global_ver_i[23]),
+ .I1(hog_global_sha_i[23]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[23]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[23]),
+ .O(\rd_data_s[23]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[24]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[24]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[24]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[24]_i_2
+ (.I0(hog_global_ver_i[24]),
+ .I1(hog_global_sha_i[24]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[24]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[24]),
+ .O(\rd_data_s[24]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[25]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[25]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[25]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[25]_i_2
+ (.I0(hog_global_ver_i[25]),
+ .I1(hog_global_sha_i[25]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[25]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[25]),
+ .O(\rd_data_s[25]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[26]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[26]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[26]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[26]_i_2
+ (.I0(hog_global_ver_i[26]),
+ .I1(hog_global_sha_i[26]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[26]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[26]),
+ .O(\rd_data_s[26]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[27]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[27]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[27]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[27]_i_2
+ (.I0(hog_global_ver_i[27]),
+ .I1(hog_global_sha_i[27]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[27]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[27]),
+ .O(\rd_data_s[27]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[28]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[28]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[28]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[28]_i_2
+ (.I0(hog_global_ver_i[28]),
+ .I1(hog_global_sha_i[28]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[28]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[28]),
+ .O(\rd_data_s[28]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[29]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[29]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[29]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[29]_i_2
+ (.I0(hog_global_ver_i[29]),
+ .I1(hog_global_sha_i[29]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[29]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[29]),
+ .O(\rd_data_s[29]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[2]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[2]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[2]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[2]_i_2
+ (.I0(hog_global_ver_i[2]),
+ .I1(hog_global_sha_i[2]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[2]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[2]),
+ .O(\rd_data_s[2]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[30]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[30]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[30]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[30]_i_2
+ (.I0(hog_global_ver_i[30]),
+ .I1(hog_global_sha_i[30]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[30]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[30]),
+ .O(\rd_data_s[30]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \rd_data_s[31]_i_1
+ (.I0(s_axi_arvalid),
+ .I1(s_axi_arready_s_reg_0),
+ .O(E));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_10
+ (.I0(s_axi_araddr[18]),
+ .I1(addr_s[18]),
+ .I2(s_axi_araddr[17]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[17]),
+ .O(\rd_data_s[31]_i_10_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_11
+ (.I0(s_axi_araddr[14]),
+ .I1(addr_s[14]),
+ .I2(s_axi_araddr[13]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[13]),
+ .O(\rd_data_s[31]_i_11_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_12
+ (.I0(s_axi_araddr[27]),
+ .I1(addr_s[27]),
+ .I2(s_axi_araddr[24]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[24]),
+ .O(\rd_data_s[31]_i_12_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_13
+ (.I0(s_axi_araddr[7]),
+ .I1(addr_s[7]),
+ .I2(s_axi_araddr[6]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[6]),
+ .O(\rd_data_s[31]_i_13_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_14
+ (.I0(s_axi_araddr[23]),
+ .I1(addr_s[23]),
+ .I2(s_axi_araddr[5]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[5]),
+ .O(\rd_data_s[31]_i_14_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_15
+ (.I0(s_axi_araddr[22]),
+ .I1(addr_s[22]),
+ .I2(s_axi_araddr[4]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[4]),
+ .O(\rd_data_s[31]_i_15_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_16
+ (.I0(s_axi_araddr[31]),
+ .I1(addr_s[31]),
+ .I2(s_axi_araddr[20]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[20]),
+ .O(\rd_data_s[31]_i_16_n_0 ));
+ LUT6 #(
+ .INIT(64'h0500000005333333))
+ \rd_data_s[31]_i_17
+ (.I0(s_axi_araddr[30]),
+ .I1(addr_s[30]),
+ .I2(s_axi_araddr[21]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[21]),
+ .O(\rd_data_s[31]_i_17_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_18
+ (.I0(s_axi_araddr[26]),
+ .I1(addr_s[26]),
+ .I2(s_axi_araddr[25]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[25]),
+ .O(\rd_data_s[31]_i_18_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_19
+ (.I0(s_axi_araddr[11]),
+ .I1(addr_s[11]),
+ .I2(s_axi_araddr[8]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[8]),
+ .O(\rd_data_s[31]_i_19_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[31]_i_2
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[31]_i_7_n_0 ),
+ .I5(\rd_data_s[31]_i_8_n_0 ),
+ .O(D[31]));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_20
+ (.I0(s_axi_araddr[10]),
+ .I1(addr_s[10]),
+ .I2(s_axi_araddr[9]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[9]),
+ .O(\rd_data_s[31]_i_20_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_21
+ (.I0(s_axi_araddr[29]),
+ .I1(addr_s[29]),
+ .I2(s_axi_araddr[28]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[28]),
+ .O(\rd_data_s[31]_i_21_n_0 ));
+ LUT4 #(
+ .INIT(16'h15D5))
+ \rd_data_s[31]_i_22
+ (.I0(addr_s[2]),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_arvalid),
+ .I3(s_axi_araddr[2]),
+ .O(\rd_data_s[31]_i_22_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBBFCB8))
+ \rd_data_s[31]_i_3
+ (.I0(addr_s[16]),
+ .I1(\rd_data_s[31]_i_9_n_0 ),
+ .I2(s_axi_araddr[16]),
+ .I3(addr_s[19]),
+ .I4(s_axi_araddr[19]),
+ .I5(\rd_data_s[31]_i_10_n_0 ),
+ .O(\rd_data_s[31]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBBFCB8))
+ \rd_data_s[31]_i_4
+ (.I0(addr_s[12]),
+ .I1(\rd_data_s[31]_i_9_n_0 ),
+ .I2(s_axi_araddr[12]),
+ .I3(addr_s[15]),
+ .I4(s_axi_araddr[15]),
+ .I5(\rd_data_s[31]_i_11_n_0 ),
+ .O(\rd_data_s[31]_i_4_n_0 ));
+ LUT4 #(
+ .INIT(16'hFFFE))
+ \rd_data_s[31]_i_5
+ (.I0(\rd_data_s[31]_i_12_n_0 ),
+ .I1(\rd_data_s[31]_i_13_n_0 ),
+ .I2(\rd_data_s[31]_i_14_n_0 ),
+ .I3(\rd_data_s[31]_i_15_n_0 ),
+ .O(\rd_data_s[31]_i_5_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000004))
+ \rd_data_s[31]_i_6
+ (.I0(\rd_data_s[31]_i_16_n_0 ),
+ .I1(\rd_data_s[31]_i_17_n_0 ),
+ .I2(\rd_data_s[31]_i_18_n_0 ),
+ .I3(\rd_data_s[31]_i_19_n_0 ),
+ .I4(\rd_data_s[31]_i_20_n_0 ),
+ .I5(\rd_data_s[31]_i_21_n_0 ),
+ .O(\rd_data_s[31]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'hFAFFFFFFFACCCCCC))
+ \rd_data_s[31]_i_7
+ (.I0(s_axi_araddr[1]),
+ .I1(addr_s[1]),
+ .I2(s_axi_araddr[0]),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_arready_s_reg_0),
+ .I5(addr_s[0]),
+ .O(\rd_data_s[31]_i_7_n_0 ));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[31]_i_8
+ (.I0(hog_global_ver_i[31]),
+ .I1(hog_global_sha_i[31]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[31]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[31]),
+ .O(\rd_data_s[31]_i_8_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h7))
+ \rd_data_s[31]_i_9
+ (.I0(s_axi_arready_s_reg_0),
+ .I1(s_axi_arvalid),
+ .O(\rd_data_s[31]_i_9_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[3]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[3]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[3]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[3]_i_2
+ (.I0(hog_global_ver_i[3]),
+ .I1(hog_global_sha_i[3]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[3]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[3]),
+ .O(\rd_data_s[3]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[4]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[4]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[4]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[4]_i_2
+ (.I0(hog_global_ver_i[4]),
+ .I1(hog_global_sha_i[4]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[4]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[4]),
+ .O(\rd_data_s[4]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[5]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[5]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[5]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[5]_i_2
+ (.I0(hog_global_ver_i[5]),
+ .I1(hog_global_sha_i[5]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[5]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[5]),
+ .O(\rd_data_s[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[6]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[6]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[6]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[6]_i_2
+ (.I0(hog_global_ver_i[6]),
+ .I1(hog_global_sha_i[6]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[6]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[6]),
+ .O(\rd_data_s[6]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[7]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[7]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[7]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[7]_i_2
+ (.I0(hog_global_ver_i[7]),
+ .I1(hog_global_sha_i[7]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[7]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[7]),
+ .O(\rd_data_s[7]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[8]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[8]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[8]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[8]_i_2
+ (.I0(hog_global_ver_i[8]),
+ .I1(hog_global_sha_i[8]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[8]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[8]),
+ .O(\rd_data_s[8]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000100))
+ \rd_data_s[9]_i_1
+ (.I0(\rd_data_s[31]_i_3_n_0 ),
+ .I1(\rd_data_s[31]_i_4_n_0 ),
+ .I2(\rd_data_s[31]_i_5_n_0 ),
+ .I3(\rd_data_s[31]_i_6_n_0 ),
+ .I4(\rd_data_s[9]_i_2_n_0 ),
+ .I5(\rd_data_s[31]_i_7_n_0 ),
+ .O(D[9]));
+ LUT6 #(
+ .INIT(64'h505F3030505F3F3F))
+ \rd_data_s[9]_i_2
+ (.I0(hog_global_ver_i[9]),
+ .I1(hog_global_sha_i[9]),
+ .I2(\addr_s[3]_i_1_n_0 ),
+ .I3(hog_global_date_i[9]),
+ .I4(\rd_data_s[31]_i_22_n_0 ),
+ .I5(hog_global_time_i[9]),
+ .O(\rd_data_s[9]_i_2_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT5 #(
+ .INIT(32'h00004F00))
+ s_axi_arready_s_i_1
+ (.I0(s_axi_arready_s_reg_0),
+ .I1(s_axi_rready),
+ .I2(rd_addr_latched),
+ .I3(s_axi_aresetn),
+ .I4(s_axi_arvalid),
+ .O(s_axi_arready_s_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_arready_s_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_arready_s_i_1_n_0),
+ .Q(s_axi_arready_s_reg_0),
+ .R(1'b0));
+ LUT1 #(
+ .INIT(2'h1))
+ s_axi_awready_s_i_1
+ (.I0(s_axi_aresetn),
+ .O(s_axi_aresetn_0));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'h88F8))
+ s_axi_rvalid_s_i_1
+ (.I0(s_axi_arvalid),
+ .I1(s_axi_arready_s_reg_0),
+ .I2(s_axi_rvalid),
+ .I3(s_axi_rready),
+ .O(s_axi_rvalid_s_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_rvalid_s_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_rvalid_s_i_1_n_0),
+ .Q(s_axi_rvalid),
+ .R(s_axi_aresetn_0));
+endmodule
+
+(* ORIG_REF_NAME = "axi4lite_wr_channel_if" *)
+module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if
+ (s_axi_wready,
+ s_axi_awready,
+ s_axi_bvalid,
+ s_axi_awready_s_reg_0,
+ s_axi_aclk,
+ s_axi_wvalid,
+ s_axi_bready,
+ s_axi_awvalid);
+ output s_axi_wready;
+ output s_axi_awready;
+ output s_axi_bvalid;
+ input s_axi_awready_s_reg_0;
+ input s_axi_aclk;
+ input s_axi_wvalid;
+ input s_axi_bready;
+ input s_axi_awvalid;
+
+ wire aw_en_i_1_n_0;
+ wire aw_en_reg_n_0;
+ wire s_axi_aclk;
+ wire s_axi_awready;
+ wire s_axi_awready_s0__0;
+ wire s_axi_awready_s_reg_0;
+ wire s_axi_awvalid;
+ wire s_axi_bready;
+ wire s_axi_bvalid;
+ wire s_axi_bvalid_s_i_1_n_0;
+ wire s_axi_wready;
+ wire s_axi_wready_s0;
+ wire s_axi_wvalid;
+
+ LUT5 #(
+ .INIT(32'h7F2A2A2A))
+ aw_en_i_1
+ (.I0(aw_en_reg_n_0),
+ .I1(s_axi_wvalid),
+ .I2(s_axi_awvalid),
+ .I3(s_axi_bready),
+ .I4(s_axi_bvalid),
+ .O(aw_en_i_1_n_0));
+ FDSE #(
+ .INIT(1'b0))
+ aw_en_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(aw_en_i_1_n_0),
+ .Q(aw_en_reg_n_0),
+ .S(s_axi_awready_s_reg_0));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT3 #(
+ .INIT(8'h80))
+ s_axi_awready_s0
+ (.I0(s_axi_awvalid),
+ .I1(s_axi_wvalid),
+ .I2(aw_en_reg_n_0),
+ .O(s_axi_awready_s0__0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_awready_s_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_awready_s0__0),
+ .Q(s_axi_awready),
+ .R(s_axi_awready_s_reg_0));
+ LUT4 #(
+ .INIT(16'h8F88))
+ s_axi_bvalid_s_i_1
+ (.I0(s_axi_wready),
+ .I1(s_axi_wvalid),
+ .I2(s_axi_bready),
+ .I3(s_axi_bvalid),
+ .O(s_axi_bvalid_s_i_1_n_0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_bvalid_s_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_bvalid_s_i_1_n_0),
+ .Q(s_axi_bvalid),
+ .R(s_axi_awready_s_reg_0));
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT4 #(
+ .INIT(16'h0080))
+ s_axi_wready_s_i_1
+ (.I0(aw_en_reg_n_0),
+ .I1(s_axi_wvalid),
+ .I2(s_axi_awvalid),
+ .I3(s_axi_wready),
+ .O(s_axi_wready_s0));
+ FDRE #(
+ .INIT(1'b0))
+ s_axi_wready_s_reg
+ (.C(s_axi_aclk),
+ .CE(1'b1),
+ .D(s_axi_wready_s0),
+ .Q(s_axi_wready),
+ .R(s_axi_awready_s_reg_0));
+endmodule
+
+(* ORIG_REF_NAME = "hog_build_info_regs" *)
+module mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs
+ (s_axi_rdata,
+ SR,
+ E,
+ D,
+ s_axi_aclk);
+ output [31:0]s_axi_rdata;
+ input [0:0]SR;
+ input [0:0]E;
+ input [31:0]D;
+ input s_axi_aclk;
+
+ wire [31:0]D;
+ wire [0:0]E;
+ wire [0:0]SR;
+ wire s_axi_aclk;
+ wire [31:0]s_axi_rdata;
+
+ FDRE \rd_data_s_reg[0]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[0]),
+ .Q(s_axi_rdata[0]),
+ .R(SR));
+ FDRE \rd_data_s_reg[10]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[10]),
+ .Q(s_axi_rdata[10]),
+ .R(SR));
+ FDRE \rd_data_s_reg[11]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[11]),
+ .Q(s_axi_rdata[11]),
+ .R(SR));
+ FDRE \rd_data_s_reg[12]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[12]),
+ .Q(s_axi_rdata[12]),
+ .R(SR));
+ FDRE \rd_data_s_reg[13]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[13]),
+ .Q(s_axi_rdata[13]),
+ .R(SR));
+ FDRE \rd_data_s_reg[14]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[14]),
+ .Q(s_axi_rdata[14]),
+ .R(SR));
+ FDRE \rd_data_s_reg[15]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[15]),
+ .Q(s_axi_rdata[15]),
+ .R(SR));
+ FDRE \rd_data_s_reg[16]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[16]),
+ .Q(s_axi_rdata[16]),
+ .R(SR));
+ FDRE \rd_data_s_reg[17]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[17]),
+ .Q(s_axi_rdata[17]),
+ .R(SR));
+ FDRE \rd_data_s_reg[18]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[18]),
+ .Q(s_axi_rdata[18]),
+ .R(SR));
+ FDRE \rd_data_s_reg[19]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[19]),
+ .Q(s_axi_rdata[19]),
+ .R(SR));
+ FDRE \rd_data_s_reg[1]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[1]),
+ .Q(s_axi_rdata[1]),
+ .R(SR));
+ FDRE \rd_data_s_reg[20]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[20]),
+ .Q(s_axi_rdata[20]),
+ .R(SR));
+ FDRE \rd_data_s_reg[21]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[21]),
+ .Q(s_axi_rdata[21]),
+ .R(SR));
+ FDRE \rd_data_s_reg[22]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[22]),
+ .Q(s_axi_rdata[22]),
+ .R(SR));
+ FDRE \rd_data_s_reg[23]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[23]),
+ .Q(s_axi_rdata[23]),
+ .R(SR));
+ FDRE \rd_data_s_reg[24]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[24]),
+ .Q(s_axi_rdata[24]),
+ .R(SR));
+ FDRE \rd_data_s_reg[25]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[25]),
+ .Q(s_axi_rdata[25]),
+ .R(SR));
+ FDRE \rd_data_s_reg[26]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[26]),
+ .Q(s_axi_rdata[26]),
+ .R(SR));
+ FDRE \rd_data_s_reg[27]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[27]),
+ .Q(s_axi_rdata[27]),
+ .R(SR));
+ FDRE \rd_data_s_reg[28]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[28]),
+ .Q(s_axi_rdata[28]),
+ .R(SR));
+ FDRE \rd_data_s_reg[29]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[29]),
+ .Q(s_axi_rdata[29]),
+ .R(SR));
+ FDRE \rd_data_s_reg[2]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[2]),
+ .Q(s_axi_rdata[2]),
+ .R(SR));
+ FDRE \rd_data_s_reg[30]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[30]),
+ .Q(s_axi_rdata[30]),
+ .R(SR));
+ FDRE \rd_data_s_reg[31]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[31]),
+ .Q(s_axi_rdata[31]),
+ .R(SR));
+ FDRE \rd_data_s_reg[3]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[3]),
+ .Q(s_axi_rdata[3]),
+ .R(SR));
+ FDRE \rd_data_s_reg[4]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[4]),
+ .Q(s_axi_rdata[4]),
+ .R(SR));
+ FDRE \rd_data_s_reg[5]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[5]),
+ .Q(s_axi_rdata[5]),
+ .R(SR));
+ FDRE \rd_data_s_reg[6]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[6]),
+ .Q(s_axi_rdata[6]),
+ .R(SR));
+ FDRE \rd_data_s_reg[7]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[7]),
+ .Q(s_axi_rdata[7]),
+ .R(SR));
+ FDRE \rd_data_s_reg[8]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[8]),
+ .Q(s_axi_rdata[8]),
+ .R(SR));
+ FDRE \rd_data_s_reg[9]
+ (.C(s_axi_aclk),
+ .CE(E),
+ .D(D[9]),
+ .Q(s_axi_rdata[9]),
+ .R(SR));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..7783afcf2e1ba7103e647d8deeb0a5bcc638eb78
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
@@ -0,0 +1,2627 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Mar 20 18:25:04 2025
+-- Host : hogtest running 64-bit unknown
+-- Command : write_vhdl -force -mode funcsim
+-- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
+-- Design : mb_design_1_axi4lite_hog_build_i_0_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if is
+ port (
+ s_axi_aresetn_0 : out STD_LOGIC;
+ s_axi_arready_s_reg_0 : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if : entity is "axi4lite_rd_channel_if";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if is
+ signal addr_s : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal \addr_s[0]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[10]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[11]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[12]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[13]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[14]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[15]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[16]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[17]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[18]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[19]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[1]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[20]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[21]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[22]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[23]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[24]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[25]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[26]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[27]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[28]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[29]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[2]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[30]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[31]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[3]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[4]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[5]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[6]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[7]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[8]_i_1_n_0\ : STD_LOGIC;
+ signal \addr_s[9]_i_1_n_0\ : STD_LOGIC;
+ signal rd_addr_latched : STD_LOGIC;
+ signal rd_addr_latched_i_1_n_0 : STD_LOGIC;
+ signal \rd_data_s[0]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[10]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[11]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[12]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[13]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[14]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[15]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[16]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[17]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[18]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[19]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[1]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[20]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[21]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[22]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[23]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[24]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[25]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[26]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[27]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[28]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[29]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[2]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[30]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_10_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_11_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_12_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_13_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_14_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_15_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_16_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_17_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_18_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_19_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_20_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_21_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_22_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_3_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_4_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_5_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_6_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_7_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_8_n_0\ : STD_LOGIC;
+ signal \rd_data_s[31]_i_9_n_0\ : STD_LOGIC;
+ signal \rd_data_s[3]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[4]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[5]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[6]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[7]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[8]_i_2_n_0\ : STD_LOGIC;
+ signal \rd_data_s[9]_i_2_n_0\ : STD_LOGIC;
+ signal \^s_axi_aresetn_0\ : STD_LOGIC;
+ signal s_axi_arready_s_i_1_n_0 : STD_LOGIC;
+ signal \^s_axi_arready_s_reg_0\ : STD_LOGIC;
+ signal \^s_axi_rvalid\ : STD_LOGIC;
+ signal s_axi_rvalid_s_i_1_n_0 : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \addr_s[0]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of rd_addr_latched_i_1 : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \rd_data_s[31]_i_1\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \rd_data_s[31]_i_9\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of s_axi_arready_s_i_1 : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of s_axi_rvalid_s_i_1 : label is "soft_lutpair1";
+begin
+ s_axi_aresetn_0 <= \^s_axi_aresetn_0\;
+ s_axi_arready_s_reg_0 <= \^s_axi_arready_s_reg_0\;
+ s_axi_rvalid <= \^s_axi_rvalid\;
+\addr_s[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(0),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(0),
+ O => \addr_s[0]_i_1_n_0\
+ );
+\addr_s[10]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(10),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(10),
+ O => \addr_s[10]_i_1_n_0\
+ );
+\addr_s[11]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(11),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(11),
+ O => \addr_s[11]_i_1_n_0\
+ );
+\addr_s[12]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(12),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(12),
+ O => \addr_s[12]_i_1_n_0\
+ );
+\addr_s[13]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(13),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(13),
+ O => \addr_s[13]_i_1_n_0\
+ );
+\addr_s[14]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(14),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(14),
+ O => \addr_s[14]_i_1_n_0\
+ );
+\addr_s[15]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(15),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(15),
+ O => \addr_s[15]_i_1_n_0\
+ );
+\addr_s[16]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(16),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(16),
+ O => \addr_s[16]_i_1_n_0\
+ );
+\addr_s[17]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(17),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(17),
+ O => \addr_s[17]_i_1_n_0\
+ );
+\addr_s[18]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(18),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(18),
+ O => \addr_s[18]_i_1_n_0\
+ );
+\addr_s[19]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(19),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(19),
+ O => \addr_s[19]_i_1_n_0\
+ );
+\addr_s[1]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(1),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(1),
+ O => \addr_s[1]_i_1_n_0\
+ );
+\addr_s[20]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(20),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(20),
+ O => \addr_s[20]_i_1_n_0\
+ );
+\addr_s[21]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(21),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(21),
+ O => \addr_s[21]_i_1_n_0\
+ );
+\addr_s[22]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(22),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(22),
+ O => \addr_s[22]_i_1_n_0\
+ );
+\addr_s[23]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(23),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(23),
+ O => \addr_s[23]_i_1_n_0\
+ );
+\addr_s[24]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(24),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(24),
+ O => \addr_s[24]_i_1_n_0\
+ );
+\addr_s[25]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(25),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(25),
+ O => \addr_s[25]_i_1_n_0\
+ );
+\addr_s[26]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(26),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(26),
+ O => \addr_s[26]_i_1_n_0\
+ );
+\addr_s[27]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(27),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(27),
+ O => \addr_s[27]_i_1_n_0\
+ );
+\addr_s[28]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(28),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(28),
+ O => \addr_s[28]_i_1_n_0\
+ );
+\addr_s[29]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(29),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(29),
+ O => \addr_s[29]_i_1_n_0\
+ );
+\addr_s[2]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"BF80"
+ )
+ port map (
+ I0 => s_axi_araddr(2),
+ I1 => s_axi_arvalid,
+ I2 => \^s_axi_arready_s_reg_0\,
+ I3 => addr_s(2),
+ O => \addr_s[2]_i_1_n_0\
+ );
+\addr_s[30]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"BF80"
+ )
+ port map (
+ I0 => s_axi_araddr(30),
+ I1 => s_axi_arvalid,
+ I2 => \^s_axi_arready_s_reg_0\,
+ I3 => addr_s(30),
+ O => \addr_s[30]_i_1_n_0\
+ );
+\addr_s[31]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(31),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(31),
+ O => \addr_s[31]_i_1_n_0\
+ );
+\addr_s[3]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(3),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(3),
+ O => \addr_s[3]_i_1_n_0\
+ );
+\addr_s[4]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(4),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(4),
+ O => \addr_s[4]_i_1_n_0\
+ );
+\addr_s[5]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(5),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(5),
+ O => \addr_s[5]_i_1_n_0\
+ );
+\addr_s[6]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(6),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(6),
+ O => \addr_s[6]_i_1_n_0\
+ );
+\addr_s[7]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(7),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(7),
+ O => \addr_s[7]_i_1_n_0\
+ );
+\addr_s[8]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(8),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(8),
+ O => \addr_s[8]_i_1_n_0\
+ );
+\addr_s[9]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EA2A"
+ )
+ port map (
+ I0 => addr_s(9),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(9),
+ O => \addr_s[9]_i_1_n_0\
+ );
+\addr_s_reg[0]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[0]_i_1_n_0\,
+ Q => addr_s(0),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[10]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[10]_i_1_n_0\,
+ Q => addr_s(10),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[11]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[11]_i_1_n_0\,
+ Q => addr_s(11),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[12]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[12]_i_1_n_0\,
+ Q => addr_s(12),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[13]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[13]_i_1_n_0\,
+ Q => addr_s(13),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[14]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[14]_i_1_n_0\,
+ Q => addr_s(14),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[15]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[15]_i_1_n_0\,
+ Q => addr_s(15),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[16]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[16]_i_1_n_0\,
+ Q => addr_s(16),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[17]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[17]_i_1_n_0\,
+ Q => addr_s(17),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[18]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[18]_i_1_n_0\,
+ Q => addr_s(18),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[19]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[19]_i_1_n_0\,
+ Q => addr_s(19),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[1]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[1]_i_1_n_0\,
+ Q => addr_s(1),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[20]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[20]_i_1_n_0\,
+ Q => addr_s(20),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[21]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[21]_i_1_n_0\,
+ Q => addr_s(21),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[22]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[22]_i_1_n_0\,
+ Q => addr_s(22),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[23]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[23]_i_1_n_0\,
+ Q => addr_s(23),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[24]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[24]_i_1_n_0\,
+ Q => addr_s(24),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[25]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[25]_i_1_n_0\,
+ Q => addr_s(25),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[26]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[26]_i_1_n_0\,
+ Q => addr_s(26),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[27]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[27]_i_1_n_0\,
+ Q => addr_s(27),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[28]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[28]_i_1_n_0\,
+ Q => addr_s(28),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[29]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[29]_i_1_n_0\,
+ Q => addr_s(29),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[2]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[2]_i_1_n_0\,
+ Q => addr_s(2),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[30]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[30]_i_1_n_0\,
+ Q => addr_s(30),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[31]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[31]_i_1_n_0\,
+ Q => addr_s(31),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[3]_i_1_n_0\,
+ Q => addr_s(3),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[4]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[4]_i_1_n_0\,
+ Q => addr_s(4),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[5]_i_1_n_0\,
+ Q => addr_s(5),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[6]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[6]_i_1_n_0\,
+ Q => addr_s(6),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[7]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[7]_i_1_n_0\,
+ Q => addr_s(7),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[8]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[8]_i_1_n_0\,
+ Q => addr_s(8),
+ R => \^s_axi_aresetn_0\
+ );
+\addr_s_reg[9]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \addr_s[9]_i_1_n_0\,
+ Q => addr_s(9),
+ R => \^s_axi_aresetn_0\
+ );
+rd_addr_latched_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"EFAA"
+ )
+ port map (
+ I0 => s_axi_arvalid,
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_rready,
+ I3 => rd_addr_latched,
+ O => rd_addr_latched_i_1_n_0
+ );
+rd_addr_latched_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => rd_addr_latched_i_1_n_0,
+ Q => rd_addr_latched,
+ R => \^s_axi_aresetn_0\
+ );
+\rd_data_s[0]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[0]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(0)
+ );
+\rd_data_s[0]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(0),
+ I1 => hog_global_sha_i(0),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(0),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(0),
+ O => \rd_data_s[0]_i_2_n_0\
+ );
+\rd_data_s[10]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[10]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(10)
+ );
+\rd_data_s[10]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(10),
+ I1 => hog_global_sha_i(10),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(10),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(10),
+ O => \rd_data_s[10]_i_2_n_0\
+ );
+\rd_data_s[11]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[11]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(11)
+ );
+\rd_data_s[11]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(11),
+ I1 => hog_global_sha_i(11),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(11),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(11),
+ O => \rd_data_s[11]_i_2_n_0\
+ );
+\rd_data_s[12]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[12]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(12)
+ );
+\rd_data_s[12]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(12),
+ I1 => hog_global_sha_i(12),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(12),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(12),
+ O => \rd_data_s[12]_i_2_n_0\
+ );
+\rd_data_s[13]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[13]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(13)
+ );
+\rd_data_s[13]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(13),
+ I1 => hog_global_sha_i(13),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(13),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(13),
+ O => \rd_data_s[13]_i_2_n_0\
+ );
+\rd_data_s[14]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[14]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(14)
+ );
+\rd_data_s[14]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(14),
+ I1 => hog_global_sha_i(14),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(14),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(14),
+ O => \rd_data_s[14]_i_2_n_0\
+ );
+\rd_data_s[15]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[15]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(15)
+ );
+\rd_data_s[15]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(15),
+ I1 => hog_global_sha_i(15),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(15),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(15),
+ O => \rd_data_s[15]_i_2_n_0\
+ );
+\rd_data_s[16]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[16]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(16)
+ );
+\rd_data_s[16]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(16),
+ I1 => hog_global_sha_i(16),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(16),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(16),
+ O => \rd_data_s[16]_i_2_n_0\
+ );
+\rd_data_s[17]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[17]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(17)
+ );
+\rd_data_s[17]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(17),
+ I1 => hog_global_sha_i(17),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(17),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(17),
+ O => \rd_data_s[17]_i_2_n_0\
+ );
+\rd_data_s[18]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[18]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(18)
+ );
+\rd_data_s[18]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(18),
+ I1 => hog_global_sha_i(18),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(18),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(18),
+ O => \rd_data_s[18]_i_2_n_0\
+ );
+\rd_data_s[19]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[19]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(19)
+ );
+\rd_data_s[19]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(19),
+ I1 => hog_global_sha_i(19),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(19),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(19),
+ O => \rd_data_s[19]_i_2_n_0\
+ );
+\rd_data_s[1]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[1]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(1)
+ );
+\rd_data_s[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(1),
+ I1 => hog_global_sha_i(1),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(1),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(1),
+ O => \rd_data_s[1]_i_2_n_0\
+ );
+\rd_data_s[20]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[20]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(20)
+ );
+\rd_data_s[20]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(20),
+ I1 => hog_global_sha_i(20),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(20),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(20),
+ O => \rd_data_s[20]_i_2_n_0\
+ );
+\rd_data_s[21]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[21]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(21)
+ );
+\rd_data_s[21]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(21),
+ I1 => hog_global_sha_i(21),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(21),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(21),
+ O => \rd_data_s[21]_i_2_n_0\
+ );
+\rd_data_s[22]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[22]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(22)
+ );
+\rd_data_s[22]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(22),
+ I1 => hog_global_sha_i(22),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(22),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(22),
+ O => \rd_data_s[22]_i_2_n_0\
+ );
+\rd_data_s[23]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[23]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(23)
+ );
+\rd_data_s[23]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(23),
+ I1 => hog_global_sha_i(23),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(23),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(23),
+ O => \rd_data_s[23]_i_2_n_0\
+ );
+\rd_data_s[24]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[24]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(24)
+ );
+\rd_data_s[24]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(24),
+ I1 => hog_global_sha_i(24),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(24),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(24),
+ O => \rd_data_s[24]_i_2_n_0\
+ );
+\rd_data_s[25]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[25]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(25)
+ );
+\rd_data_s[25]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(25),
+ I1 => hog_global_sha_i(25),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(25),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(25),
+ O => \rd_data_s[25]_i_2_n_0\
+ );
+\rd_data_s[26]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[26]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(26)
+ );
+\rd_data_s[26]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(26),
+ I1 => hog_global_sha_i(26),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(26),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(26),
+ O => \rd_data_s[26]_i_2_n_0\
+ );
+\rd_data_s[27]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[27]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(27)
+ );
+\rd_data_s[27]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(27),
+ I1 => hog_global_sha_i(27),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(27),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(27),
+ O => \rd_data_s[27]_i_2_n_0\
+ );
+\rd_data_s[28]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[28]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(28)
+ );
+\rd_data_s[28]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(28),
+ I1 => hog_global_sha_i(28),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(28),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(28),
+ O => \rd_data_s[28]_i_2_n_0\
+ );
+\rd_data_s[29]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[29]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(29)
+ );
+\rd_data_s[29]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(29),
+ I1 => hog_global_sha_i(29),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(29),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(29),
+ O => \rd_data_s[29]_i_2_n_0\
+ );
+\rd_data_s[2]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[2]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(2)
+ );
+\rd_data_s[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(2),
+ I1 => hog_global_sha_i(2),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(2),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(2),
+ O => \rd_data_s[2]_i_2_n_0\
+ );
+\rd_data_s[30]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[30]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(30)
+ );
+\rd_data_s[30]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(30),
+ I1 => hog_global_sha_i(30),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(30),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(30),
+ O => \rd_data_s[30]_i_2_n_0\
+ );
+\rd_data_s[31]_i_1\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => s_axi_arvalid,
+ I1 => \^s_axi_arready_s_reg_0\,
+ O => E(0)
+ );
+\rd_data_s[31]_i_10\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(18),
+ I1 => addr_s(18),
+ I2 => s_axi_araddr(17),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(17),
+ O => \rd_data_s[31]_i_10_n_0\
+ );
+\rd_data_s[31]_i_11\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(14),
+ I1 => addr_s(14),
+ I2 => s_axi_araddr(13),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(13),
+ O => \rd_data_s[31]_i_11_n_0\
+ );
+\rd_data_s[31]_i_12\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(27),
+ I1 => addr_s(27),
+ I2 => s_axi_araddr(24),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(24),
+ O => \rd_data_s[31]_i_12_n_0\
+ );
+\rd_data_s[31]_i_13\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(7),
+ I1 => addr_s(7),
+ I2 => s_axi_araddr(6),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(6),
+ O => \rd_data_s[31]_i_13_n_0\
+ );
+\rd_data_s[31]_i_14\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(23),
+ I1 => addr_s(23),
+ I2 => s_axi_araddr(5),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(5),
+ O => \rd_data_s[31]_i_14_n_0\
+ );
+\rd_data_s[31]_i_15\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(22),
+ I1 => addr_s(22),
+ I2 => s_axi_araddr(4),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(4),
+ O => \rd_data_s[31]_i_15_n_0\
+ );
+\rd_data_s[31]_i_16\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(31),
+ I1 => addr_s(31),
+ I2 => s_axi_araddr(20),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(20),
+ O => \rd_data_s[31]_i_16_n_0\
+ );
+\rd_data_s[31]_i_17\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0500000005333333"
+ )
+ port map (
+ I0 => s_axi_araddr(30),
+ I1 => addr_s(30),
+ I2 => s_axi_araddr(21),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(21),
+ O => \rd_data_s[31]_i_17_n_0\
+ );
+\rd_data_s[31]_i_18\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(26),
+ I1 => addr_s(26),
+ I2 => s_axi_araddr(25),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(25),
+ O => \rd_data_s[31]_i_18_n_0\
+ );
+\rd_data_s[31]_i_19\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(11),
+ I1 => addr_s(11),
+ I2 => s_axi_araddr(8),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(8),
+ O => \rd_data_s[31]_i_19_n_0\
+ );
+\rd_data_s[31]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[31]_i_7_n_0\,
+ I5 => \rd_data_s[31]_i_8_n_0\,
+ O => D(31)
+ );
+\rd_data_s[31]_i_20\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(10),
+ I1 => addr_s(10),
+ I2 => s_axi_araddr(9),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(9),
+ O => \rd_data_s[31]_i_20_n_0\
+ );
+\rd_data_s[31]_i_21\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(29),
+ I1 => addr_s(29),
+ I2 => s_axi_araddr(28),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(28),
+ O => \rd_data_s[31]_i_21_n_0\
+ );
+\rd_data_s[31]_i_22\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"15D5"
+ )
+ port map (
+ I0 => addr_s(2),
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => s_axi_arvalid,
+ I3 => s_axi_araddr(2),
+ O => \rd_data_s[31]_i_22_n_0\
+ );
+\rd_data_s[31]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFBBFCB8"
+ )
+ port map (
+ I0 => addr_s(16),
+ I1 => \rd_data_s[31]_i_9_n_0\,
+ I2 => s_axi_araddr(16),
+ I3 => addr_s(19),
+ I4 => s_axi_araddr(19),
+ I5 => \rd_data_s[31]_i_10_n_0\,
+ O => \rd_data_s[31]_i_3_n_0\
+ );
+\rd_data_s[31]_i_4\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFBBFCB8"
+ )
+ port map (
+ I0 => addr_s(12),
+ I1 => \rd_data_s[31]_i_9_n_0\,
+ I2 => s_axi_araddr(12),
+ I3 => addr_s(15),
+ I4 => s_axi_araddr(15),
+ I5 => \rd_data_s[31]_i_11_n_0\,
+ O => \rd_data_s[31]_i_4_n_0\
+ );
+\rd_data_s[31]_i_5\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"FFFE"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_12_n_0\,
+ I1 => \rd_data_s[31]_i_13_n_0\,
+ I2 => \rd_data_s[31]_i_14_n_0\,
+ I3 => \rd_data_s[31]_i_15_n_0\,
+ O => \rd_data_s[31]_i_5_n_0\
+ );
+\rd_data_s[31]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000004"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_16_n_0\,
+ I1 => \rd_data_s[31]_i_17_n_0\,
+ I2 => \rd_data_s[31]_i_18_n_0\,
+ I3 => \rd_data_s[31]_i_19_n_0\,
+ I4 => \rd_data_s[31]_i_20_n_0\,
+ I5 => \rd_data_s[31]_i_21_n_0\,
+ O => \rd_data_s[31]_i_6_n_0\
+ );
+\rd_data_s[31]_i_7\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FAFFFFFFFACCCCCC"
+ )
+ port map (
+ I0 => s_axi_araddr(1),
+ I1 => addr_s(1),
+ I2 => s_axi_araddr(0),
+ I3 => s_axi_arvalid,
+ I4 => \^s_axi_arready_s_reg_0\,
+ I5 => addr_s(0),
+ O => \rd_data_s[31]_i_7_n_0\
+ );
+\rd_data_s[31]_i_8\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(31),
+ I1 => hog_global_sha_i(31),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(31),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(31),
+ O => \rd_data_s[31]_i_8_n_0\
+ );
+\rd_data_s[31]_i_9\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"7"
+ )
+ port map (
+ I0 => \^s_axi_arready_s_reg_0\,
+ I1 => s_axi_arvalid,
+ O => \rd_data_s[31]_i_9_n_0\
+ );
+\rd_data_s[3]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[3]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(3)
+ );
+\rd_data_s[3]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(3),
+ I1 => hog_global_sha_i(3),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(3),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(3),
+ O => \rd_data_s[3]_i_2_n_0\
+ );
+\rd_data_s[4]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[4]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(4)
+ );
+\rd_data_s[4]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(4),
+ I1 => hog_global_sha_i(4),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(4),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(4),
+ O => \rd_data_s[4]_i_2_n_0\
+ );
+\rd_data_s[5]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[5]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(5)
+ );
+\rd_data_s[5]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(5),
+ I1 => hog_global_sha_i(5),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(5),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(5),
+ O => \rd_data_s[5]_i_2_n_0\
+ );
+\rd_data_s[6]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[6]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(6)
+ );
+\rd_data_s[6]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(6),
+ I1 => hog_global_sha_i(6),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(6),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(6),
+ O => \rd_data_s[6]_i_2_n_0\
+ );
+\rd_data_s[7]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[7]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(7)
+ );
+\rd_data_s[7]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(7),
+ I1 => hog_global_sha_i(7),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(7),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(7),
+ O => \rd_data_s[7]_i_2_n_0\
+ );
+\rd_data_s[8]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[8]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(8)
+ );
+\rd_data_s[8]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(8),
+ I1 => hog_global_sha_i(8),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(8),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(8),
+ O => \rd_data_s[8]_i_2_n_0\
+ );
+\rd_data_s[9]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"0000000000000100"
+ )
+ port map (
+ I0 => \rd_data_s[31]_i_3_n_0\,
+ I1 => \rd_data_s[31]_i_4_n_0\,
+ I2 => \rd_data_s[31]_i_5_n_0\,
+ I3 => \rd_data_s[31]_i_6_n_0\,
+ I4 => \rd_data_s[9]_i_2_n_0\,
+ I5 => \rd_data_s[31]_i_7_n_0\,
+ O => D(9)
+ );
+\rd_data_s[9]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"505F3030505F3F3F"
+ )
+ port map (
+ I0 => hog_global_ver_i(9),
+ I1 => hog_global_sha_i(9),
+ I2 => \addr_s[3]_i_1_n_0\,
+ I3 => hog_global_date_i(9),
+ I4 => \rd_data_s[31]_i_22_n_0\,
+ I5 => hog_global_time_i(9),
+ O => \rd_data_s[9]_i_2_n_0\
+ );
+s_axi_arready_s_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00004F00"
+ )
+ port map (
+ I0 => \^s_axi_arready_s_reg_0\,
+ I1 => s_axi_rready,
+ I2 => rd_addr_latched,
+ I3 => s_axi_aresetn,
+ I4 => s_axi_arvalid,
+ O => s_axi_arready_s_i_1_n_0
+ );
+s_axi_arready_s_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_axi_arready_s_i_1_n_0,
+ Q => \^s_axi_arready_s_reg_0\,
+ R => '0'
+ );
+s_axi_awready_s_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => s_axi_aresetn,
+ O => \^s_axi_aresetn_0\
+ );
+s_axi_rvalid_s_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"88F8"
+ )
+ port map (
+ I0 => s_axi_arvalid,
+ I1 => \^s_axi_arready_s_reg_0\,
+ I2 => \^s_axi_rvalid\,
+ I3 => s_axi_rready,
+ O => s_axi_rvalid_s_i_1_n_0
+ );
+s_axi_rvalid_s_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_axi_rvalid_s_i_1_n_0,
+ Q => \^s_axi_rvalid\,
+ R => \^s_axi_aresetn_0\
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if is
+ port (
+ s_axi_wready : out STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_awready_s_reg_0 : in STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if : entity is "axi4lite_wr_channel_if";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if is
+ signal aw_en_i_1_n_0 : STD_LOGIC;
+ signal aw_en_reg_n_0 : STD_LOGIC;
+ signal \s_axi_awready_s0__0\ : STD_LOGIC;
+ signal \^s_axi_bvalid\ : STD_LOGIC;
+ signal s_axi_bvalid_s_i_1_n_0 : STD_LOGIC;
+ signal \^s_axi_wready\ : STD_LOGIC;
+ signal s_axi_wready_s0 : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of s_axi_awready_s0 : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of s_axi_wready_s_i_1 : label is "soft_lutpair3";
+begin
+ s_axi_bvalid <= \^s_axi_bvalid\;
+ s_axi_wready <= \^s_axi_wready\;
+aw_en_i_1: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"7F2A2A2A"
+ )
+ port map (
+ I0 => aw_en_reg_n_0,
+ I1 => s_axi_wvalid,
+ I2 => s_axi_awvalid,
+ I3 => s_axi_bready,
+ I4 => \^s_axi_bvalid\,
+ O => aw_en_i_1_n_0
+ );
+aw_en_reg: unisim.vcomponents.FDSE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => aw_en_i_1_n_0,
+ Q => aw_en_reg_n_0,
+ S => s_axi_awready_s_reg_0
+ );
+s_axi_awready_s0: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"80"
+ )
+ port map (
+ I0 => s_axi_awvalid,
+ I1 => s_axi_wvalid,
+ I2 => aw_en_reg_n_0,
+ O => \s_axi_awready_s0__0\
+ );
+s_axi_awready_s_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => \s_axi_awready_s0__0\,
+ Q => s_axi_awready,
+ R => s_axi_awready_s_reg_0
+ );
+s_axi_bvalid_s_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"8F88"
+ )
+ port map (
+ I0 => \^s_axi_wready\,
+ I1 => s_axi_wvalid,
+ I2 => s_axi_bready,
+ I3 => \^s_axi_bvalid\,
+ O => s_axi_bvalid_s_i_1_n_0
+ );
+s_axi_bvalid_s_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_axi_bvalid_s_i_1_n_0,
+ Q => \^s_axi_bvalid\,
+ R => s_axi_awready_s_reg_0
+ );
+s_axi_wready_s_i_1: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0080"
+ )
+ port map (
+ I0 => aw_en_reg_n_0,
+ I1 => s_axi_wvalid,
+ I2 => s_axi_awvalid,
+ I3 => \^s_axi_wready\,
+ O => s_axi_wready_s0
+ );
+s_axi_wready_s_reg: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => s_axi_aclk,
+ CE => '1',
+ D => s_axi_wready_s0,
+ Q => \^s_axi_wready\,
+ R => s_axi_awready_s_reg_0
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs is
+ port (
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ SR : in STD_LOGIC_VECTOR ( 0 to 0 );
+ E : in STD_LOGIC_VECTOR ( 0 to 0 );
+ D : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_aclk : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs : entity is "hog_build_info_regs";
+end mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs is
+begin
+\rd_data_s_reg[0]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(0),
+ Q => s_axi_rdata(0),
+ R => SR(0)
+ );
+\rd_data_s_reg[10]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(10),
+ Q => s_axi_rdata(10),
+ R => SR(0)
+ );
+\rd_data_s_reg[11]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(11),
+ Q => s_axi_rdata(11),
+ R => SR(0)
+ );
+\rd_data_s_reg[12]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(12),
+ Q => s_axi_rdata(12),
+ R => SR(0)
+ );
+\rd_data_s_reg[13]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(13),
+ Q => s_axi_rdata(13),
+ R => SR(0)
+ );
+\rd_data_s_reg[14]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(14),
+ Q => s_axi_rdata(14),
+ R => SR(0)
+ );
+\rd_data_s_reg[15]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(15),
+ Q => s_axi_rdata(15),
+ R => SR(0)
+ );
+\rd_data_s_reg[16]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(16),
+ Q => s_axi_rdata(16),
+ R => SR(0)
+ );
+\rd_data_s_reg[17]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(17),
+ Q => s_axi_rdata(17),
+ R => SR(0)
+ );
+\rd_data_s_reg[18]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(18),
+ Q => s_axi_rdata(18),
+ R => SR(0)
+ );
+\rd_data_s_reg[19]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(19),
+ Q => s_axi_rdata(19),
+ R => SR(0)
+ );
+\rd_data_s_reg[1]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(1),
+ Q => s_axi_rdata(1),
+ R => SR(0)
+ );
+\rd_data_s_reg[20]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(20),
+ Q => s_axi_rdata(20),
+ R => SR(0)
+ );
+\rd_data_s_reg[21]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(21),
+ Q => s_axi_rdata(21),
+ R => SR(0)
+ );
+\rd_data_s_reg[22]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(22),
+ Q => s_axi_rdata(22),
+ R => SR(0)
+ );
+\rd_data_s_reg[23]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(23),
+ Q => s_axi_rdata(23),
+ R => SR(0)
+ );
+\rd_data_s_reg[24]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(24),
+ Q => s_axi_rdata(24),
+ R => SR(0)
+ );
+\rd_data_s_reg[25]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(25),
+ Q => s_axi_rdata(25),
+ R => SR(0)
+ );
+\rd_data_s_reg[26]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(26),
+ Q => s_axi_rdata(26),
+ R => SR(0)
+ );
+\rd_data_s_reg[27]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(27),
+ Q => s_axi_rdata(27),
+ R => SR(0)
+ );
+\rd_data_s_reg[28]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(28),
+ Q => s_axi_rdata(28),
+ R => SR(0)
+ );
+\rd_data_s_reg[29]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(29),
+ Q => s_axi_rdata(29),
+ R => SR(0)
+ );
+\rd_data_s_reg[2]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(2),
+ Q => s_axi_rdata(2),
+ R => SR(0)
+ );
+\rd_data_s_reg[30]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(30),
+ Q => s_axi_rdata(30),
+ R => SR(0)
+ );
+\rd_data_s_reg[31]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(31),
+ Q => s_axi_rdata(31),
+ R => SR(0)
+ );
+\rd_data_s_reg[3]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(3),
+ Q => s_axi_rdata(3),
+ R => SR(0)
+ );
+\rd_data_s_reg[4]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(4),
+ Q => s_axi_rdata(4),
+ R => SR(0)
+ );
+\rd_data_s_reg[5]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(5),
+ Q => s_axi_rdata(5),
+ R => SR(0)
+ );
+\rd_data_s_reg[6]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(6),
+ Q => s_axi_rdata(6),
+ R => SR(0)
+ );
+\rd_data_s_reg[7]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(7),
+ Q => s_axi_rdata(7),
+ R => SR(0)
+ );
+\rd_data_s_reg[8]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(8),
+ Q => s_axi_rdata(8),
+ R => SR(0)
+ );
+\rd_data_s_reg[9]\: unisim.vcomponents.FDRE
+ port map (
+ C => s_axi_aclk,
+ CE => E(0),
+ D => D(9),
+ Q => s_axi_rdata(9),
+ R => SR(0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if is
+ port (
+ s_axi_wready : out STD_LOGIC;
+ SR : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_awready : out STD_LOGIC;
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_arready_s_reg : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ D : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ E : out STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if : entity is "axi4lite_if";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if is
+ signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
+begin
+ SR(0) <= \^sr\(0);
+axi4lite_rd_channel_if_i: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if
+ port map (
+ D(31 downto 0) => D(31 downto 0),
+ E(0) => E(0),
+ hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
+ hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
+ hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
+ hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_aresetn_0 => \^sr\(0),
+ s_axi_arready_s_reg_0 => s_axi_arready_s_reg,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_rready => s_axi_rready,
+ s_axi_rvalid => s_axi_rvalid
+ );
+axi4lite_wr_channel_if_i: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if
+ port map (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_awready => s_axi_awready,
+ s_axi_awready_s_reg_0 => \^sr\(0),
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_wvalid => s_axi_wvalid
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info is
+ port (
+ s_axi_wready : out STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arready_s_reg : out STD_LOGIC;
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_bready : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info : entity is "axi4lite_hog_build_info";
+end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info is
+ signal p_0_in : STD_LOGIC;
+ signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal rd_valid_s : STD_LOGIC;
+begin
+axi4lite_if_inst: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if
+ port map (
+ D(31 downto 0) => p_1_in(31 downto 0),
+ E(0) => rd_valid_s,
+ SR(0) => p_0_in,
+ hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
+ hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
+ hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
+ hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arready_s_reg => s_axi_arready_s_reg,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_rready => s_axi_rready,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_wvalid => s_axi_wvalid
+ );
+hog_build_info_regs_inst: entity work.mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs
+ port map (
+ D(31 downto 0) => p_1_in(31 downto 0),
+ E(0) => rd_valid_s,
+ SR(0) => p_0_in,
+ s_axi_aclk => s_axi_aclk,
+ s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0)
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity mb_design_1_axi4lite_hog_build_i_0_0 is
+ port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of mb_design_1_axi4lite_hog_build_i_0_0 : entity is true;
+ attribute CHECK_LICENSE_TYPE : string;
+ attribute CHECK_LICENSE_TYPE of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}";
+ attribute downgradeipidentifiedwarnings : string;
+ attribute downgradeipidentifiedwarnings of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "yes";
+ attribute ip_definition_source : string;
+ attribute ip_definition_source of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "module_ref";
+ attribute x_core_info : string;
+ attribute x_core_info of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "axi4lite_hog_build_info,Vivado 2024.1.2";
+end mb_design_1_axi4lite_hog_build_i_0_0;
+
+architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0 is
+ signal \<const0>\ : STD_LOGIC;
+ attribute x_interface_info : string;
+ attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
+ attribute x_interface_parameter : string;
+ attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
+ attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
+ attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
+ attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
+ attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
+ attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
+ attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 s_axi BREADY";
+ attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi BVALID";
+ attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 s_axi RREADY";
+ attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi RVALID";
+ attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 s_axi WREADY";
+ attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi WVALID";
+ attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
+ attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
+ attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 s_axi BRESP";
+ attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 s_axi RDATA";
+ attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 s_axi RRESP";
+ attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 s_axi WDATA";
+ attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
+begin
+ s_axi_bresp(1) <= \<const0>\;
+ s_axi_bresp(0) <= \<const0>\;
+ s_axi_rresp(1) <= \<const0>\;
+ s_axi_rresp(0) <= \<const0>\;
+GND: unisim.vcomponents.GND
+ port map (
+ G => \<const0>\
+ );
+U0: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info
+ port map (
+ hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
+ hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
+ hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
+ hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
+ s_axi_aclk => s_axi_aclk,
+ s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_arready_s_reg => s_axi_arready,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
+ s_axi_rready => s_axi_rready,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_wvalid => s_axi_wvalid
+ );
+end STRUCTURE;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
new file mode 100644
index 0000000000000000000000000000000000000000..7d313d63019db586cb51cede39a5fa90242f19c2
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
@@ -0,0 +1,48 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+// Date : Thu Mar 20 18:25:04 2025
+// Host : hogtest running 64-bit unknown
+// Command : write_verilog -force -mode synth_stub
+// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
+// Design : mb_design_1_axi4lite_hog_build_i_0_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi4lite_hog_build_info,Vivado 2024.1.2" *)
+module mb_design_1_axi4lite_hog_build_i_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
+ s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
+ s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
+ s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, hog_global_date_i, hog_global_time_i,
+ hog_global_ver_i, hog_global_sha_i)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,hog_global_date_i[31:0],hog_global_time_i[31:0],hog_global_ver_i[31:0],hog_global_sha_i[31:0]" */
+/* synthesis syn_force_seq_prim="s_axi_aclk" */;
+ input s_axi_aclk /* synthesis syn_isclock = 1 */;
+ input s_axi_aresetn;
+ input [31:0]s_axi_awaddr;
+ input s_axi_awvalid;
+ output s_axi_awready;
+ input [31:0]s_axi_wdata;
+ input [3:0]s_axi_wstrb;
+ input s_axi_wvalid;
+ output s_axi_wready;
+ output [1:0]s_axi_bresp;
+ output s_axi_bvalid;
+ input s_axi_bready;
+ input [31:0]s_axi_araddr;
+ input s_axi_arvalid;
+ output s_axi_arready;
+ output [31:0]s_axi_rdata;
+ output [1:0]s_axi_rresp;
+ output s_axi_rvalid;
+ input s_axi_rready;
+ input [31:0]hog_global_date_i;
+ input [31:0]hog_global_time_i;
+ input [31:0]hog_global_ver_i;
+ input [31:0]hog_global_sha_i;
+endmodule
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..2a42350f908ae63ce7306f2198a299309ed70c82
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
@@ -0,0 +1,53 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
+-- Date : Thu Mar 20 18:25:04 2025
+-- Host : hogtest running 64-bit unknown
+-- Command : write_vhdl -force -mode synth_stub
+-- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
+-- Design : mb_design_1_axi4lite_hog_build_i_0_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity mb_design_1_axi4lite_hog_build_i_0_0 is
+ Port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+
+end mb_design_1_axi4lite_hog_build_i_0_0;
+
+architecture stub of mb_design_1_axi4lite_hog_build_i_0_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,hog_global_date_i[31:0],hog_global_time_i[31:0],hog_global_ver_i[31:0],hog_global_sha_i[31:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi4lite_hog_build_info,Vivado 2024.1.2";
+begin
+end;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b785979ae0919f991bc8b4608df207fdf9f4eec5
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd
@@ -0,0 +1,172 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axi4lite_hog_build_info:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY mb_design_1_axi4lite_hog_build_i_0_0 IS
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+END mb_design_1_axi4lite_hog_build_i_0_0;
+
+ARCHITECTURE mb_design_1_axi4lite_hog_build_i_0_0_arch OF mb_design_1_axi4lite_hog_build_i_0_0 IS
+ ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+ ATTRIBUTE DowngradeIPIdentifiedWarnings OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "yes";
+ COMPONENT axi4lite_hog_build_info IS
+ GENERIC (
+ C_ADDR_WIDTH : INTEGER
+ );
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+ END COMPONENT axi4lite_hog_build_info;
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" &
+", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
+BEGIN
+ U0 : axi4lite_hog_build_info
+ GENERIC MAP (
+ C_ADDR_WIDTH => 32
+ )
+ PORT MAP (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_arready => s_axi_arready,
+ s_axi_rdata => s_axi_rdata,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_rready => s_axi_rready,
+ hog_global_date_i => hog_global_date_i,
+ hog_global_time_i => hog_global_time_i,
+ hog_global_ver_i => hog_global_ver_i,
+ hog_global_sha_i => hog_global_sha_i
+ );
+END mb_design_1_axi4lite_hog_build_i_0_0_arch;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1ba8a04793fcd97a509c05a9de0f7dff48b61d71
--- /dev/null
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd
@@ -0,0 +1,180 @@
+-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of AMD and is protected under U.S. and international copyright
+-- and other intellectual property laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- AMD, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) AMD shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or AMD had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- AMD products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of AMD products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:module_ref:axi4lite_hog_build_info:1.0
+-- IP Revision: 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY mb_design_1_axi4lite_hog_build_i_0_0 IS
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+END mb_design_1_axi4lite_hog_build_i_0_0;
+
+ARCHITECTURE mb_design_1_axi4lite_hog_build_i_0_0_arch OF mb_design_1_axi4lite_hog_build_i_0_0 IS
+ ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+ ATTRIBUTE DowngradeIPIdentifiedWarnings OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "yes";
+ COMPONENT axi4lite_hog_build_info IS
+ GENERIC (
+ C_ADDR_WIDTH : INTEGER
+ );
+ PORT (
+ s_axi_aclk : IN STD_LOGIC;
+ s_axi_aresetn : IN STD_LOGIC;
+ s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_awvalid : IN STD_LOGIC;
+ s_axi_awready : OUT STD_LOGIC;
+ s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ s_axi_wvalid : IN STD_LOGIC;
+ s_axi_wready : OUT STD_LOGIC;
+ s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_bvalid : OUT STD_LOGIC;
+ s_axi_bready : IN STD_LOGIC;
+ s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_arvalid : IN STD_LOGIC;
+ s_axi_arready : OUT STD_LOGIC;
+ s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ s_axi_rvalid : OUT STD_LOGIC;
+ s_axi_rready : IN STD_LOGIC;
+ hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+ );
+ END COMPONENT axi4lite_hog_build_info;
+ ATTRIBUTE X_CORE_INFO : STRING;
+ ATTRIBUTE X_CORE_INFO OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "axi4lite_hog_build_info,Vivado 2024.1.2";
+ ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+ ATTRIBUTE CHECK_LICENSE_TYPE OF mb_design_1_axi4lite_hog_build_i_0_0_arch : ARCHITECTURE IS "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}";
+ ATTRIBUTE CORE_GENERATION_INFO : STRING;
+ ATTRIBUTE CORE_GENERATION_INFO OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axi4lite_hog_build_info,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ADDR_WIDTH=32}";
+ ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
+ ATTRIBUTE IP_DEFINITION_SOURCE OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "module_ref";
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
+ ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" &
+", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
+ ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
+BEGIN
+ U0 : axi4lite_hog_build_info
+ GENERIC MAP (
+ C_ADDR_WIDTH => 32
+ )
+ PORT MAP (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_arready => s_axi_arready,
+ s_axi_rdata => s_axi_rdata,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_rready => s_axi_rready,
+ hog_global_date_i => hog_global_date_i,
+ hog_global_time_i => hog_global_time_i,
+ hog_global_ver_i => hog_global_ver_i,
+ hog_global_sha_i => hog_global_sha_i
+ );
+END mb_design_1_axi4lite_hog_build_i_0_0_arch;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.dcp b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.dcp
index b5ba35c713b25f4de222401dca2873080886b8e7..cecaabf140d08998f6be5d2df95097ed7e5dd1fd 100644
Binary files a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.dcp and b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.dcp differ
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
index e6405dfaf8698a91b978b0a3e6f9906fa52e2fb6..8624f8deb94fa0f6207b642fa8c69a4c7f04acf5 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
@@ -2638,7 +2638,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:37:17 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:30 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -2656,11 +2656,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:d418c950</spirit:value>
+ <spirit:value>9:8ca2308d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -2680,7 +2680,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:f2268312</spirit:value>
+ <spirit:value>9:732b1e1c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -2696,11 +2696,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:f2268312</spirit:value>
+ <spirit:value>9:732b1e1c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -2720,7 +2720,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:d418c950</spirit:value>
+ <spirit:value>9:8ca2308d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -2736,11 +2736,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:d418c950</spirit:value>
+ <spirit:value>9:8ca2308d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.v
index c54c810b54d215d4cf1a31e3ab85f0d714ef89f6..bf7508ebd76e903dc93389c45f66dd5e399e33eb 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.v
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.v
@@ -2,10 +2,10 @@
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-// Date : Tue Mar 4 22:37:17 2025
+// Date : Thu Mar 20 17:31:20 2025
// Host : hogtest running 64-bit unknown
-// Command : write_verilog -force -mode funcsim
-// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.v
+// Command : write_verilog -force -mode funcsim -rename_top mb_design_1_lmb_bram_if_cntlr_0_0 -prefix
+// mb_design_1_lmb_bram_if_cntlr_0_0_ mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.v
// Design : mb_design_1_lmb_bram_if_cntlr_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -13,9 +13,18 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
-(* CHECK_LICENSE_TYPE = "mb_design_1_lmb_bram_if_cntlr_0_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2024.1.2" *)
-(* NotValidForBitStream *)
-module mb_design_1_lmb_bram_if_cntlr_0_0
+(* C_ARBITRATION = "0" *) (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *)
+(* C_CE_COUNTER_WIDTH = "0" *) (* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *)
+(* C_ECC_ONOFF_REGISTER = "0" *) (* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *)
+(* C_FAMILY = "artix7" *) (* C_FAULT_INJECT = "0" *) (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000000111111111111111" *)
+(* C_INTERCONNECT = "0" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *)
+(* C_LMB_PROTOCOL = "0" *) (* C_MASK = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK4 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+(* C_MASK5 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK6 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK7 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+(* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
+(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *)
+(* C_WRITE_ACCESS = "2" *)
+module mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr
(LMB_Clk,
LMB_Rst,
LMB_ABus,
@@ -29,40 +38,234 @@ module mb_design_1_lmb_bram_if_cntlr_0_0
Sl_Wait,
Sl_UE,
Sl_CE,
+ LMB1_ABus,
+ LMB1_WriteDBus,
+ LMB1_AddrStrobe,
+ LMB1_ReadStrobe,
+ LMB1_WriteStrobe,
+ LMB1_BE,
+ Sl1_DBus,
+ Sl1_Ready,
+ Sl1_Wait,
+ Sl1_UE,
+ Sl1_CE,
+ LMB2_ABus,
+ LMB2_WriteDBus,
+ LMB2_AddrStrobe,
+ LMB2_ReadStrobe,
+ LMB2_WriteStrobe,
+ LMB2_BE,
+ Sl2_DBus,
+ Sl2_Ready,
+ Sl2_Wait,
+ Sl2_UE,
+ Sl2_CE,
+ LMB3_ABus,
+ LMB3_WriteDBus,
+ LMB3_AddrStrobe,
+ LMB3_ReadStrobe,
+ LMB3_WriteStrobe,
+ LMB3_BE,
+ Sl3_DBus,
+ Sl3_Ready,
+ Sl3_Wait,
+ Sl3_UE,
+ Sl3_CE,
+ LMB4_ABus,
+ LMB4_WriteDBus,
+ LMB4_AddrStrobe,
+ LMB4_ReadStrobe,
+ LMB4_WriteStrobe,
+ LMB4_BE,
+ Sl4_DBus,
+ Sl4_Ready,
+ Sl4_Wait,
+ Sl4_UE,
+ Sl4_CE,
+ LMB5_ABus,
+ LMB5_WriteDBus,
+ LMB5_AddrStrobe,
+ LMB5_ReadStrobe,
+ LMB5_WriteStrobe,
+ LMB5_BE,
+ Sl5_DBus,
+ Sl5_Ready,
+ Sl5_Wait,
+ Sl5_UE,
+ Sl5_CE,
+ LMB6_ABus,
+ LMB6_WriteDBus,
+ LMB6_AddrStrobe,
+ LMB6_ReadStrobe,
+ LMB6_WriteStrobe,
+ LMB6_BE,
+ Sl6_DBus,
+ Sl6_Ready,
+ Sl6_Wait,
+ Sl6_UE,
+ Sl6_CE,
+ LMB7_ABus,
+ LMB7_WriteDBus,
+ LMB7_AddrStrobe,
+ LMB7_ReadStrobe,
+ LMB7_WriteStrobe,
+ LMB7_BE,
+ Sl7_DBus,
+ Sl7_Ready,
+ Sl7_Wait,
+ Sl7_UE,
+ Sl7_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
- BRAM_Din_A);
- (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3:SLMB4:SLMB5:SLMB6:SLMB7, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
- (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
- (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 32768, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
- (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
+ BRAM_Din_A,
+ S_AXI_CTRL_ACLK,
+ S_AXI_CTRL_ARESETN,
+ S_AXI_CTRL_AWADDR,
+ S_AXI_CTRL_AWVALID,
+ S_AXI_CTRL_AWREADY,
+ S_AXI_CTRL_WDATA,
+ S_AXI_CTRL_WSTRB,
+ S_AXI_CTRL_WVALID,
+ S_AXI_CTRL_WREADY,
+ S_AXI_CTRL_BRESP,
+ S_AXI_CTRL_BVALID,
+ S_AXI_CTRL_BREADY,
+ S_AXI_CTRL_ARADDR,
+ S_AXI_CTRL_ARVALID,
+ S_AXI_CTRL_ARREADY,
+ S_AXI_CTRL_RDATA,
+ S_AXI_CTRL_RRESP,
+ S_AXI_CTRL_RVALID,
+ S_AXI_CTRL_RREADY,
+ UE,
+ CE,
+ Interrupt);
+ input LMB_Clk;
+ input LMB_Rst;
+ input [0:31]LMB_ABus;
+ input [0:31]LMB_WriteDBus;
+ input LMB_AddrStrobe;
+ input LMB_ReadStrobe;
+ input LMB_WriteStrobe;
+ input [0:3]LMB_BE;
+ output [0:31]Sl_DBus;
+ output Sl_Ready;
+ output Sl_Wait;
+ output Sl_UE;
+ output Sl_CE;
+ input [0:31]LMB1_ABus;
+ input [0:31]LMB1_WriteDBus;
+ input LMB1_AddrStrobe;
+ input LMB1_ReadStrobe;
+ input LMB1_WriteStrobe;
+ input [0:3]LMB1_BE;
+ output [0:31]Sl1_DBus;
+ output Sl1_Ready;
+ output Sl1_Wait;
+ output Sl1_UE;
+ output Sl1_CE;
+ input [0:31]LMB2_ABus;
+ input [0:31]LMB2_WriteDBus;
+ input LMB2_AddrStrobe;
+ input LMB2_ReadStrobe;
+ input LMB2_WriteStrobe;
+ input [0:3]LMB2_BE;
+ output [0:31]Sl2_DBus;
+ output Sl2_Ready;
+ output Sl2_Wait;
+ output Sl2_UE;
+ output Sl2_CE;
+ input [0:31]LMB3_ABus;
+ input [0:31]LMB3_WriteDBus;
+ input LMB3_AddrStrobe;
+ input LMB3_ReadStrobe;
+ input LMB3_WriteStrobe;
+ input [0:3]LMB3_BE;
+ output [0:31]Sl3_DBus;
+ output Sl3_Ready;
+ output Sl3_Wait;
+ output Sl3_UE;
+ output Sl3_CE;
+ input [0:31]LMB4_ABus;
+ input [0:31]LMB4_WriteDBus;
+ input LMB4_AddrStrobe;
+ input LMB4_ReadStrobe;
+ input LMB4_WriteStrobe;
+ input [0:3]LMB4_BE;
+ output [0:31]Sl4_DBus;
+ output Sl4_Ready;
+ output Sl4_Wait;
+ output Sl4_UE;
+ output Sl4_CE;
+ input [0:31]LMB5_ABus;
+ input [0:31]LMB5_WriteDBus;
+ input LMB5_AddrStrobe;
+ input LMB5_ReadStrobe;
+ input LMB5_WriteStrobe;
+ input [0:3]LMB5_BE;
+ output [0:31]Sl5_DBus;
+ output Sl5_Ready;
+ output Sl5_Wait;
+ output Sl5_UE;
+ output Sl5_CE;
+ input [0:31]LMB6_ABus;
+ input [0:31]LMB6_WriteDBus;
+ input LMB6_AddrStrobe;
+ input LMB6_ReadStrobe;
+ input LMB6_WriteStrobe;
+ input [0:3]LMB6_BE;
+ output [0:31]Sl6_DBus;
+ output Sl6_Ready;
+ output Sl6_Wait;
+ output Sl6_UE;
+ output Sl6_CE;
+ input [0:31]LMB7_ABus;
+ input [0:31]LMB7_WriteDBus;
+ input LMB7_AddrStrobe;
+ input LMB7_ReadStrobe;
+ input LMB7_WriteStrobe;
+ input [0:3]LMB7_BE;
+ output [0:31]Sl7_DBus;
+ output Sl7_Ready;
+ output Sl7_Wait;
+ output Sl7_UE;
+ output Sl7_CE;
+ output BRAM_Rst_A;
+ output BRAM_Clk_A;
+ output [0:31]BRAM_Addr_A;
+ output BRAM_EN_A;
+ output [0:3]BRAM_WEN_A;
+ output [0:31]BRAM_Dout_A;
+ input [0:31]BRAM_Din_A;
+ input S_AXI_CTRL_ACLK;
+ input S_AXI_CTRL_ARESETN;
+ input [31:0]S_AXI_CTRL_AWADDR;
+ input S_AXI_CTRL_AWVALID;
+ output S_AXI_CTRL_AWREADY;
+ input [31:0]S_AXI_CTRL_WDATA;
+ input [3:0]S_AXI_CTRL_WSTRB;
+ input S_AXI_CTRL_WVALID;
+ output S_AXI_CTRL_WREADY;
+ output [1:0]S_AXI_CTRL_BRESP;
+ output S_AXI_CTRL_BVALID;
+ input S_AXI_CTRL_BREADY;
+ input [31:0]S_AXI_CTRL_ARADDR;
+ input S_AXI_CTRL_ARVALID;
+ output S_AXI_CTRL_ARREADY;
+ output [31:0]S_AXI_CTRL_RDATA;
+ output [1:0]S_AXI_CTRL_RRESP;
+ output S_AXI_CTRL_RVALID;
+ input S_AXI_CTRL_RREADY;
+ output UE;
+ output CE;
+ output Interrupt;
wire \<const0> ;
- wire [0:31]BRAM_Addr_A;
- wire BRAM_Clk_A;
wire [0:31]BRAM_Din_A;
- wire [0:31]BRAM_Dout_A;
- wire BRAM_EN_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
@@ -71,489 +274,16 @@ module mb_design_1_lmb_bram_if_cntlr_0_0
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
- wire [0:31]Sl_DBus;
+ wire \No_ECC.Sl_Rdy_i_1_n_0 ;
+ wire \No_ECC.lmb_as_i_1_n_0 ;
+ wire Sl_Rdy;
wire Sl_Ready;
- wire NLW_U0_BRAM_Rst_A_UNCONNECTED;
- wire NLW_U0_CE_UNCONNECTED;
- wire NLW_U0_Interrupt_UNCONNECTED;
- wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
- wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
- wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
- wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
- wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
- wire NLW_U0_Sl1_CE_UNCONNECTED;
- wire NLW_U0_Sl1_Ready_UNCONNECTED;
- wire NLW_U0_Sl1_UE_UNCONNECTED;
- wire NLW_U0_Sl1_Wait_UNCONNECTED;
- wire NLW_U0_Sl2_CE_UNCONNECTED;
- wire NLW_U0_Sl2_Ready_UNCONNECTED;
- wire NLW_U0_Sl2_UE_UNCONNECTED;
- wire NLW_U0_Sl2_Wait_UNCONNECTED;
- wire NLW_U0_Sl3_CE_UNCONNECTED;
- wire NLW_U0_Sl3_Ready_UNCONNECTED;
- wire NLW_U0_Sl3_UE_UNCONNECTED;
- wire NLW_U0_Sl3_Wait_UNCONNECTED;
- wire NLW_U0_Sl4_CE_UNCONNECTED;
- wire NLW_U0_Sl4_Ready_UNCONNECTED;
- wire NLW_U0_Sl4_UE_UNCONNECTED;
- wire NLW_U0_Sl4_Wait_UNCONNECTED;
- wire NLW_U0_Sl5_CE_UNCONNECTED;
- wire NLW_U0_Sl5_Ready_UNCONNECTED;
- wire NLW_U0_Sl5_UE_UNCONNECTED;
- wire NLW_U0_Sl5_Wait_UNCONNECTED;
- wire NLW_U0_Sl6_CE_UNCONNECTED;
- wire NLW_U0_Sl6_Ready_UNCONNECTED;
- wire NLW_U0_Sl6_UE_UNCONNECTED;
- wire NLW_U0_Sl6_Wait_UNCONNECTED;
- wire NLW_U0_Sl7_CE_UNCONNECTED;
- wire NLW_U0_Sl7_Ready_UNCONNECTED;
- wire NLW_U0_Sl7_UE_UNCONNECTED;
- wire NLW_U0_Sl7_Wait_UNCONNECTED;
- wire NLW_U0_Sl_CE_UNCONNECTED;
- wire NLW_U0_Sl_UE_UNCONNECTED;
- wire NLW_U0_Sl_Wait_UNCONNECTED;
- wire NLW_U0_UE_UNCONNECTED;
- wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
- wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
- wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
- wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
- wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
- wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
- wire [0:31]NLW_U0_Sl4_DBus_UNCONNECTED;
- wire [0:31]NLW_U0_Sl5_DBus_UNCONNECTED;
- wire [0:31]NLW_U0_Sl6_DBus_UNCONNECTED;
- wire [0:31]NLW_U0_Sl7_DBus_UNCONNECTED;
+ wire lmb_as;
- assign BRAM_Rst_A = \<const0> ;
- assign Sl_CE = \<const0> ;
- assign Sl_UE = \<const0> ;
- assign Sl_Wait = \<const0> ;
- GND GND
- (.G(\<const0> ));
- (* C_ARBITRATION = "0" *)
- (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_BRAM_AWIDTH = "32" *)
- (* C_CE_COUNTER_WIDTH = "0" *)
- (* C_CE_FAILING_REGISTERS = "0" *)
- (* C_ECC = "0" *)
- (* C_ECC_ONOFF_REGISTER = "0" *)
- (* C_ECC_ONOFF_RESET_VALUE = "1" *)
- (* C_ECC_STATUS_REGISTERS = "0" *)
- (* C_FAMILY = "artix7" *)
- (* C_FAULT_INJECT = "0" *)
- (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000000111111111111111" *)
- (* C_INTERCONNECT = "0" *)
- (* C_LMB_AWIDTH = "32" *)
- (* C_LMB_DWIDTH = "32" *)
- (* C_LMB_PROTOCOL = "0" *)
- (* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *)
- (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_MASK4 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_MASK5 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_MASK6 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_MASK7 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
- (* C_NUM_LMB = "1" *)
- (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
- (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
- (* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
- (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
- (* C_UE_FAILING_REGISTERS = "0" *)
- (* C_WRITE_ACCESS = "2" *)
- mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr U0
- (.BRAM_Addr_A(BRAM_Addr_A),
- .BRAM_Clk_A(BRAM_Clk_A),
- .BRAM_Din_A(BRAM_Din_A),
- .BRAM_Dout_A(BRAM_Dout_A),
- .BRAM_EN_A(BRAM_EN_A),
- .BRAM_Rst_A(NLW_U0_BRAM_Rst_A_UNCONNECTED),
- .BRAM_WEN_A(BRAM_WEN_A),
- .CE(NLW_U0_CE_UNCONNECTED),
- .Interrupt(NLW_U0_Interrupt_UNCONNECTED),
- .LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB1_AddrStrobe(1'b0),
- .LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB1_ReadStrobe(1'b0),
- .LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB1_WriteStrobe(1'b0),
- .LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB2_AddrStrobe(1'b0),
- .LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB2_ReadStrobe(1'b0),
- .LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB2_WriteStrobe(1'b0),
- .LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB3_AddrStrobe(1'b0),
- .LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB3_ReadStrobe(1'b0),
- .LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB3_WriteStrobe(1'b0),
- .LMB4_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB4_AddrStrobe(1'b0),
- .LMB4_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB4_ReadStrobe(1'b0),
- .LMB4_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB4_WriteStrobe(1'b0),
- .LMB5_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB5_AddrStrobe(1'b0),
- .LMB5_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB5_ReadStrobe(1'b0),
- .LMB5_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB5_WriteStrobe(1'b0),
- .LMB6_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB6_AddrStrobe(1'b0),
- .LMB6_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB6_ReadStrobe(1'b0),
- .LMB6_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB6_WriteStrobe(1'b0),
- .LMB7_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB7_AddrStrobe(1'b0),
- .LMB7_BE({1'b0,1'b0,1'b0,1'b0}),
- .LMB7_ReadStrobe(1'b0),
- .LMB7_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .LMB7_WriteStrobe(1'b0),
- .LMB_ABus(LMB_ABus),
- .LMB_AddrStrobe(LMB_AddrStrobe),
- .LMB_BE(LMB_BE),
- .LMB_Clk(LMB_Clk),
- .LMB_ReadStrobe(1'b0),
- .LMB_Rst(LMB_Rst),
- .LMB_WriteDBus(LMB_WriteDBus),
- .LMB_WriteStrobe(LMB_WriteStrobe),
- .S_AXI_CTRL_ACLK(1'b0),
- .S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_CTRL_ARESETN(1'b0),
- .S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
- .S_AXI_CTRL_ARVALID(1'b0),
- .S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
- .S_AXI_CTRL_AWVALID(1'b0),
- .S_AXI_CTRL_BREADY(1'b0),
- .S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
- .S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
- .S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
- .S_AXI_CTRL_RREADY(1'b0),
- .S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
- .S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
- .S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
- .S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_CTRL_WVALID(1'b0),
- .Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
- .Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
- .Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
- .Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
- .Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
- .Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
- .Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
- .Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
- .Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
- .Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
- .Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
- .Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
- .Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
- .Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
- .Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
- .Sl4_CE(NLW_U0_Sl4_CE_UNCONNECTED),
- .Sl4_DBus(NLW_U0_Sl4_DBus_UNCONNECTED[0:31]),
- .Sl4_Ready(NLW_U0_Sl4_Ready_UNCONNECTED),
- .Sl4_UE(NLW_U0_Sl4_UE_UNCONNECTED),
- .Sl4_Wait(NLW_U0_Sl4_Wait_UNCONNECTED),
- .Sl5_CE(NLW_U0_Sl5_CE_UNCONNECTED),
- .Sl5_DBus(NLW_U0_Sl5_DBus_UNCONNECTED[0:31]),
- .Sl5_Ready(NLW_U0_Sl5_Ready_UNCONNECTED),
- .Sl5_UE(NLW_U0_Sl5_UE_UNCONNECTED),
- .Sl5_Wait(NLW_U0_Sl5_Wait_UNCONNECTED),
- .Sl6_CE(NLW_U0_Sl6_CE_UNCONNECTED),
- .Sl6_DBus(NLW_U0_Sl6_DBus_UNCONNECTED[0:31]),
- .Sl6_Ready(NLW_U0_Sl6_Ready_UNCONNECTED),
- .Sl6_UE(NLW_U0_Sl6_UE_UNCONNECTED),
- .Sl6_Wait(NLW_U0_Sl6_Wait_UNCONNECTED),
- .Sl7_CE(NLW_U0_Sl7_CE_UNCONNECTED),
- .Sl7_DBus(NLW_U0_Sl7_DBus_UNCONNECTED[0:31]),
- .Sl7_Ready(NLW_U0_Sl7_Ready_UNCONNECTED),
- .Sl7_UE(NLW_U0_Sl7_UE_UNCONNECTED),
- .Sl7_Wait(NLW_U0_Sl7_Wait_UNCONNECTED),
- .Sl_CE(NLW_U0_Sl_CE_UNCONNECTED),
- .Sl_DBus(Sl_DBus),
- .Sl_Ready(Sl_Ready),
- .Sl_UE(NLW_U0_Sl_UE_UNCONNECTED),
- .Sl_Wait(NLW_U0_Sl_Wait_UNCONNECTED),
- .UE(NLW_U0_UE_UNCONNECTED));
-endmodule
-
-(* C_ARBITRATION = "0" *) (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *)
-(* C_CE_COUNTER_WIDTH = "0" *) (* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *)
-(* C_ECC_ONOFF_REGISTER = "0" *) (* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *)
-(* C_FAMILY = "artix7" *) (* C_FAULT_INJECT = "0" *) (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000000111111111111111" *)
-(* C_INTERCONNECT = "0" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *)
-(* C_LMB_PROTOCOL = "0" *) (* C_MASK = "64'b0000000000000000000000000000000001000000000000000000000000000000" *) (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
-(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK4 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
-(* C_MASK5 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK6 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK7 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
-(* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
-(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *)
-(* C_WRITE_ACCESS = "2" *) (* ORIG_REF_NAME = "lmb_bram_if_cntlr" *)
-module mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr
- (LMB_Clk,
- LMB_Rst,
- LMB_ABus,
- LMB_WriteDBus,
- LMB_AddrStrobe,
- LMB_ReadStrobe,
- LMB_WriteStrobe,
- LMB_BE,
- Sl_DBus,
- Sl_Ready,
- Sl_Wait,
- Sl_UE,
- Sl_CE,
- LMB1_ABus,
- LMB1_WriteDBus,
- LMB1_AddrStrobe,
- LMB1_ReadStrobe,
- LMB1_WriteStrobe,
- LMB1_BE,
- Sl1_DBus,
- Sl1_Ready,
- Sl1_Wait,
- Sl1_UE,
- Sl1_CE,
- LMB2_ABus,
- LMB2_WriteDBus,
- LMB2_AddrStrobe,
- LMB2_ReadStrobe,
- LMB2_WriteStrobe,
- LMB2_BE,
- Sl2_DBus,
- Sl2_Ready,
- Sl2_Wait,
- Sl2_UE,
- Sl2_CE,
- LMB3_ABus,
- LMB3_WriteDBus,
- LMB3_AddrStrobe,
- LMB3_ReadStrobe,
- LMB3_WriteStrobe,
- LMB3_BE,
- Sl3_DBus,
- Sl3_Ready,
- Sl3_Wait,
- Sl3_UE,
- Sl3_CE,
- LMB4_ABus,
- LMB4_WriteDBus,
- LMB4_AddrStrobe,
- LMB4_ReadStrobe,
- LMB4_WriteStrobe,
- LMB4_BE,
- Sl4_DBus,
- Sl4_Ready,
- Sl4_Wait,
- Sl4_UE,
- Sl4_CE,
- LMB5_ABus,
- LMB5_WriteDBus,
- LMB5_AddrStrobe,
- LMB5_ReadStrobe,
- LMB5_WriteStrobe,
- LMB5_BE,
- Sl5_DBus,
- Sl5_Ready,
- Sl5_Wait,
- Sl5_UE,
- Sl5_CE,
- LMB6_ABus,
- LMB6_WriteDBus,
- LMB6_AddrStrobe,
- LMB6_ReadStrobe,
- LMB6_WriteStrobe,
- LMB6_BE,
- Sl6_DBus,
- Sl6_Ready,
- Sl6_Wait,
- Sl6_UE,
- Sl6_CE,
- LMB7_ABus,
- LMB7_WriteDBus,
- LMB7_AddrStrobe,
- LMB7_ReadStrobe,
- LMB7_WriteStrobe,
- LMB7_BE,
- Sl7_DBus,
- Sl7_Ready,
- Sl7_Wait,
- Sl7_UE,
- Sl7_CE,
- BRAM_Rst_A,
- BRAM_Clk_A,
- BRAM_Addr_A,
- BRAM_EN_A,
- BRAM_WEN_A,
- BRAM_Dout_A,
- BRAM_Din_A,
- S_AXI_CTRL_ACLK,
- S_AXI_CTRL_ARESETN,
- S_AXI_CTRL_AWADDR,
- S_AXI_CTRL_AWVALID,
- S_AXI_CTRL_AWREADY,
- S_AXI_CTRL_WDATA,
- S_AXI_CTRL_WSTRB,
- S_AXI_CTRL_WVALID,
- S_AXI_CTRL_WREADY,
- S_AXI_CTRL_BRESP,
- S_AXI_CTRL_BVALID,
- S_AXI_CTRL_BREADY,
- S_AXI_CTRL_ARADDR,
- S_AXI_CTRL_ARVALID,
- S_AXI_CTRL_ARREADY,
- S_AXI_CTRL_RDATA,
- S_AXI_CTRL_RRESP,
- S_AXI_CTRL_RVALID,
- S_AXI_CTRL_RREADY,
- UE,
- CE,
- Interrupt);
- input LMB_Clk;
- input LMB_Rst;
- input [0:31]LMB_ABus;
- input [0:31]LMB_WriteDBus;
- input LMB_AddrStrobe;
- input LMB_ReadStrobe;
- input LMB_WriteStrobe;
- input [0:3]LMB_BE;
- output [0:31]Sl_DBus;
- output Sl_Ready;
- output Sl_Wait;
- output Sl_UE;
- output Sl_CE;
- input [0:31]LMB1_ABus;
- input [0:31]LMB1_WriteDBus;
- input LMB1_AddrStrobe;
- input LMB1_ReadStrobe;
- input LMB1_WriteStrobe;
- input [0:3]LMB1_BE;
- output [0:31]Sl1_DBus;
- output Sl1_Ready;
- output Sl1_Wait;
- output Sl1_UE;
- output Sl1_CE;
- input [0:31]LMB2_ABus;
- input [0:31]LMB2_WriteDBus;
- input LMB2_AddrStrobe;
- input LMB2_ReadStrobe;
- input LMB2_WriteStrobe;
- input [0:3]LMB2_BE;
- output [0:31]Sl2_DBus;
- output Sl2_Ready;
- output Sl2_Wait;
- output Sl2_UE;
- output Sl2_CE;
- input [0:31]LMB3_ABus;
- input [0:31]LMB3_WriteDBus;
- input LMB3_AddrStrobe;
- input LMB3_ReadStrobe;
- input LMB3_WriteStrobe;
- input [0:3]LMB3_BE;
- output [0:31]Sl3_DBus;
- output Sl3_Ready;
- output Sl3_Wait;
- output Sl3_UE;
- output Sl3_CE;
- input [0:31]LMB4_ABus;
- input [0:31]LMB4_WriteDBus;
- input LMB4_AddrStrobe;
- input LMB4_ReadStrobe;
- input LMB4_WriteStrobe;
- input [0:3]LMB4_BE;
- output [0:31]Sl4_DBus;
- output Sl4_Ready;
- output Sl4_Wait;
- output Sl4_UE;
- output Sl4_CE;
- input [0:31]LMB5_ABus;
- input [0:31]LMB5_WriteDBus;
- input LMB5_AddrStrobe;
- input LMB5_ReadStrobe;
- input LMB5_WriteStrobe;
- input [0:3]LMB5_BE;
- output [0:31]Sl5_DBus;
- output Sl5_Ready;
- output Sl5_Wait;
- output Sl5_UE;
- output Sl5_CE;
- input [0:31]LMB6_ABus;
- input [0:31]LMB6_WriteDBus;
- input LMB6_AddrStrobe;
- input LMB6_ReadStrobe;
- input LMB6_WriteStrobe;
- input [0:3]LMB6_BE;
- output [0:31]Sl6_DBus;
- output Sl6_Ready;
- output Sl6_Wait;
- output Sl6_UE;
- output Sl6_CE;
- input [0:31]LMB7_ABus;
- input [0:31]LMB7_WriteDBus;
- input LMB7_AddrStrobe;
- input LMB7_ReadStrobe;
- input LMB7_WriteStrobe;
- input [0:3]LMB7_BE;
- output [0:31]Sl7_DBus;
- output Sl7_Ready;
- output Sl7_Wait;
- output Sl7_UE;
- output Sl7_CE;
- output BRAM_Rst_A;
- output BRAM_Clk_A;
- output [0:31]BRAM_Addr_A;
- output BRAM_EN_A;
- output [0:3]BRAM_WEN_A;
- output [0:31]BRAM_Dout_A;
- input [0:31]BRAM_Din_A;
- input S_AXI_CTRL_ACLK;
- input S_AXI_CTRL_ARESETN;
- input [31:0]S_AXI_CTRL_AWADDR;
- input S_AXI_CTRL_AWVALID;
- output S_AXI_CTRL_AWREADY;
- input [31:0]S_AXI_CTRL_WDATA;
- input [3:0]S_AXI_CTRL_WSTRB;
- input S_AXI_CTRL_WVALID;
- output S_AXI_CTRL_WREADY;
- output [1:0]S_AXI_CTRL_BRESP;
- output S_AXI_CTRL_BVALID;
- input S_AXI_CTRL_BREADY;
- input [31:0]S_AXI_CTRL_ARADDR;
- input S_AXI_CTRL_ARVALID;
- output S_AXI_CTRL_ARREADY;
- output [31:0]S_AXI_CTRL_RDATA;
- output [1:0]S_AXI_CTRL_RRESP;
- output S_AXI_CTRL_RVALID;
- input S_AXI_CTRL_RREADY;
- output UE;
- output CE;
- output Interrupt;
-
- wire \<const0> ;
- wire [0:31]BRAM_Din_A;
- wire [0:3]BRAM_WEN_A;
- wire [0:31]LMB_ABus;
- wire LMB_AddrStrobe;
- wire [0:3]LMB_BE;
- wire LMB_Clk;
- wire LMB_Rst;
- wire [0:31]LMB_WriteDBus;
- wire LMB_WriteStrobe;
- wire \No_ECC.Sl_Rdy_i_1_n_0 ;
- wire \No_ECC.lmb_as_i_1_n_0 ;
- wire Sl_Rdy;
- wire Sl_Ready;
- wire lmb_as;
-
- assign BRAM_Addr_A[0:31] = LMB_ABus;
- assign BRAM_Clk_A = LMB_Clk;
- assign BRAM_Dout_A[0:31] = LMB_WriteDBus;
- assign BRAM_EN_A = LMB_AddrStrobe;
+ assign BRAM_Addr_A[0:31] = LMB_ABus;
+ assign BRAM_Clk_A = LMB_Clk;
+ assign BRAM_Dout_A[0:31] = LMB_WriteDBus;
+ assign BRAM_EN_A = LMB_AddrStrobe;
assign BRAM_Rst_A = \<const0> ;
assign CE = \<const0> ;
assign Interrupt = \<const0> ;
@@ -856,45 +586,50 @@ module mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr
assign Sl_Wait = \<const0> ;
assign UE = \<const0> ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'h40))
+ LUT4 #(
+ .INIT(16'h0200))
\BRAM_WEN_A[0]_INST_0
- (.I0(LMB_ABus[1]),
- .I1(LMB_WriteStrobe),
- .I2(LMB_BE[0]),
+ (.I0(LMB_WriteStrobe),
+ .I1(LMB_ABus[1]),
+ .I2(LMB_ABus[0]),
+ .I3(LMB_BE[0]),
.O(BRAM_WEN_A[0]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'h40))
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT4 #(
+ .INIT(16'h0200))
\BRAM_WEN_A[1]_INST_0
- (.I0(LMB_ABus[1]),
- .I1(LMB_WriteStrobe),
- .I2(LMB_BE[1]),
+ (.I0(LMB_WriteStrobe),
+ .I1(LMB_ABus[1]),
+ .I2(LMB_ABus[0]),
+ .I3(LMB_BE[1]),
.O(BRAM_WEN_A[1]));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT3 #(
- .INIT(8'h40))
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT4 #(
+ .INIT(16'h0200))
\BRAM_WEN_A[2]_INST_0
- (.I0(LMB_ABus[1]),
- .I1(LMB_WriteStrobe),
- .I2(LMB_BE[2]),
+ (.I0(LMB_WriteStrobe),
+ .I1(LMB_ABus[1]),
+ .I2(LMB_ABus[0]),
+ .I3(LMB_BE[2]),
.O(BRAM_WEN_A[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT3 #(
- .INIT(8'h40))
+ LUT4 #(
+ .INIT(16'h0200))
\BRAM_WEN_A[3]_INST_0
- (.I0(LMB_ABus[1]),
- .I1(LMB_WriteStrobe),
- .I2(LMB_BE[3]),
+ (.I0(LMB_WriteStrobe),
+ .I1(LMB_ABus[1]),
+ .I2(LMB_ABus[0]),
+ .I3(LMB_BE[3]),
.O(BRAM_WEN_A[3]));
GND GND
(.G(\<const0> ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT2 #(
- .INIT(4'h1))
+ LUT3 #(
+ .INIT(8'h01))
\No_ECC.Sl_Rdy_i_1
- (.I0(LMB_ABus[1]),
- .I1(LMB_Rst),
+ (.I0(LMB_ABus[0]),
+ .I1(LMB_ABus[1]),
+ .I2(LMB_Rst),
.O(\No_ECC.Sl_Rdy_i_1_n_0 ));
FDRE \No_ECC.Sl_Rdy_reg
(.C(LMB_Clk),
@@ -922,6 +657,276 @@ module mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr
.I1(Sl_Rdy),
.O(Sl_Ready));
endmodule
+
+(* CHECK_LICENSE_TYPE = "mb_design_1_lmb_bram_if_cntlr_0_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2024.1.2" *)
+(* NotValidForBitStream *)
+module mb_design_1_lmb_bram_if_cntlr_0_0
+ (LMB_Clk,
+ LMB_Rst,
+ LMB_ABus,
+ LMB_WriteDBus,
+ LMB_AddrStrobe,
+ LMB_ReadStrobe,
+ LMB_WriteStrobe,
+ LMB_BE,
+ Sl_DBus,
+ Sl_Ready,
+ Sl_Wait,
+ Sl_UE,
+ Sl_CE,
+ BRAM_Rst_A,
+ BRAM_Clk_A,
+ BRAM_Addr_A,
+ BRAM_EN_A,
+ BRAM_WEN_A,
+ BRAM_Dout_A,
+ BRAM_Din_A);
+ (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3:SLMB4:SLMB5:SLMB6:SLMB7, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input LMB_Clk;
+ (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
+ (* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 32768, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
+ (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
+
+ wire \<const0> ;
+ wire [0:31]BRAM_Addr_A;
+ wire BRAM_Clk_A;
+ wire [0:31]BRAM_Din_A;
+ wire [0:31]BRAM_Dout_A;
+ wire BRAM_EN_A;
+ wire [0:3]BRAM_WEN_A;
+ wire [0:31]LMB_ABus;
+ wire LMB_AddrStrobe;
+ wire [0:3]LMB_BE;
+ wire LMB_Clk;
+ wire LMB_Rst;
+ wire [0:31]LMB_WriteDBus;
+ wire LMB_WriteStrobe;
+ wire [0:31]Sl_DBus;
+ wire Sl_Ready;
+ wire NLW_U0_BRAM_Rst_A_UNCONNECTED;
+ wire NLW_U0_CE_UNCONNECTED;
+ wire NLW_U0_Interrupt_UNCONNECTED;
+ wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
+ wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
+ wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
+ wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
+ wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
+ wire NLW_U0_Sl1_CE_UNCONNECTED;
+ wire NLW_U0_Sl1_Ready_UNCONNECTED;
+ wire NLW_U0_Sl1_UE_UNCONNECTED;
+ wire NLW_U0_Sl1_Wait_UNCONNECTED;
+ wire NLW_U0_Sl2_CE_UNCONNECTED;
+ wire NLW_U0_Sl2_Ready_UNCONNECTED;
+ wire NLW_U0_Sl2_UE_UNCONNECTED;
+ wire NLW_U0_Sl2_Wait_UNCONNECTED;
+ wire NLW_U0_Sl3_CE_UNCONNECTED;
+ wire NLW_U0_Sl3_Ready_UNCONNECTED;
+ wire NLW_U0_Sl3_UE_UNCONNECTED;
+ wire NLW_U0_Sl3_Wait_UNCONNECTED;
+ wire NLW_U0_Sl4_CE_UNCONNECTED;
+ wire NLW_U0_Sl4_Ready_UNCONNECTED;
+ wire NLW_U0_Sl4_UE_UNCONNECTED;
+ wire NLW_U0_Sl4_Wait_UNCONNECTED;
+ wire NLW_U0_Sl5_CE_UNCONNECTED;
+ wire NLW_U0_Sl5_Ready_UNCONNECTED;
+ wire NLW_U0_Sl5_UE_UNCONNECTED;
+ wire NLW_U0_Sl5_Wait_UNCONNECTED;
+ wire NLW_U0_Sl6_CE_UNCONNECTED;
+ wire NLW_U0_Sl6_Ready_UNCONNECTED;
+ wire NLW_U0_Sl6_UE_UNCONNECTED;
+ wire NLW_U0_Sl6_Wait_UNCONNECTED;
+ wire NLW_U0_Sl7_CE_UNCONNECTED;
+ wire NLW_U0_Sl7_Ready_UNCONNECTED;
+ wire NLW_U0_Sl7_UE_UNCONNECTED;
+ wire NLW_U0_Sl7_Wait_UNCONNECTED;
+ wire NLW_U0_Sl_CE_UNCONNECTED;
+ wire NLW_U0_Sl_UE_UNCONNECTED;
+ wire NLW_U0_Sl_Wait_UNCONNECTED;
+ wire NLW_U0_UE_UNCONNECTED;
+ wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
+ wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
+ wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl4_DBus_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl5_DBus_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl6_DBus_UNCONNECTED;
+ wire [0:31]NLW_U0_Sl7_DBus_UNCONNECTED;
+
+ assign BRAM_Rst_A = \<const0> ;
+ assign Sl_CE = \<const0> ;
+ assign Sl_UE = \<const0> ;
+ assign Sl_Wait = \<const0> ;
+ GND GND
+ (.G(\<const0> ));
+ (* C_ARBITRATION = "0" *)
+ (* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
+ (* C_BRAM_AWIDTH = "32" *)
+ (* C_CE_COUNTER_WIDTH = "0" *)
+ (* C_CE_FAILING_REGISTERS = "0" *)
+ (* C_ECC = "0" *)
+ (* C_ECC_ONOFF_REGISTER = "0" *)
+ (* C_ECC_ONOFF_RESET_VALUE = "1" *)
+ (* C_ECC_STATUS_REGISTERS = "0" *)
+ (* C_FAMILY = "artix7" *)
+ (* C_FAULT_INJECT = "0" *)
+ (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000000111111111111111" *)
+ (* C_INTERCONNECT = "0" *)
+ (* C_LMB_AWIDTH = "32" *)
+ (* C_LMB_DWIDTH = "32" *)
+ (* C_LMB_PROTOCOL = "0" *)
+ (* C_MASK = "64'b0000000000000000000000000000000011000000000000000000000000000000" *)
+ (* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_MASK4 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_MASK5 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_MASK6 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_MASK7 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
+ (* C_NUM_LMB = "1" *)
+ (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
+ (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
+ (* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
+ (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
+ (* C_UE_FAILING_REGISTERS = "0" *)
+ (* C_WRITE_ACCESS = "2" *)
+ mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr U0
+ (.BRAM_Addr_A(BRAM_Addr_A),
+ .BRAM_Clk_A(BRAM_Clk_A),
+ .BRAM_Din_A(BRAM_Din_A),
+ .BRAM_Dout_A(BRAM_Dout_A),
+ .BRAM_EN_A(BRAM_EN_A),
+ .BRAM_Rst_A(NLW_U0_BRAM_Rst_A_UNCONNECTED),
+ .BRAM_WEN_A(BRAM_WEN_A),
+ .CE(NLW_U0_CE_UNCONNECTED),
+ .Interrupt(NLW_U0_Interrupt_UNCONNECTED),
+ .LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB1_AddrStrobe(1'b0),
+ .LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB1_ReadStrobe(1'b0),
+ .LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB1_WriteStrobe(1'b0),
+ .LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB2_AddrStrobe(1'b0),
+ .LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB2_ReadStrobe(1'b0),
+ .LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB2_WriteStrobe(1'b0),
+ .LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB3_AddrStrobe(1'b0),
+ .LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB3_ReadStrobe(1'b0),
+ .LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB3_WriteStrobe(1'b0),
+ .LMB4_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB4_AddrStrobe(1'b0),
+ .LMB4_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB4_ReadStrobe(1'b0),
+ .LMB4_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB4_WriteStrobe(1'b0),
+ .LMB5_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB5_AddrStrobe(1'b0),
+ .LMB5_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB5_ReadStrobe(1'b0),
+ .LMB5_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB5_WriteStrobe(1'b0),
+ .LMB6_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB6_AddrStrobe(1'b0),
+ .LMB6_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB6_ReadStrobe(1'b0),
+ .LMB6_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB6_WriteStrobe(1'b0),
+ .LMB7_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB7_AddrStrobe(1'b0),
+ .LMB7_BE({1'b0,1'b0,1'b0,1'b0}),
+ .LMB7_ReadStrobe(1'b0),
+ .LMB7_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .LMB7_WriteStrobe(1'b0),
+ .LMB_ABus(LMB_ABus),
+ .LMB_AddrStrobe(LMB_AddrStrobe),
+ .LMB_BE(LMB_BE),
+ .LMB_Clk(LMB_Clk),
+ .LMB_ReadStrobe(1'b0),
+ .LMB_Rst(LMB_Rst),
+ .LMB_WriteDBus(LMB_WriteDBus),
+ .LMB_WriteStrobe(LMB_WriteStrobe),
+ .S_AXI_CTRL_ACLK(1'b0),
+ .S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_CTRL_ARESETN(1'b0),
+ .S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
+ .S_AXI_CTRL_ARVALID(1'b0),
+ .S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
+ .S_AXI_CTRL_AWVALID(1'b0),
+ .S_AXI_CTRL_BREADY(1'b0),
+ .S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
+ .S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
+ .S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
+ .S_AXI_CTRL_RREADY(1'b0),
+ .S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
+ .S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
+ .S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
+ .S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
+ .S_AXI_CTRL_WVALID(1'b0),
+ .Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
+ .Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
+ .Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
+ .Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
+ .Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
+ .Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
+ .Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
+ .Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
+ .Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
+ .Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
+ .Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
+ .Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
+ .Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
+ .Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
+ .Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
+ .Sl4_CE(NLW_U0_Sl4_CE_UNCONNECTED),
+ .Sl4_DBus(NLW_U0_Sl4_DBus_UNCONNECTED[0:31]),
+ .Sl4_Ready(NLW_U0_Sl4_Ready_UNCONNECTED),
+ .Sl4_UE(NLW_U0_Sl4_UE_UNCONNECTED),
+ .Sl4_Wait(NLW_U0_Sl4_Wait_UNCONNECTED),
+ .Sl5_CE(NLW_U0_Sl5_CE_UNCONNECTED),
+ .Sl5_DBus(NLW_U0_Sl5_DBus_UNCONNECTED[0:31]),
+ .Sl5_Ready(NLW_U0_Sl5_Ready_UNCONNECTED),
+ .Sl5_UE(NLW_U0_Sl5_UE_UNCONNECTED),
+ .Sl5_Wait(NLW_U0_Sl5_Wait_UNCONNECTED),
+ .Sl6_CE(NLW_U0_Sl6_CE_UNCONNECTED),
+ .Sl6_DBus(NLW_U0_Sl6_DBus_UNCONNECTED[0:31]),
+ .Sl6_Ready(NLW_U0_Sl6_Ready_UNCONNECTED),
+ .Sl6_UE(NLW_U0_Sl6_UE_UNCONNECTED),
+ .Sl6_Wait(NLW_U0_Sl6_Wait_UNCONNECTED),
+ .Sl7_CE(NLW_U0_Sl7_CE_UNCONNECTED),
+ .Sl7_DBus(NLW_U0_Sl7_DBus_UNCONNECTED[0:31]),
+ .Sl7_Ready(NLW_U0_Sl7_Ready_UNCONNECTED),
+ .Sl7_UE(NLW_U0_Sl7_UE_UNCONNECTED),
+ .Sl7_Wait(NLW_U0_Sl7_Wait_UNCONNECTED),
+ .Sl_CE(NLW_U0_Sl_CE_UNCONNECTED),
+ .Sl_DBus(Sl_DBus),
+ .Sl_Ready(Sl_Ready),
+ .Sl_UE(NLW_U0_Sl_UE_UNCONNECTED),
+ .Sl_Wait(NLW_U0_Sl_Wait_UNCONNECTED),
+ .UE(NLW_U0_UE_UNCONNECTED));
+endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.vhdl
index 51b7299514dac4c0878d9f8347a08848cc6dc408..136d81d535376bd1fb0ff40bd0075989fa016fd3 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.vhdl
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.vhdl
@@ -2,10 +2,10 @@
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--- Date : Tue Mar 4 22:37:17 2025
+-- Date : Thu Mar 20 17:31:20 2025
-- Host : hogtest running 64-bit unknown
--- Command : write_vhdl -force -mode funcsim
--- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.vhdl
+-- Command : write_vhdl -force -mode funcsim -rename_top mb_design_1_lmb_bram_if_cntlr_0_0 -prefix
+-- mb_design_1_lmb_bram_if_cntlr_0_0_ mb_design_1_lmb_bram_if_cntlr_0_0_sim_netlist.vhdl
-- Design : mb_design_1_lmb_bram_if_cntlr_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -170,7 +170,7 @@ entity mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr is
attribute C_LMB_PROTOCOL : integer;
attribute C_LMB_PROTOCOL of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is 0;
attribute C_MASK : string;
- attribute C_MASK of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000001000000000000000000000000000000";
+ attribute C_MASK of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000011000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
@@ -199,8 +199,6 @@ entity mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr is
attribute C_UE_FAILING_REGISTERS of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is 2;
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr";
end mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr;
architecture STRUCTURE of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr is
@@ -216,8 +214,8 @@ architecture STRUCTURE of mb_design_1_lmb_bram_if_cntlr_0_0_lmb_bram_if_cntlr is
signal lmb_as : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \BRAM_WEN_A[0]_INST_0\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \BRAM_WEN_A[1]_INST_0\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of \BRAM_WEN_A[2]_INST_0\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \BRAM_WEN_A[1]_INST_0\ : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \BRAM_WEN_A[2]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \BRAM_WEN_A[3]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \No_ECC.Sl_Rdy_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \No_ECC.lmb_as_i_1\ : label is "soft_lutpair2";
@@ -532,57 +530,62 @@ begin
\^lmb_addrstrobe\ <= LMB_AddrStrobe;
\^lmb_clk\ <= LMB_Clk;
\^lmb_writedbus\(0 to 31) <= LMB_WriteDBus(0 to 31);
-\BRAM_WEN_A[0]_INST_0\: unisim.vcomponents.LUT3
+\BRAM_WEN_A[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"40"
+ INIT => X"0200"
)
port map (
- I0 => \^lmb_abus\(1),
- I1 => LMB_WriteStrobe,
- I2 => LMB_BE(0),
+ I0 => LMB_WriteStrobe,
+ I1 => \^lmb_abus\(1),
+ I2 => \^lmb_abus\(0),
+ I3 => LMB_BE(0),
O => BRAM_WEN_A(0)
);
-\BRAM_WEN_A[1]_INST_0\: unisim.vcomponents.LUT3
+\BRAM_WEN_A[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"40"
+ INIT => X"0200"
)
port map (
- I0 => \^lmb_abus\(1),
- I1 => LMB_WriteStrobe,
- I2 => LMB_BE(1),
+ I0 => LMB_WriteStrobe,
+ I1 => \^lmb_abus\(1),
+ I2 => \^lmb_abus\(0),
+ I3 => LMB_BE(1),
O => BRAM_WEN_A(1)
);
-\BRAM_WEN_A[2]_INST_0\: unisim.vcomponents.LUT3
+\BRAM_WEN_A[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"40"
+ INIT => X"0200"
)
port map (
- I0 => \^lmb_abus\(1),
- I1 => LMB_WriteStrobe,
- I2 => LMB_BE(2),
+ I0 => LMB_WriteStrobe,
+ I1 => \^lmb_abus\(1),
+ I2 => \^lmb_abus\(0),
+ I3 => LMB_BE(2),
O => BRAM_WEN_A(2)
);
-\BRAM_WEN_A[3]_INST_0\: unisim.vcomponents.LUT3
+\BRAM_WEN_A[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"40"
+ INIT => X"0200"
)
port map (
- I0 => \^lmb_abus\(1),
- I1 => LMB_WriteStrobe,
- I2 => LMB_BE(3),
+ I0 => LMB_WriteStrobe,
+ I1 => \^lmb_abus\(1),
+ I2 => \^lmb_abus\(0),
+ I3 => LMB_BE(3),
O => BRAM_WEN_A(3)
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
-\No_ECC.Sl_Rdy_i_1\: unisim.vcomponents.LUT2
+\No_ECC.Sl_Rdy_i_1\: unisim.vcomponents.LUT3
generic map(
- INIT => X"1"
+ INIT => X"01"
)
port map (
- I0 => \^lmb_abus\(1),
- I1 => LMB_Rst,
+ I0 => \^lmb_abus\(0),
+ I1 => \^lmb_abus\(1),
+ I2 => LMB_Rst,
O => \No_ECC.Sl_Rdy_i_1_n_0\
);
\No_ECC.Sl_Rdy_reg\: unisim.vcomponents.FDRE
@@ -742,7 +745,7 @@ architecture STRUCTURE of mb_design_1_lmb_bram_if_cntlr_0_0 is
attribute C_LMB_PROTOCOL : integer;
attribute C_LMB_PROTOCOL of U0 : label is 0;
attribute C_MASK : string;
- attribute C_MASK of U0 : label is "64'b0000000000000000000000000000000001000000000000000000000000000000";
+ attribute C_MASK of U0 : label is "64'b0000000000000000000000000000000011000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.v
index 71df21c4301ee01c23ea4a257b3354e88ae6d4ab..1a3d833ef2c297d99a978019c0b62cd1dcccbd04 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.v
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.v
@@ -2,10 +2,10 @@
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-// Date : Tue Mar 4 22:37:17 2025
+// Date : Thu Mar 20 17:31:20 2025
// Host : hogtest running 64-bit unknown
-// Command : write_verilog -force -mode synth_stub
-// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.v
+// Command : write_verilog -force -mode synth_stub -rename_top mb_design_1_lmb_bram_if_cntlr_0_0 -prefix
+// mb_design_1_lmb_bram_if_cntlr_0_0_ mb_design_1_lmb_bram_if_cntlr_0_0_stub.v
// Design : mb_design_1_lmb_bram_if_cntlr_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.vhdl
index 2c272208567a3dfc0e6971e6e4e62aba6e042e3f..9eef1123376a33d49fc2583a84bf9cb591ae6d6f 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.vhdl
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.vhdl
@@ -2,10 +2,10 @@
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--- Date : Tue Mar 4 22:37:17 2025
+-- Date : Thu Mar 20 17:31:20 2025
-- Host : hogtest running 64-bit unknown
--- Command : write_vhdl -force -mode synth_stub
--- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0_stub.vhdl
+-- Command : write_vhdl -force -mode synth_stub -rename_top mb_design_1_lmb_bram_if_cntlr_0_0 -prefix
+-- mb_design_1_lmb_bram_if_cntlr_0_0_ mb_design_1_lmb_bram_if_cntlr_0_0_stub.vhdl
-- Design : mb_design_1_lmb_bram_if_cntlr_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/sim/mb_design_1_lmb_bram_if_cntlr_0_0.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/sim/mb_design_1_lmb_bram_if_cntlr_0_0.vhd
index 480136095c88d442c63b8e627cf7f0e455b69fa8..bd9c3bbe8120998a27f2601a336ae5917f8c3de0 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/sim/mb_design_1_lmb_bram_if_cntlr_0_0.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/sim/mb_design_1_lmb_bram_if_cntlr_0_0.vhd
@@ -271,7 +271,7 @@ BEGIN
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
- C_MASK => X"0000000040000000",
+ C_MASK => X"00000000c0000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/synth/mb_design_1_lmb_bram_if_cntlr_0_0.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/synth/mb_design_1_lmb_bram_if_cntlr_0_0.vhd
index 9fed3b033b6d7cf39126aae847f224111db72531..055f32e984840f68ee6f7d8221dbdb4f636593f4 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/synth/mb_design_1_lmb_bram_if_cntlr_0_0.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/synth/mb_design_1_lmb_bram_if_cntlr_0_0.vhd
@@ -243,7 +243,7 @@ ARCHITECTURE mb_design_1_lmb_bram_if_cntlr_0_0_arch OF mb_design_1_lmb_bram_if_c
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mb_design_1_lmb_bram_if_cntlr_0_0_arch : ARCHITECTURE IS "mb_design_1_lmb_bram_if_cntlr_0_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
- ATTRIBUTE CORE_GENERATION_INFO OF mb_design_1_lmb_bram_if_cntlr_0_0_arch: ARCHITECTURE IS "mb_design_1_lmb_bram_if_cntlr_0_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=24,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x0000000000007FFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x0000000040000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_MASK4=0x0000000000800000,C_MASK5=0x0000000000800000,C_MASK6=0x0000000000800000,C_M" &
+ ATTRIBUTE CORE_GENERATION_INFO OF mb_design_1_lmb_bram_if_cntlr_0_0_arch: ARCHITECTURE IS "mb_design_1_lmb_bram_if_cntlr_0_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=24,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x0000000000007FFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x00000000c0000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_MASK4=0x0000000000800000,C_MASK5=0x0000000000800000,C_MASK6=0x0000000000800000,C_M" &
"ASK7=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_LMB_PROTOCOL=0,C_ARBITRATION=0,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
@@ -278,7 +278,7 @@ BEGIN
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
- C_MASK => X"0000000040000000",
+ C_MASK => X"00000000c0000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.dcp b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.dcp
index 4178a91a1ece933cd94f40915329a5a51ad9d39d..29f0b36cfad3f1c7433934c1e37c1c58430d8ec8 100644
Binary files a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.dcp and b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.dcp differ
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
index d072aac2f5b75f8c5e588f6303c584d882202347..618e5e26651d8dd76c18b1bea0f6f690ee2dc44e 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
@@ -27310,7 +27310,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:38:42 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:30 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
@@ -27328,11 +27328,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:64c45613</spirit:value>
+ <spirit:value>9:ab1ef4d3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -27348,11 +27348,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:f2e0e0ef</spirit:value>
+ <spirit:value>9:973302a5</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -27376,11 +27376,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:f2e0e0ef</spirit:value>
+ <spirit:value>9:973302a5</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
@@ -27419,7 +27419,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:dbfefa5c</spirit:value>
+ <spirit:value>9:2fc6241c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -27435,11 +27435,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:dbfefa5c</spirit:value>
+ <spirit:value>9:2fc6241c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -27477,7 +27477,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:64c45613</spirit:value>
+ <spirit:value>9:ab1ef4d3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -27493,11 +27493,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
- <spirit:value>Tue Mar 04 21:34:15 UTC 2025</spirit:value>
+ <spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
- <spirit:value>9:64c45613</spirit:value>
+ <spirit:value>9:ab1ef4d3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -27511,7 +27511,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -27524,7 +27524,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -27541,7 +27541,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27568,7 +27568,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27588,7 +27588,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27615,7 +27615,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27642,7 +27642,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27669,7 +27669,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27696,7 +27696,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27723,7 +27723,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27743,7 +27743,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27770,7 +27770,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27797,7 +27797,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27824,7 +27824,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -27841,7 +27841,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27868,7 +27868,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27888,7 +27888,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27908,7 +27908,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27935,7 +27935,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27962,7 +27962,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -27989,7 +27989,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28006,7 +28006,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28030,7 +28030,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28047,7 +28047,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28071,7 +28071,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28095,7 +28095,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28115,7 +28115,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28142,7 +28142,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28162,7 +28162,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28189,7 +28189,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28216,7 +28216,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28243,7 +28243,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28270,7 +28270,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28297,7 +28297,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28317,7 +28317,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28344,7 +28344,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28371,7 +28371,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28398,7 +28398,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28415,7 +28415,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28439,7 +28439,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28456,7 +28456,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28473,7 +28473,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28497,7 +28497,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28521,7 +28521,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28545,7 +28545,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28565,7 +28565,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28589,7 +28589,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28606,7 +28606,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28630,7 +28630,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28654,7 +28654,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28678,7 +28678,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28702,7 +28702,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28726,7 +28726,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28743,7 +28743,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28767,7 +28767,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28791,7 +28791,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28815,7 +28815,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28839,7 +28839,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -28859,7 +28859,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28883,7 +28883,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28900,7 +28900,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28917,7 +28917,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28941,7 +28941,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28965,7 +28965,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -28989,7 +28989,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29009,7 +29009,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29036,7 +29036,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29056,7 +29056,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29083,7 +29083,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29110,7 +29110,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29127,7 +29127,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29151,7 +29151,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29168,7 +29168,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29192,7 +29192,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29216,7 +29216,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29240,7 +29240,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29264,7 +29264,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29288,7 +29288,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29305,7 +29305,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29329,7 +29329,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29353,7 +29353,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29377,7 +29377,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -29401,7 +29401,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29421,7 +29421,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29448,7 +29448,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29468,7 +29468,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29488,7 +29488,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29515,7 +29515,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29542,7 +29542,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -29569,7 +29569,7 @@
<spirit:wireTypeDef>
<spirit:typeName>wire</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
- <spirit:viewNameRef>xilinx_systemcsimulation</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.v
index a4f3b68af288ddf9db112544a5fca5a796b086b2..5637daa684356a674712e3cd2949ee631f676723 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.v
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.v
@@ -2,10 +2,10 @@
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-// Date : Tue Mar 4 22:38:42 2025
+// Date : Thu Mar 20 17:31:25 2025
// Host : hogtest running 64-bit unknown
-// Command : write_verilog -force -mode funcsim
-// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.v
+// Command : write_verilog -force -mode funcsim -rename_top mb_design_1_xbar_0 -prefix
+// mb_design_1_xbar_0_ mb_design_1_xbar_0_sim_netlist.v
// Design : mb_design_1_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -13,437 +13,115 @@
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
-(* CHECK_LICENSE_TYPE = "mb_design_1_xbar_0,axi_crossbar_v2_1_33_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_33_axi_crossbar,Vivado 2024.1.2" *)
-(* NotValidForBitStream *)
-module mb_design_1_xbar_0
- (aclk,
- aresetn,
- s_axi_awaddr,
- s_axi_awprot,
- s_axi_awvalid,
- s_axi_awready,
- s_axi_wdata,
- s_axi_wstrb,
- s_axi_wvalid,
- s_axi_wready,
- s_axi_bresp,
- s_axi_bvalid,
- s_axi_bready,
- s_axi_araddr,
- s_axi_arprot,
- s_axi_arvalid,
- s_axi_arready,
- s_axi_rdata,
- s_axi_rresp,
- s_axi_rvalid,
- s_axi_rready,
- m_axi_awaddr,
- m_axi_awprot,
- m_axi_awvalid,
- m_axi_awready,
- m_axi_wdata,
- m_axi_wstrb,
- m_axi_wvalid,
- m_axi_wready,
- m_axi_bresp,
- m_axi_bvalid,
- m_axi_bready,
- m_axi_araddr,
- m_axi_arprot,
- m_axi_arvalid,
- m_axi_arready,
- m_axi_rdata,
- m_axi_rresp,
- m_axi_rvalid,
- m_axi_rready);
- (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input aclk;
- (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *) output [127:0]m_axi_awaddr;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *) output [11:0]m_axi_awprot;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *) output [3:0]m_axi_awvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *) input [3:0]m_axi_awready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *) output [127:0]m_axi_wdata;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *) output [15:0]m_axi_wstrb;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *) output [3:0]m_axi_wvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *) input [3:0]m_axi_wready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *) input [7:0]m_axi_bresp;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *) input [3:0]m_axi_bvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *) output [3:0]m_axi_bready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *) output [127:0]m_axi_araddr;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *) output [11:0]m_axi_arprot;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *) output [3:0]m_axi_arvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *) input [3:0]m_axi_arready;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *) input [127:0]m_axi_rdata;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *) input [7:0]m_axi_rresp;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *) input [3:0]m_axi_rvalid;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [3:0]m_axi_rready;
-
- wire \<const0> ;
- wire aclk;
- wire aresetn;
- wire [127:0]m_axi_araddr;
- wire [11:0]m_axi_arprot;
- wire [3:0]m_axi_arready;
- wire [2:0]\^m_axi_arvalid ;
- wire [127:0]m_axi_awaddr;
- wire [11:0]m_axi_awprot;
- wire [3:0]m_axi_awready;
- wire [2:0]\^m_axi_awvalid ;
- wire [2:0]\^m_axi_bready ;
- wire [7:0]m_axi_bresp;
- wire [3:0]m_axi_bvalid;
- wire [127:0]m_axi_rdata;
- wire [2:0]\^m_axi_rready ;
- wire [7:0]m_axi_rresp;
- wire [3:0]m_axi_rvalid;
- wire [127:0]m_axi_wdata;
- wire [3:0]m_axi_wready;
- wire [15:0]m_axi_wstrb;
- wire [2:0]\^m_axi_wvalid ;
- wire [31:0]s_axi_araddr;
- wire [2:0]s_axi_arprot;
- wire [0:0]s_axi_arready;
- wire [0:0]s_axi_arvalid;
- wire [31:0]s_axi_awaddr;
- wire [2:0]s_axi_awprot;
- wire [0:0]s_axi_awready;
- wire [0:0]s_axi_awvalid;
- wire [0:0]s_axi_bready;
- wire [1:0]s_axi_bresp;
- wire [0:0]s_axi_bvalid;
- wire [31:0]s_axi_rdata;
- wire [0:0]s_axi_rready;
- wire [1:0]s_axi_rresp;
- wire [0:0]s_axi_rvalid;
- wire [31:0]s_axi_wdata;
- wire [0:0]s_axi_wready;
- wire [3:0]s_axi_wstrb;
- wire [0:0]s_axi_wvalid;
- wire [7:0]NLW_inst_m_axi_arburst_UNCONNECTED;
- wire [15:0]NLW_inst_m_axi_arcache_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_arid_UNCONNECTED;
- wire [31:0]NLW_inst_m_axi_arlen_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_arlock_UNCONNECTED;
- wire [15:0]NLW_inst_m_axi_arqos_UNCONNECTED;
- wire [15:0]NLW_inst_m_axi_arregion_UNCONNECTED;
- wire [11:0]NLW_inst_m_axi_arsize_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_aruser_UNCONNECTED;
- wire [3:3]NLW_inst_m_axi_arvalid_UNCONNECTED;
- wire [7:0]NLW_inst_m_axi_awburst_UNCONNECTED;
- wire [15:0]NLW_inst_m_axi_awcache_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_awid_UNCONNECTED;
- wire [31:0]NLW_inst_m_axi_awlen_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_awlock_UNCONNECTED;
- wire [15:0]NLW_inst_m_axi_awqos_UNCONNECTED;
- wire [15:0]NLW_inst_m_axi_awregion_UNCONNECTED;
- wire [11:0]NLW_inst_m_axi_awsize_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_awuser_UNCONNECTED;
- wire [3:3]NLW_inst_m_axi_awvalid_UNCONNECTED;
- wire [3:3]NLW_inst_m_axi_bready_UNCONNECTED;
- wire [3:3]NLW_inst_m_axi_rready_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_wid_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_wlast_UNCONNECTED;
- wire [3:0]NLW_inst_m_axi_wuser_UNCONNECTED;
- wire [3:3]NLW_inst_m_axi_wvalid_UNCONNECTED;
- wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
- wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
- wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
- wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
- wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
-
- assign m_axi_arvalid[3] = \<const0> ;
- assign m_axi_arvalid[2:0] = \^m_axi_arvalid [2:0];
- assign m_axi_awvalid[3] = \<const0> ;
- assign m_axi_awvalid[2:0] = \^m_axi_awvalid [2:0];
- assign m_axi_bready[3] = \<const0> ;
- assign m_axi_bready[2:0] = \^m_axi_bready [2:0];
- assign m_axi_rready[3] = \<const0> ;
- assign m_axi_rready[2:0] = \^m_axi_rready [2:0];
- assign m_axi_wvalid[3] = \<const0> ;
- assign m_axi_wvalid[2:0] = \^m_axi_wvalid [2:0];
- GND GND
- (.G(\<const0> ));
- (* C_AXI_ADDR_WIDTH = "32" *)
- (* C_AXI_ARUSER_WIDTH = "1" *)
- (* C_AXI_AWUSER_WIDTH = "1" *)
- (* C_AXI_BUSER_WIDTH = "1" *)
- (* C_AXI_DATA_WIDTH = "32" *)
- (* C_AXI_ID_WIDTH = "1" *)
- (* C_AXI_PROTOCOL = "2" *)
- (* C_AXI_RUSER_WIDTH = "1" *)
- (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
- (* C_AXI_WUSER_WIDTH = "1" *)
- (* C_CONNECTIVITY_MODE = "0" *)
- (* C_DEBUG = "1" *)
- (* C_FAMILY = "artix7" *)
- (* C_M_AXI_ADDR_WIDTH = "128'b00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100" *)
- (* C_M_AXI_BASE_ADDR = "256'b1111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000" *)
- (* C_M_AXI_READ_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
- (* C_M_AXI_READ_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
- (* C_M_AXI_SECURE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_M_AXI_WRITE_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
- (* C_M_AXI_WRITE_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
- (* C_NUM_ADDR_RANGES = "1" *)
- (* C_NUM_MASTER_SLOTS = "4" *)
- (* C_NUM_SLAVE_SLOTS = "1" *)
- (* C_R_REGISTER = "1" *)
- (* C_S_AXI_ARB_PRIORITY = "0" *)
- (* C_S_AXI_BASE_ID = "0" *)
- (* C_S_AXI_READ_ACCEPTANCE = "1" *)
- (* C_S_AXI_SINGLE_THREAD = "1" *)
- (* C_S_AXI_THREAD_ID_WIDTH = "0" *)
- (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
- (* DowngradeIPIdentifiedWarnings = "yes" *)
- (* P_ADDR_DECODE = "1" *)
- (* P_AXI3 = "1" *)
- (* P_AXI4 = "0" *)
- (* P_AXILITE = "2" *)
- (* P_AXILITE_SIZE = "3'b010" *)
- (* P_FAMILY = "artix7" *)
- (* P_INCR = "2'b01" *)
- (* P_LEN = "8" *)
- (* P_LOCK = "1" *)
- (* P_M_AXI_ERR_MODE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* P_M_AXI_SUPPORTS_READ = "4'b1111" *)
- (* P_M_AXI_SUPPORTS_WRITE = "4'b1111" *)
- (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
- (* P_RANGE_CHECK = "1" *)
- (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
- (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
- (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
- (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
- mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar inst
- (.aclk(aclk),
- .aresetn(aresetn),
- .m_axi_araddr(m_axi_araddr),
- .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[7:0]),
- .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[15:0]),
- .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[3:0]),
- .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[31:0]),
- .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[3:0]),
- .m_axi_arprot(m_axi_arprot),
- .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[15:0]),
- .m_axi_arready(m_axi_arready),
- .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[15:0]),
- .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[11:0]),
- .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[3:0]),
- .m_axi_arvalid({NLW_inst_m_axi_arvalid_UNCONNECTED[3],\^m_axi_arvalid }),
- .m_axi_awaddr(m_axi_awaddr),
- .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[7:0]),
- .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[15:0]),
- .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[3:0]),
- .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[31:0]),
- .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[3:0]),
- .m_axi_awprot(m_axi_awprot),
- .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[15:0]),
- .m_axi_awready(m_axi_awready),
- .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[15:0]),
- .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[11:0]),
- .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[3:0]),
- .m_axi_awvalid({NLW_inst_m_axi_awvalid_UNCONNECTED[3],\^m_axi_awvalid }),
- .m_axi_bid({1'b0,1'b0,1'b0,1'b0}),
- .m_axi_bready({NLW_inst_m_axi_bready_UNCONNECTED[3],\^m_axi_bready }),
- .m_axi_bresp(m_axi_bresp),
- .m_axi_buser({1'b0,1'b0,1'b0,1'b0}),
- .m_axi_bvalid(m_axi_bvalid),
- .m_axi_rdata(m_axi_rdata),
- .m_axi_rid({1'b0,1'b0,1'b0,1'b0}),
- .m_axi_rlast({1'b1,1'b1,1'b1,1'b1}),
- .m_axi_rready({NLW_inst_m_axi_rready_UNCONNECTED[3],\^m_axi_rready }),
- .m_axi_rresp(m_axi_rresp),
- .m_axi_ruser({1'b0,1'b0,1'b0,1'b0}),
- .m_axi_rvalid(m_axi_rvalid),
- .m_axi_wdata(m_axi_wdata),
- .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[3:0]),
- .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[3:0]),
- .m_axi_wready(m_axi_wready),
- .m_axi_wstrb(m_axi_wstrb),
- .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[3:0]),
- .m_axi_wvalid({NLW_inst_m_axi_wvalid_UNCONNECTED[3],\^m_axi_wvalid }),
- .s_axi_araddr(s_axi_araddr),
- .s_axi_arburst({1'b0,1'b0}),
- .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
- .s_axi_arid(1'b0),
- .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .s_axi_arlock(1'b0),
- .s_axi_arprot(s_axi_arprot),
- .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
- .s_axi_arready(s_axi_arready),
- .s_axi_arsize({1'b0,1'b0,1'b0}),
- .s_axi_aruser(1'b0),
- .s_axi_arvalid(s_axi_arvalid),
- .s_axi_awaddr(s_axi_awaddr),
- .s_axi_awburst({1'b0,1'b0}),
- .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
- .s_axi_awid(1'b0),
- .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .s_axi_awlock(1'b0),
- .s_axi_awprot(s_axi_awprot),
- .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
- .s_axi_awready(s_axi_awready),
- .s_axi_awsize({1'b0,1'b0,1'b0}),
- .s_axi_awuser(1'b0),
- .s_axi_awvalid(s_axi_awvalid),
- .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
- .s_axi_bready(s_axi_bready),
- .s_axi_bresp(s_axi_bresp),
- .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
- .s_axi_bvalid(s_axi_bvalid),
- .s_axi_rdata(s_axi_rdata),
- .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
- .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
- .s_axi_rready(s_axi_rready),
- .s_axi_rresp(s_axi_rresp),
- .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
- .s_axi_rvalid(s_axi_rvalid),
- .s_axi_wdata(s_axi_wdata),
- .s_axi_wid(1'b0),
- .s_axi_wlast(1'b1),
- .s_axi_wready(s_axi_wready),
- .s_axi_wstrb(s_axi_wstrb),
- .s_axi_wuser(1'b0),
- .s_axi_wvalid(s_axi_wvalid));
-endmodule
-
-(* ORIG_REF_NAME = "axi_crossbar_v2_1_33_addr_arbiter_sasd" *)
module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
- (p_0_in1_in,
- m_valid_i,
+ (m_valid_i,
SR,
aa_grant_rnw,
- aresetn_d_reg,
- D,
- aresetn_d_reg_0,
- aresetn_d_reg_1,
- \gen_no_arbiter.m_amesg_i_reg[19]_0 ,
- Q,
- m_ready_d0,
- s_axi_wready,
- m_axi_wvalid,
- s_axi_wvalid_0_sp_1,
- m_axi_awvalid,
s_axi_bvalid,
+ s_axi_wready,
m_axi_bready,
- s_axi_bready_0_sp_1,
+ m_axi_awvalid,
\gen_no_arbiter.grant_rnw_reg_0 ,
+ m_axi_wvalid,
+ \gen_no_arbiter.m_valid_i_reg_0 ,
\aresetn_d_reg[0] ,
- \aresetn_d_reg[1] ,
E,
+ \aresetn_d_reg[1] ,
+ m_ready_d0,
m_axi_arvalid,
- m_ready_d0_0,
- \m_ready_d_reg[1] ,
- \gen_no_arbiter.grant_rnw_reg_1 ,
+ mi_arvalid_en,
s_axi_awready,
s_axi_arready,
- \gen_axilite.s_axi_awready_i_reg ,
- \m_ready_d_reg[2] ,
+ s_axi_rvalid,
+ D,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ,
+ \gen_no_arbiter.m_amesg_i_reg[48]_0 ,
+ \m_atarget_hot_reg[5] ,
+ \gen_axilite.s_axi_bvalid_i_reg ,
aclk,
- aresetn_d,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ,
+ m_ready_d0_0,
s_axi_awvalid,
s_axi_arvalid,
- \gen_no_arbiter.m_valid_i_reg_0 ,
+ aresetn_d,
m_ready_d,
- s_axi_wready_0_sp_1,
- \gen_axilite.s_axi_bvalid_i_reg ,
- s_axi_wvalid,
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0 ,
- s_axi_bvalid_0_sp_1,
+ f_mux_return__3,
+ f_mux_return__1,
+ Q,
s_axi_bready,
- \m_ready_d[2]_i_3 ,
- \m_ready_d[2]_i_3_0 ,
+ \gen_no_arbiter.m_valid_i_reg_1 ,
+ \gen_no_arbiter.m_valid_i_reg_2 ,
+ \gen_no_arbiter.m_valid_i_reg_3 ,
+ s_axi_wvalid,
m_valid_i_reg,
- aa_rready,
- m_ready_d_1,
m_valid_i_reg_0,
m_valid_i_reg_1,
+ m_valid_i_reg_2,
+ aa_rready,
+ m_ready_d_1,
s_axi_rready,
sr_rvalid,
+ \m_ready_d_reg[1] ,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[1]_1 ,
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1 ,
- m_axi_wready,
- m_atarget_enc,
+ \m_ready_d_reg[1]_2 ,
s_axi_arprot,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
mi_wready,
mi_bvalid);
- output p_0_in1_in;
output m_valid_i;
output [0:0]SR;
output aa_grant_rnw;
- output aresetn_d_reg;
- output [3:0]D;
- output aresetn_d_reg_0;
- output aresetn_d_reg_1;
- output [0:0]\gen_no_arbiter.m_amesg_i_reg[19]_0 ;
- output [34:0]Q;
- output [0:0]m_ready_d0;
- output [0:0]s_axi_wready;
- output [2:0]m_axi_wvalid;
- output s_axi_wvalid_0_sp_1;
- output [2:0]m_axi_awvalid;
output [0:0]s_axi_bvalid;
- output [2:0]m_axi_bready;
- output s_axi_bready_0_sp_1;
- output \gen_no_arbiter.grant_rnw_reg_0 ;
+ output [0:0]s_axi_wready;
+ output [4:0]m_axi_bready;
+ output [4:0]m_axi_awvalid;
+ output [0:0]\gen_no_arbiter.grant_rnw_reg_0 ;
+ output [4:0]m_axi_wvalid;
+ output \gen_no_arbiter.m_valid_i_reg_0 ;
output \aresetn_d_reg[0] ;
- output \aresetn_d_reg[1] ;
output [0:0]E;
- output [2:0]m_axi_arvalid;
- output [0:0]m_ready_d0_0;
- output \m_ready_d_reg[1] ;
- output \gen_no_arbiter.grant_rnw_reg_1 ;
+ output \aresetn_d_reg[1] ;
+ output [1:0]m_ready_d0;
+ output [4:0]m_axi_arvalid;
+ output mi_arvalid_en;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
- output \gen_axilite.s_axi_awready_i_reg ;
- output \m_ready_d_reg[2] ;
+ output [0:0]s_axi_rvalid;
+ output [2:0]D;
+ output [5:0]\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
+ output [34:0]\gen_no_arbiter.m_amesg_i_reg[48]_0 ;
+ output \m_atarget_hot_reg[5] ;
+ output \gen_axilite.s_axi_bvalid_i_reg ;
input aclk;
- input aresetn_d;
+ input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ;
+ input [1:0]m_ready_d0_0;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_arvalid;
- input \gen_no_arbiter.m_valid_i_reg_0 ;
+ input aresetn_d;
input [2:0]m_ready_d;
- input s_axi_wready_0_sp_1;
- input [3:0]\gen_axilite.s_axi_bvalid_i_reg ;
- input [0:0]s_axi_wvalid;
- input \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0 ;
- input s_axi_bvalid_0_sp_1;
+ input f_mux_return__3;
+ input f_mux_return__1;
+ input [5:0]Q;
input [0:0]s_axi_bready;
- input \m_ready_d[2]_i_3 ;
- input \m_ready_d[2]_i_3_0 ;
+ input \gen_no_arbiter.m_valid_i_reg_1 ;
+ input \gen_no_arbiter.m_valid_i_reg_2 ;
+ input \gen_no_arbiter.m_valid_i_reg_3 ;
+ input [0:0]s_axi_wvalid;
input [1:0]m_valid_i_reg;
- input aa_rready;
- input [1:0]m_ready_d_1;
input m_valid_i_reg_0;
input m_valid_i_reg_1;
+ input m_valid_i_reg_2;
+ input aa_rready;
+ input [1:0]m_ready_d_1;
input [0:0]s_axi_rready;
input sr_rvalid;
+ input [0:0]\m_ready_d_reg[1] ;
input \m_ready_d_reg[1]_0 ;
input \m_ready_d_reg[1]_1 ;
- input \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1 ;
- input [1:0]m_axi_wready;
- input [2:0]m_atarget_enc;
+ input \m_ready_d_reg[1]_2 ;
input [2:0]s_axi_arprot;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
@@ -451,68 +129,78 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
input [0:0]mi_wready;
input [0:0]mi_bvalid;
- wire [3:0]D;
+ wire [2:0]D;
wire [0:0]E;
- wire [34:0]Q;
+ wire [5:0]Q;
wire [0:0]SR;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire aresetn_d;
- wire aresetn_d_reg;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1] ;
- wire aresetn_d_reg_0;
- wire aresetn_d_reg_1;
- wire \gen_axilite.s_axi_awready_i_reg ;
- wire \gen_axilite.s_axi_bvalid_i_i_2_n_0 ;
- wire [3:0]\gen_axilite.s_axi_bvalid_i_reg ;
+ wire f_mux_return__1;
+ wire f_mux_return__3;
+ wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ;
+ wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ;
+ wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ;
+ wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ;
+ wire \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ;
+ wire \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ;
+ wire \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ;
+ wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
- wire \gen_no_arbiter.grant_rnw_reg_0 ;
- wire \gen_no_arbiter.grant_rnw_reg_1 ;
- wire [0:0]\gen_no_arbiter.m_amesg_i_reg[19]_0 ;
+ wire [0:0]\gen_no_arbiter.grant_rnw_reg_0 ;
+ wire [34:0]\gen_no_arbiter.m_amesg_i_reg[48]_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ;
- wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0 ;
- wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ;
- wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ;
+ wire [5:0]\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
+ wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_reg_0 ;
+ wire \gen_no_arbiter.m_valid_i_reg_1 ;
+ wire \gen_no_arbiter.m_valid_i_reg_2 ;
+ wire \gen_no_arbiter.m_valid_i_reg_3 ;
wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
- wire [2:0]m_atarget_enc;
- wire \m_atarget_hot[4]_i_10_n_0 ;
- wire \m_atarget_hot[4]_i_2_n_0 ;
- wire \m_atarget_hot[4]_i_5_n_0 ;
- wire \m_atarget_hot[4]_i_6_n_0 ;
- wire \m_atarget_hot[4]_i_7_n_0 ;
- wire \m_atarget_hot[4]_i_8_n_0 ;
- wire \m_atarget_hot[4]_i_9_n_0 ;
- wire [2:0]m_axi_arvalid;
- wire [2:0]m_axi_awvalid;
- wire [2:0]m_axi_bready;
- wire [1:0]m_axi_wready;
- wire [2:0]m_axi_wvalid;
+ wire \m_atarget_hot[2]_i_3_n_0 ;
+ wire \m_atarget_hot[3]_i_3_n_0 ;
+ wire \m_atarget_hot[5]_i_12_n_0 ;
+ wire \m_atarget_hot[5]_i_13_n_0 ;
+ wire \m_atarget_hot[5]_i_14_n_0 ;
+ wire \m_atarget_hot[5]_i_15_n_0 ;
+ wire \m_atarget_hot[5]_i_16_n_0 ;
+ wire \m_atarget_hot[5]_i_2_n_0 ;
+ wire \m_atarget_hot[5]_i_6_n_0 ;
+ wire \m_atarget_hot[5]_i_8_n_0 ;
+ wire \m_atarget_hot[5]_i_9_n_0 ;
+ wire \m_atarget_hot_reg[5] ;
+ wire [4:0]m_axi_arvalid;
+ wire [4:0]m_axi_awvalid;
+ wire [4:0]m_axi_bready;
+ wire [4:0]m_axi_wvalid;
wire [2:0]m_ready_d;
- wire [0:0]m_ready_d0;
- wire [0:0]m_ready_d0_0;
- wire \m_ready_d[0]_i_4_n_0 ;
- wire \m_ready_d[2]_i_3 ;
- wire \m_ready_d[2]_i_3_0 ;
+ wire [1:0]m_ready_d0;
+ wire [1:0]m_ready_d0_0;
wire [1:0]m_ready_d_1;
- wire \m_ready_d_reg[1] ;
+ wire [0:0]\m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
- wire \m_ready_d_reg[2] ;
+ wire \m_ready_d_reg[1]_2 ;
wire m_valid_i;
wire m_valid_i_i_2_n_0;
- wire m_valid_i_i_3_n_0;
wire [1:0]m_valid_i_reg;
wire m_valid_i_reg_0;
wire m_valid_i_reg_1;
+ wire m_valid_i_reg_2;
+ wire mi_arvalid_en;
+ wire mi_awvalid_en;
wire [0:0]mi_bvalid;
wire [0:0]mi_wready;
wire p_0_in1_in;
+ wire p_3_in;
+ wire p_4_in;
+ wire r_transfer_en;
wire [48:1]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
@@ -527,73 +215,76 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
- wire s_axi_bready_0_sn_1;
wire [0:0]s_axi_bvalid;
- wire s_axi_bvalid_0_sn_1;
wire [0:0]s_axi_rready;
+ wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
- wire s_axi_wready_0_sn_1;
wire [0:0]s_axi_wvalid;
- wire s_axi_wvalid_0_sn_1;
wire s_ready_i;
wire sr_rvalid;
- wire [1:0]target_mi_enc;
+ wire [2:2]target_mi_enc;
- assign s_axi_bready_0_sp_1 = s_axi_bready_0_sn_1;
- assign s_axi_bvalid_0_sn_1 = s_axi_bvalid_0_sp_1;
- assign s_axi_wready_0_sn_1 = s_axi_wready_0_sp_1;
- assign s_axi_wvalid_0_sp_1 = s_axi_wvalid_0_sn_1;
- LUT6 #(
- .INIT(64'hFFEFFFFF00100000))
+ LUT5 #(
+ .INIT(32'hDFFF2000))
\gen_axilite.s_axi_awready_i_i_1
- (.I0(\gen_no_arbiter.grant_rnw_reg_0 ),
- .I1(m_ready_d[2]),
- .I2(\gen_axilite.s_axi_bvalid_i_reg [3]),
- .I3(mi_bvalid),
- .I4(s_axi_wvalid_0_sn_1),
- .I5(mi_wready),
- .O(\m_ready_d_reg[2] ));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT2 #(
- .INIT(4'hB))
- \gen_axilite.s_axi_awready_i_i_2
- (.I0(aa_grant_rnw),
- .I1(m_valid_i),
- .O(\gen_no_arbiter.grant_rnw_reg_0 ));
+ (.I0(p_4_in),
+ .I1(mi_bvalid),
+ .I2(Q[5]),
+ .I3(mi_awvalid_en),
+ .I4(mi_wready),
+ .O(\gen_axilite.s_axi_bvalid_i_reg ));
LUT6 #(
- .INIT(64'h0008FF00FF08FF00))
+ .INIT(64'h5F5FC0005F5F0000))
\gen_axilite.s_axi_bvalid_i_i_1
- (.I0(mi_wready),
- .I1(s_axi_wvalid_0_sn_1),
- .I2(\gen_axilite.s_axi_bvalid_i_i_2_n_0 ),
- .I3(mi_bvalid),
- .I4(\gen_axilite.s_axi_bvalid_i_reg [3]),
- .I5(s_axi_bready_0_sn_1),
- .O(\gen_axilite.s_axi_awready_i_reg ));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT3 #(
- .INIT(8'hFB))
+ (.I0(p_3_in),
+ .I1(p_4_in),
+ .I2(Q[5]),
+ .I3(mi_wready),
+ .I4(mi_bvalid),
+ .I5(mi_awvalid_en),
+ .O(\m_atarget_hot_reg[5] ));
+ (* SOFT_HLUTNM = "soft_lutpair5" *)
+ LUT4 #(
+ .INIT(16'h0400))
\gen_axilite.s_axi_bvalid_i_i_2
- (.I0(m_ready_d[2]),
- .I1(m_valid_i),
+ (.I0(m_ready_d[0]),
+ .I1(s_axi_bready),
.I2(aa_grant_rnw),
- .O(\gen_axilite.s_axi_bvalid_i_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
+ .I3(m_valid_i),
+ .O(p_3_in));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT4 #(
+ .INIT(16'h0400))
+ \gen_axilite.s_axi_bvalid_i_i_3
+ (.I0(m_ready_d[1]),
+ .I1(s_axi_wvalid),
+ .I2(aa_grant_rnw),
+ .I3(m_valid_i),
+ .O(p_4_in));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
- .INIT(8'h40))
+ .INIT(8'h04))
+ \gen_axilite.s_axi_bvalid_i_i_4
+ (.I0(aa_grant_rnw),
+ .I1(m_valid_i),
+ .I2(m_ready_d[2]),
+ .O(mi_awvalid_en));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
+ LUT3 #(
+ .INIT(8'h08))
\gen_axilite.s_axi_rvalid_i_i_2
- (.I0(m_ready_d_1[1]),
+ (.I0(aa_grant_rnw),
.I1(m_valid_i),
- .I2(aa_grant_rnw),
- .O(\m_ready_d_reg[1] ));
+ .I2(m_ready_d_1[1]),
+ .O(mi_arvalid_en));
LUT6 #(
- .INIT(64'hFFFF53FF00005000))
+ .INIT(64'hDFCFDFFF10001000))
\gen_no_arbiter.grant_rnw_i_1
(.I0(s_awvalid_reg),
- .I1(s_axi_awvalid),
- .I2(s_axi_arvalid),
- .I3(p_0_in1_in),
- .I4(m_valid_i),
+ .I1(m_valid_i),
+ .I2(p_0_in1_in),
+ .I3(s_axi_arvalid),
+ .I4(s_axi_awvalid),
.I5(aa_grant_rnw),
.O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
FDRE \gen_no_arbiter.grant_rnw_reg
@@ -891,250 +582,241 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[10]),
- .Q(Q[9]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [9]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[11]),
- .Q(Q[10]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [10]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[12]),
- .Q(Q[11]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [11]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[13]),
- .Q(Q[12]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [12]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[14]),
- .Q(Q[13]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [13]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[15]),
- .Q(Q[14]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [14]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[16]),
- .Q(Q[15]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [15]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[17]),
- .Q(Q[16]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [16]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[18]),
- .Q(Q[17]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [17]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[19]),
- .Q(Q[18]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [18]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[1]),
- .Q(Q[0]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [0]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[20]),
- .Q(Q[19]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [19]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[21]),
- .Q(Q[20]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [20]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[22]),
- .Q(Q[21]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[23]),
- .Q(Q[22]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[24]),
- .Q(Q[23]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[25]),
- .Q(Q[24]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[26]),
- .Q(Q[25]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [25]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[27]),
- .Q(Q[26]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [26]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[28]),
- .Q(Q[27]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [27]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[29]),
- .Q(Q[28]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [28]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[2]),
- .Q(Q[1]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [1]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[30]),
- .Q(Q[29]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [29]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[31]),
- .Q(Q[30]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [30]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[32]),
- .Q(Q[31]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [31]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[3]),
- .Q(Q[2]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [2]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[46]),
- .Q(Q[32]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [32]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[47]),
- .Q(Q[33]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [33]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[48]),
- .Q(Q[34]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [34]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[4]),
- .Q(Q[3]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [3]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[5]),
- .Q(Q[4]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [4]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[6]),
- .Q(Q[5]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [5]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[7]),
- .Q(Q[6]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [6]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[8]),
- .Q(Q[7]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [7]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[9]),
- .Q(Q[8]),
+ .Q(\gen_no_arbiter.m_amesg_i_reg[48]_0 [8]),
.R(SR));
LUT6 #(
- .INIT(64'hFF555755FFFFFFFF))
+ .INIT(64'hDDD5D5D5D5D5D5D5))
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1
(.I0(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ),
- .I1(s_axi_awvalid),
- .I2(s_axi_arvalid),
- .I3(p_0_in1_in),
- .I4(m_valid_i),
- .I5(aresetn_d),
+ .I1(m_valid_i),
+ .I2(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ),
+ .I3(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ),
+ .I4(m_ready_d0_0[0]),
+ .I5(m_ready_d0_0[1]),
.O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00EFFFFFFFEFFFFF))
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
+ LUT5 #(
+ .INIT(32'h0FEF0000))
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2
- (.I0(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ),
- .I1(\gen_no_arbiter.m_valid_i_reg_0 ),
- .I2(m_ready_d0),
- .I3(aa_grant_rnw),
- .I4(m_valid_i),
- .I5(\m_ready_d[0]_i_4_n_0 ),
+ (.I0(s_axi_awvalid),
+ .I1(s_axi_arvalid),
+ .I2(p_0_in1_in),
+ .I3(m_valid_i),
+ .I4(aresetn_d),
.O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ));
LUT6 #(
- .INIT(64'h00000000FF2FFFFF))
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3
- (.I0(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ),
- .I1(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0 ),
- .I2(s_axi_wvalid),
- .I3(aa_grant_rnw),
- .I4(m_valid_i),
- .I5(m_ready_d[1]),
- .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0 ));
- LUT5 #(
- .INIT(32'hF3F7FFF7))
+ .INIT(64'h00000000FFFEAAAA))
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4
- (.I0(m_axi_wready[0]),
- .I1(m_atarget_enc[1]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[0]),
- .I4(m_axi_wready[1]),
+ (.I0(m_ready_d[2]),
+ .I1(\gen_no_arbiter.m_valid_i_reg_1 ),
+ .I2(\gen_no_arbiter.m_valid_i_reg_2 ),
+ .I3(\gen_no_arbiter.m_valid_i_reg_3 ),
+ .I4(m_valid_i),
+ .I5(aa_grant_rnw),
.O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ));
(* inverted = "yes" *)
FDRE #(
@@ -1145,13 +827,15 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
.D(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0 ),
.Q(p_0_in1_in),
.R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT3 #(
- .INIT(8'hB1))
+ LUT6 #(
+ .INIT(64'h111D1D1D1D1D1D1D))
\gen_no_arbiter.m_valid_i_i_1
- (.I0(m_valid_i),
- .I1(p_0_in1_in),
- .I2(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0 ),
+ (.I0(p_0_in1_in),
+ .I1(m_valid_i),
+ .I2(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ),
+ .I3(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0 ),
+ .I4(m_ready_d0_0[0]),
+ .I5(m_ready_d0_0[1]),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
@@ -1161,7 +845,7 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(SR));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ (* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h10))
\gen_no_arbiter.s_ready_i[0]_i_1
@@ -1177,352 +861,501 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
.D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i),
.R(1'b0));
- LUT2 #(
- .INIT(4'h8))
+ LUT6 #(
+ .INIT(64'hAAAAAAAAAA00AA02))
\m_atarget_enc[0]_i_1
- (.I0(target_mi_enc[0]),
- .I1(aresetn_d),
- .O(aresetn_d_reg_0));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ (.I0(aresetn_d),
+ .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
+ .I2(target_mi_enc),
+ .I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
+ .I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ),
+ .I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
+ .O(D[0]));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_enc[1]_i_1
- (.I0(target_mi_enc[1]),
- .I1(aresetn_d),
- .O(aresetn_d_reg_1));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'h02))
+ (.I0(aresetn_d),
+ .I1(\m_atarget_hot[5]_i_2_n_0 ),
+ .O(D[1]));
+ (* SOFT_HLUTNM = "soft_lutpair1" *)
+ LUT5 #(
+ .INIT(32'hCCCD0000))
\m_atarget_enc[2]_i_1
- (.I0(\m_atarget_hot[4]_i_2_n_0 ),
- .I1(target_mi_enc[1]),
- .I2(target_mi_enc[0]),
- .O(\gen_no_arbiter.m_amesg_i_reg[19]_0 ));
+ (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
+ .I1(target_mi_enc),
+ .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
+ .I3(\m_atarget_hot[5]_i_2_n_0 ),
+ .I4(aresetn_d),
+ .O(D[2]));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
- .INIT(4'h1))
+ .INIT(4'h2))
\m_atarget_hot[0]_i_1
+ (.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
+ .I1(p_0_in1_in),
+ .O(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 [0]));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h4))
+ \m_atarget_hot[1]_i_1
(.I0(p_0_in1_in),
- .I1(\m_atarget_hot[4]_i_2_n_0 ),
- .O(D[0]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
+ .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
+ .O(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 [1]));
+ (* SOFT_HLUTNM = "soft_lutpair17" *)
+ LUT2 #(
+ .INIT(4'h4))
+ \m_atarget_hot[2]_i_1
+ (.I0(p_0_in1_in),
+ .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ),
+ .O(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 [2]));
+ LUT6 #(
+ .INIT(64'h8000000000000000))
+ \m_atarget_hot[2]_i_2
+ (.I0(\m_atarget_hot[5]_i_9_n_0 ),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
+ .I3(\m_atarget_hot[2]_i_3_n_0 ),
+ .I4(\m_atarget_hot[5]_i_15_n_0 ),
+ .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
+ .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h2))
- \m_atarget_hot[1]_i_1
- (.I0(target_mi_enc[0]),
- .I1(p_0_in1_in),
- .O(D[1]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
+ \m_atarget_hot[2]_i_3
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
+ .O(\m_atarget_hot[2]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'h4))
+ \m_atarget_hot[3]_i_1
+ (.I0(p_0_in1_in),
+ .I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
+ .O(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 [3]));
+ LUT6 #(
+ .INIT(64'h0080000000000000))
+ \m_atarget_hot[3]_i_2
+ (.I0(\m_atarget_hot[5]_i_9_n_0 ),
+ .I1(\m_atarget_hot[3]_i_3_n_0 ),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
+ .I4(\m_atarget_hot[5]_i_15_n_0 ),
+ .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
+ .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ));
LUT2 #(
.INIT(4'h2))
- \m_atarget_hot[2]_i_1
- (.I0(target_mi_enc[1]),
- .I1(p_0_in1_in),
- .O(D[2]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT4 #(
- .INIT(16'h0002))
+ \m_atarget_hot[3]_i_3
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
+ .O(\m_atarget_hot[3]_i_3_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair16" *)
+ LUT2 #(
+ .INIT(4'h4))
\m_atarget_hot[4]_i_1
- (.I0(\m_atarget_hot[4]_i_2_n_0 ),
- .I1(target_mi_enc[1]),
- .I2(target_mi_enc[0]),
- .I3(p_0_in1_in),
- .O(D[3]));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFE))
- \m_atarget_hot[4]_i_10
- (.I0(Q[22]),
- .I1(Q[23]),
- .I2(Q[25]),
- .I3(Q[24]),
- .I4(Q[21]),
- .I5(Q[20]),
- .O(\m_atarget_hot[4]_i_10_n_0 ));
+ (.I0(p_0_in1_in),
+ .I1(target_mi_enc),
+ .O(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 [4]));
+ (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT5 #(
+ .INIT(32'h00000001))
+ \m_atarget_hot[5]_i_1
+ (.I0(p_0_in1_in),
+ .I1(\m_atarget_hot[5]_i_2_n_0 ),
+ .I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
+ .I3(target_mi_enc),
+ .I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
+ .O(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 [5]));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \m_atarget_hot[5]_i_10
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
+ .I4(\gen_no_arbiter.m_amesg_i_reg[48]_0 [20]),
+ .I5(\gen_no_arbiter.m_amesg_i_reg[48]_0 [25]),
+ .O(\gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ));
+ LUT6 #(
+ .INIT(64'h0000000000000001))
+ \m_atarget_hot[5]_i_11
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [15]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [14]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [18]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [19]),
+ .I4(\gen_no_arbiter.m_amesg_i_reg[48]_0 [16]),
+ .I5(\gen_no_arbiter.m_amesg_i_reg[48]_0 [17]),
+ .O(\gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ));
+ LUT6 #(
+ .INIT(64'h0000000100000000))
+ \m_atarget_hot[5]_i_12
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [26]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [27]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [28]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [29]),
+ .I4(\gen_no_arbiter.m_amesg_i_reg[48]_0 [30]),
+ .I5(\gen_no_arbiter.m_amesg_i_reg[48]_0 [31]),
+ .O(\m_atarget_hot[5]_i_12_n_0 ));
+ LUT3 #(
+ .INIT(8'h01))
+ \m_atarget_hot[5]_i_13
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [9]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [8]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [7]),
+ .O(\m_atarget_hot[5]_i_13_n_0 ));
LUT4 #(
- .INIT(16'hFEFF))
- \m_atarget_hot[4]_i_2
- (.I0(\m_atarget_hot[4]_i_5_n_0 ),
- .I1(\m_atarget_hot[4]_i_6_n_0 ),
- .I2(\m_atarget_hot[4]_i_7_n_0 ),
- .I3(\m_atarget_hot[4]_i_8_n_0 ),
- .O(\m_atarget_hot[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000000000002))
- \m_atarget_hot[4]_i_3
- (.I0(\m_atarget_hot[4]_i_8_n_0 ),
- .I1(\m_atarget_hot[4]_i_9_n_0 ),
- .I2(Q[18]),
- .I3(Q[17]),
- .I4(Q[19]),
- .I5(Q[16]),
- .O(target_mi_enc[1]));
- LUT6 #(
- .INIT(64'h0000000000000002))
- \m_atarget_hot[4]_i_4
- (.I0(\m_atarget_hot[4]_i_8_n_0 ),
- .I1(\m_atarget_hot[4]_i_10_n_0 ),
- .I2(Q[18]),
- .I3(Q[17]),
- .I4(Q[19]),
- .I5(Q[16]),
- .O(target_mi_enc[0]));
+ .INIT(16'h0001))
+ \m_atarget_hot[5]_i_14
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [13]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [12]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [11]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [10]),
+ .O(\m_atarget_hot[5]_i_14_n_0 ));
+ LUT2 #(
+ .INIT(4'h1))
+ \m_atarget_hot[5]_i_15
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [25]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [20]),
+ .O(\m_atarget_hot[5]_i_15_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
- .INIT(16'hFFFE))
- \m_atarget_hot[4]_i_5
- (.I0(Q[18]),
- .I1(Q[17]),
- .I2(Q[19]),
- .I3(Q[16]),
- .O(\m_atarget_hot[4]_i_5_n_0 ));
+ .INIT(16'h0100))
+ \m_atarget_hot[5]_i_16
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [13]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [12]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
+ .O(\m_atarget_hot[5]_i_16_n_0 ));
LUT4 #(
- .INIT(16'hFFEF))
- \m_atarget_hot[4]_i_6
- (.I0(Q[13]),
- .I1(Q[15]),
- .I2(Q[22]),
- .I3(Q[14]),
- .O(\m_atarget_hot[4]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFFFD))
- \m_atarget_hot[4]_i_7
- (.I0(Q[24]),
- .I1(Q[25]),
- .I2(Q[23]),
- .I3(Q[12]),
- .I4(Q[21]),
- .I5(Q[20]),
- .O(\m_atarget_hot[4]_i_7_n_0 ));
+ .INIT(16'hC800))
+ \m_atarget_hot[5]_i_2
+ (.I0(\m_atarget_hot[5]_i_6_n_0 ),
+ .I1(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
+ .I2(\m_atarget_hot[5]_i_8_n_0 ),
+ .I3(\m_atarget_hot[5]_i_9_n_0 ),
+ .O(\m_atarget_hot[5]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h0001000000000000))
+ \m_atarget_hot[5]_i_3
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [17]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [16]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [19]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [18]),
+ .I4(\gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
+ .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
+ .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ));
+ LUT5 #(
+ .INIT(32'h80000000))
+ \m_atarget_hot[5]_i_4
+ (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
+ .I1(\gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ),
+ .I2(\m_atarget_hot[5]_i_12_n_0 ),
+ .I3(\m_atarget_hot[5]_i_13_n_0 ),
+ .I4(\m_atarget_hot[5]_i_14_n_0 ),
+ .O(target_mi_enc));
+ LUT6 #(
+ .INIT(64'h0800000000000000))
+ \m_atarget_hot[5]_i_5
+ (.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
+ .I3(\m_atarget_hot[5]_i_15_n_0 ),
+ .I4(\m_atarget_hot[5]_i_16_n_0 ),
+ .I5(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
+ .O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ));
+ LUT6 #(
+ .INIT(64'h0000000000000020))
+ \m_atarget_hot[5]_i_6
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
+ .I4(\gen_no_arbiter.m_amesg_i_reg[48]_0 [20]),
+ .I5(\gen_no_arbiter.m_amesg_i_reg[48]_0 [25]),
+ .O(\m_atarget_hot[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
- \m_atarget_hot[4]_i_8
- (.I0(Q[27]),
- .I1(Q[28]),
- .I2(Q[31]),
- .I3(Q[26]),
- .I4(Q[29]),
- .I5(Q[30]),
- .O(\m_atarget_hot[4]_i_8_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFFFFFFFDFF))
- \m_atarget_hot[4]_i_9
- (.I0(Q[24]),
- .I1(Q[25]),
- .I2(Q[20]),
- .I3(Q[21]),
- .I4(Q[23]),
- .I5(Q[22]),
- .O(\m_atarget_hot[4]_i_9_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
+ \m_atarget_hot[5]_i_7
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [28]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [29]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [26]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [27]),
+ .I4(\gen_no_arbiter.m_amesg_i_reg[48]_0 [31]),
+ .I5(\gen_no_arbiter.m_amesg_i_reg[48]_0 [30]),
+ .O(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ));
+ LUT6 #(
+ .INIT(64'h0000000000000080))
+ \m_atarget_hot[5]_i_8
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [23]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [24]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [22]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [21]),
+ .I4(\gen_no_arbiter.m_amesg_i_reg[48]_0 [20]),
+ .I5(\gen_no_arbiter.m_amesg_i_reg[48]_0 [25]),
+ .O(\m_atarget_hot[5]_i_8_n_0 ));
+ LUT4 #(
+ .INIT(16'h0001))
+ \m_atarget_hot[5]_i_9
+ (.I0(\gen_no_arbiter.m_amesg_i_reg[48]_0 [17]),
+ .I1(\gen_no_arbiter.m_amesg_i_reg[48]_0 [16]),
+ .I2(\gen_no_arbiter.m_amesg_i_reg[48]_0 [19]),
+ .I3(\gen_no_arbiter.m_amesg_i_reg[48]_0 [18]),
+ .O(\m_atarget_hot[5]_i_9_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
- .INIT(16'h0080))
+ .INIT(16'h2000))
\m_axi_arvalid[0]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]),
- .I1(aa_grant_rnw),
+ (.I0(Q[0]),
+ .I1(m_ready_d_1[1]),
.I2(m_valid_i),
- .I3(m_ready_d_1[1]),
+ .I3(aa_grant_rnw),
.O(m_axi_arvalid[0]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
- .INIT(16'h0080))
+ .INIT(16'h2000))
\m_axi_arvalid[1]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]),
- .I1(aa_grant_rnw),
+ (.I0(Q[1]),
+ .I1(m_ready_d_1[1]),
.I2(m_valid_i),
- .I3(m_ready_d_1[1]),
+ .I3(aa_grant_rnw),
.O(m_axi_arvalid[1]));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
+ (* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
- .INIT(16'h0080))
+ .INIT(16'h2000))
\m_axi_arvalid[2]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]),
- .I1(aa_grant_rnw),
+ (.I0(Q[2]),
+ .I1(m_ready_d_1[1]),
.I2(m_valid_i),
- .I3(m_ready_d_1[1]),
+ .I3(aa_grant_rnw),
.O(m_axi_arvalid[2]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT4 #(
+ .INIT(16'h2000))
+ \m_axi_arvalid[3]_INST_0
+ (.I0(Q[3]),
+ .I1(m_ready_d_1[1]),
+ .I2(m_valid_i),
+ .I3(aa_grant_rnw),
+ .O(m_axi_arvalid[3]));
+ (* SOFT_HLUTNM = "soft_lutpair14" *)
+ LUT4 #(
+ .INIT(16'h2000))
+ \m_axi_arvalid[4]_INST_0
+ (.I0(Q[4]),
+ .I1(m_ready_d_1[1]),
+ .I2(m_valid_i),
+ .I3(aa_grant_rnw),
+ .O(m_axi_arvalid[4]));
+ (* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]),
- .I1(aa_grant_rnw),
+ (.I0(Q[0]),
+ .I1(m_ready_d[2]),
.I2(m_valid_i),
- .I3(m_ready_d[2]),
+ .I3(aa_grant_rnw),
.O(m_axi_awvalid[0]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
+ (* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]),
- .I1(aa_grant_rnw),
+ (.I0(Q[1]),
+ .I1(m_ready_d[2]),
.I2(m_valid_i),
- .I3(m_ready_d[2]),
+ .I3(aa_grant_rnw),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[2]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]),
- .I1(aa_grant_rnw),
+ (.I0(Q[2]),
+ .I1(m_ready_d[2]),
.I2(m_valid_i),
- .I3(m_ready_d[2]),
+ .I3(aa_grant_rnw),
.O(m_axi_awvalid[2]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT4 #(
+ .INIT(16'h0020))
+ \m_axi_awvalid[3]_INST_0
+ (.I0(Q[3]),
+ .I1(m_ready_d[2]),
+ .I2(m_valid_i),
+ .I3(aa_grant_rnw),
+ .O(m_axi_awvalid[3]));
+ (* SOFT_HLUTNM = "soft_lutpair11" *)
+ LUT4 #(
+ .INIT(16'h0020))
+ \m_axi_awvalid[4]_INST_0
+ (.I0(Q[4]),
+ .I1(m_ready_d[2]),
+ .I2(m_valid_i),
+ .I3(aa_grant_rnw),
+ .O(m_axi_awvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
- .INIT(32'h00200000))
+ .INIT(32'h00000800))
\m_axi_bready[0]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]),
- .I1(m_ready_d[0]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_bready),
+ (.I0(Q[0]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_bready),
+ .I4(m_ready_d[0]),
.O(m_axi_bready[0]));
LUT5 #(
- .INIT(32'h00200000))
+ .INIT(32'h00000800))
\m_axi_bready[1]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]),
- .I1(m_ready_d[0]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_bready),
+ (.I0(Q[1]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_bready),
+ .I4(m_ready_d[0]),
.O(m_axi_bready[1]));
LUT5 #(
- .INIT(32'h00200000))
+ .INIT(32'h00000800))
\m_axi_bready[2]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]),
- .I1(m_ready_d[0]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_bready),
+ (.I0(Q[2]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_bready),
+ .I4(m_ready_d[0]),
.O(m_axi_bready[2]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
- .INIT(32'h00200000))
+ .INIT(32'h00000800))
+ \m_axi_bready[3]_INST_0
+ (.I0(Q[3]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_bready),
+ .I4(m_ready_d[0]),
+ .O(m_axi_bready[3]));
+ LUT5 #(
+ .INIT(32'h00000800))
+ \m_axi_bready[4]_INST_0
+ (.I0(Q[4]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_bready),
+ .I4(m_ready_d[0]),
+ .O(m_axi_bready[4]));
+ (* SOFT_HLUTNM = "soft_lutpair6" *)
+ LUT5 #(
+ .INIT(32'h00000800))
\m_axi_wvalid[0]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [0]),
- .I1(m_ready_d[1]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_wvalid),
+ (.I0(Q[0]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_wvalid),
+ .I4(m_ready_d[1]),
.O(m_axi_wvalid[0]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
- .INIT(32'h00200000))
+ .INIT(32'h00000800))
\m_axi_wvalid[1]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [1]),
- .I1(m_ready_d[1]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_wvalid),
+ (.I0(Q[1]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_wvalid),
+ .I4(m_ready_d[1]),
.O(m_axi_wvalid[1]));
LUT5 #(
- .INIT(32'h00200000))
+ .INIT(32'h00000800))
\m_axi_wvalid[2]_INST_0
- (.I0(\gen_axilite.s_axi_bvalid_i_reg [2]),
- .I1(m_ready_d[1]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_wvalid),
+ (.I0(Q[2]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_wvalid),
+ .I4(m_ready_d[1]),
.O(m_axi_wvalid[2]));
+ LUT5 #(
+ .INIT(32'h00000800))
+ \m_axi_wvalid[3]_INST_0
+ (.I0(Q[3]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_wvalid),
+ .I4(m_ready_d[1]),
+ .O(m_axi_wvalid[3]));
+ LUT5 #(
+ .INIT(32'h00000800))
+ \m_axi_wvalid[4]_INST_0
+ (.I0(Q[4]),
+ .I1(m_valid_i),
+ .I2(aa_grant_rnw),
+ .I3(s_axi_wvalid),
+ .I4(m_ready_d[1]),
+ .O(m_axi_wvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
- .INIT(32'h0080FFFF))
+ .INIT(32'h0800FFFF))
\m_payload_i[34]_i_1
- (.I0(s_axi_rready),
- .I1(aa_grant_rnw),
- .I2(m_valid_i),
- .I3(m_ready_d_1[0]),
+ (.I0(aa_grant_rnw),
+ .I1(m_valid_i),
+ .I2(m_ready_d_1[0]),
+ .I3(s_axi_rready),
.I4(sr_rvalid),
.O(E));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT4 #(
- .INIT(16'h0020))
- \m_ready_d[0]_i_2
- (.I0(s_axi_bready),
- .I1(aa_grant_rnw),
- .I2(m_valid_i),
- .I3(m_ready_d[0]),
- .O(s_axi_bready_0_sn_1));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT2 #(
- .INIT(4'h7))
- \m_ready_d[0]_i_2__0
+ LUT6 #(
+ .INIT(64'hFFFFFFFF88888880))
+ \m_ready_d[1]_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
- .O(\gen_no_arbiter.grant_rnw_reg_1 ));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT2 #(
- .INIT(4'hB))
- \m_ready_d[0]_i_3
- (.I0(\m_ready_d[0]_i_4_n_0 ),
- .I1(aresetn_d),
- .O(aresetn_d_reg));
- LUT6 #(
- .INIT(64'h00000000F8F0F8F8))
- \m_ready_d[0]_i_4
+ .I2(\m_ready_d_reg[1]_0 ),
+ .I3(\m_ready_d_reg[1]_1 ),
+ .I4(\m_ready_d_reg[1]_2 ),
+ .I5(m_ready_d_1[1]),
+ .O(m_ready_d0[1]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFF80000000))
+ \m_ready_d[1]_i_3
(.I0(aa_grant_rnw),
.I1(m_valid_i),
- .I2(m_ready_d_1[1]),
- .I3(\m_ready_d_reg[1]_0 ),
- .I4(\m_ready_d_reg[1]_1 ),
- .I5(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1 ),
- .O(\m_ready_d[0]_i_4_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT4 #(
- .INIT(16'h0020))
- \m_ready_d[1]_i_2
- (.I0(s_axi_wvalid),
- .I1(aa_grant_rnw),
- .I2(m_valid_i),
- .I3(m_ready_d[1]),
- .O(s_axi_wvalid_0_sn_1));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT5 #(
- .INIT(32'hFDF0F0F0))
- \m_ready_d[1]_i_2__0
- (.I0(\m_ready_d_reg[1]_1 ),
- .I1(\m_ready_d_reg[1]_0 ),
- .I2(m_ready_d_1[1]),
- .I3(m_valid_i),
- .I4(aa_grant_rnw),
- .O(m_ready_d0_0));
+ .I2(s_axi_rready),
+ .I3(sr_rvalid),
+ .I4(\m_ready_d_reg[1] ),
+ .I5(m_ready_d_1[0]),
+ .O(m_ready_d0[0]));
LUT6 #(
- .INIT(64'hFFFFFFFF00D00000))
- \m_ready_d[2]_i_7
- (.I0(\m_ready_d[2]_i_3 ),
- .I1(\m_ready_d[2]_i_3_0 ),
- .I2(s_axi_bready),
- .I3(aa_grant_rnw),
- .I4(m_valid_i),
- .I5(m_ready_d[0]),
- .O(m_ready_d0));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ .INIT(64'hFFFFFFFF44444440))
+ \m_ready_d[2]_i_2
+ (.I0(aa_grant_rnw),
+ .I1(m_valid_i),
+ .I2(\gen_no_arbiter.m_valid_i_reg_3 ),
+ .I3(\gen_no_arbiter.m_valid_i_reg_2 ),
+ .I4(\gen_no_arbiter.m_valid_i_reg_1 ),
+ .I5(m_ready_d[2]),
+ .O(\gen_no_arbiter.grant_rnw_reg_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
+ LUT2 #(
+ .INIT(4'h2))
+ \m_ready_d[2]_i_9
+ (.I0(m_valid_i),
+ .I1(aa_grant_rnw),
+ .O(\gen_no_arbiter.m_valid_i_reg_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
- .INIT(8'h8A))
+ .INIT(8'hC4))
m_valid_i_i_1
- (.I0(m_valid_i_reg[1]),
- .I1(m_valid_i_i_2_n_0),
- .I2(m_valid_i_i_3_n_0),
+ (.I0(E),
+ .I1(m_valid_i_reg[1]),
+ .I2(m_valid_i_i_2_n_0),
.O(\aresetn_d_reg[1] ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
- .INIT(32'h8AAAAAAA))
+ .INIT(32'hAAA8FFFF))
m_valid_i_i_2
- (.I0(sr_rvalid),
- .I1(m_ready_d_1[0]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(s_axi_rready),
+ (.I0(r_transfer_en),
+ .I1(m_valid_i_reg_0),
+ .I2(m_valid_i_reg_1),
+ .I3(m_valid_i_reg_2),
+ .I4(aa_rready),
.O(m_valid_i_i_2_n_0));
- LUT6 #(
- .INIT(64'h8AAAAAAA8AAA8AAA))
+ (* SOFT_HLUTNM = "soft_lutpair0" *)
+ LUT3 #(
+ .INIT(8'h08))
m_valid_i_i_3
- (.I0(aa_rready),
- .I1(m_ready_d_1[0]),
- .I2(m_valid_i),
- .I3(aa_grant_rnw),
- .I4(m_valid_i_reg_0),
- .I5(m_valid_i_reg_1),
- .O(m_valid_i_i_3_n_0));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
+ (.I0(aa_grant_rnw),
+ .I1(m_valid_i),
+ .I2(m_ready_d_1[0]),
+ .O(r_transfer_en));
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0040))
\s_arvalid_reg[0]_i_1
@@ -1557,46 +1390,51 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
.D(\s_awvalid_reg[0]_i_1_n_0 ),
.Q(s_awvalid_reg),
.R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
- (.I0(aa_grant_rnw),
- .I1(s_ready_i),
+ (.I0(s_ready_i),
+ .I1(aa_grant_rnw),
.O(s_axi_arready));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
+ (* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_awready));
+ (* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
- .INIT(32'h00000004))
+ .INIT(32'h00020000))
\s_axi_bvalid[0]_INST_0
- (.I0(m_ready_d[0]),
- .I1(m_valid_i),
- .I2(aa_grant_rnw),
- .I3(p_0_in1_in),
- .I4(s_axi_bvalid_0_sn_1),
+ (.I0(m_valid_i),
+ .I1(aa_grant_rnw),
+ .I2(p_0_in1_in),
+ .I3(m_ready_d[0]),
+ .I4(f_mux_return__3),
.O(s_axi_bvalid));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
+ LUT2 #(
+ .INIT(4'h4))
+ \s_axi_rvalid[0]_INST_0
+ (.I0(p_0_in1_in),
+ .I1(sr_rvalid),
+ .O(s_axi_rvalid));
LUT5 #(
- .INIT(32'h00000004))
+ .INIT(32'h00020000))
\s_axi_wready[0]_INST_0
- (.I0(m_ready_d[1]),
- .I1(m_valid_i),
- .I2(aa_grant_rnw),
- .I3(p_0_in1_in),
- .I4(s_axi_wready_0_sn_1),
+ (.I0(m_valid_i),
+ .I1(aa_grant_rnw),
+ .I2(p_0_in1_in),
+ .I3(m_ready_d[1]),
+ .I4(f_mux_return__1),
.O(s_axi_wready));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
+ (* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
- .INIT(8'h8A))
+ .INIT(8'hB0))
s_ready_i_i_1
- (.I0(m_valid_i_reg[0]),
- .I1(m_valid_i_i_3_n_0),
- .I2(m_valid_i_i_2_n_0),
+ (.I0(E),
+ .I1(m_valid_i_i_2_n_0),
+ .I2(m_valid_i_reg[0]),
.O(\aresetn_d_reg[0] ));
endmodule
@@ -1604,19 +1442,19 @@ endmodule
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *)
-(* C_FAMILY = "artix7" *) (* C_M_AXI_ADDR_WIDTH = "128'b00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100" *) (* C_M_AXI_BASE_ADDR = "256'b1111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000" *)
-(* C_M_AXI_READ_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
-(* C_M_AXI_WRITE_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
-(* C_NUM_MASTER_SLOTS = "4" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
+(* C_FAMILY = "artix7" *) (* C_M_AXI_ADDR_WIDTH = "160'b0000000000000000000000000000011100000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100" *) (* C_M_AXI_BASE_ADDR = "320'b00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000" *)
+(* C_M_AXI_READ_CONNECTIVITY = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
+(* C_M_AXI_WRITE_CONNECTIVITY = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
+(* C_NUM_MASTER_SLOTS = "5" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_33_axi_crossbar" *) (* P_ADDR_DECODE = "1" *)
-(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
-(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "artix7" *) (* P_INCR = "2'b01" *)
-(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
-(* P_M_AXI_SUPPORTS_READ = "4'b1111" *) (* P_M_AXI_SUPPORTS_WRITE = "4'b1111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
-(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
-(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
+(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
+(* P_FAMILY = "artix7" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
+(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "5'b11111" *)
+(* P_M_AXI_SUPPORTS_WRITE = "5'b11111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
+(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
+(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
(aclk,
aresetn,
@@ -1753,71 +1591,71 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
- output [3:0]m_axi_awid;
- output [127:0]m_axi_awaddr;
- output [31:0]m_axi_awlen;
- output [11:0]m_axi_awsize;
- output [7:0]m_axi_awburst;
- output [3:0]m_axi_awlock;
- output [15:0]m_axi_awcache;
- output [11:0]m_axi_awprot;
- output [15:0]m_axi_awregion;
- output [15:0]m_axi_awqos;
- output [3:0]m_axi_awuser;
- output [3:0]m_axi_awvalid;
- input [3:0]m_axi_awready;
- output [3:0]m_axi_wid;
- output [127:0]m_axi_wdata;
- output [15:0]m_axi_wstrb;
- output [3:0]m_axi_wlast;
- output [3:0]m_axi_wuser;
- output [3:0]m_axi_wvalid;
- input [3:0]m_axi_wready;
- input [3:0]m_axi_bid;
- input [7:0]m_axi_bresp;
- input [3:0]m_axi_buser;
- input [3:0]m_axi_bvalid;
- output [3:0]m_axi_bready;
- output [3:0]m_axi_arid;
- output [127:0]m_axi_araddr;
- output [31:0]m_axi_arlen;
- output [11:0]m_axi_arsize;
- output [7:0]m_axi_arburst;
- output [3:0]m_axi_arlock;
- output [15:0]m_axi_arcache;
- output [11:0]m_axi_arprot;
- output [15:0]m_axi_arregion;
- output [15:0]m_axi_arqos;
- output [3:0]m_axi_aruser;
- output [3:0]m_axi_arvalid;
- input [3:0]m_axi_arready;
- input [3:0]m_axi_rid;
- input [127:0]m_axi_rdata;
- input [7:0]m_axi_rresp;
- input [3:0]m_axi_rlast;
- input [3:0]m_axi_ruser;
- input [3:0]m_axi_rvalid;
- output [3:0]m_axi_rready;
+ output [4:0]m_axi_awid;
+ output [159:0]m_axi_awaddr;
+ output [39:0]m_axi_awlen;
+ output [14:0]m_axi_awsize;
+ output [9:0]m_axi_awburst;
+ output [4:0]m_axi_awlock;
+ output [19:0]m_axi_awcache;
+ output [14:0]m_axi_awprot;
+ output [19:0]m_axi_awregion;
+ output [19:0]m_axi_awqos;
+ output [4:0]m_axi_awuser;
+ output [4:0]m_axi_awvalid;
+ input [4:0]m_axi_awready;
+ output [4:0]m_axi_wid;
+ output [159:0]m_axi_wdata;
+ output [19:0]m_axi_wstrb;
+ output [4:0]m_axi_wlast;
+ output [4:0]m_axi_wuser;
+ output [4:0]m_axi_wvalid;
+ input [4:0]m_axi_wready;
+ input [4:0]m_axi_bid;
+ input [9:0]m_axi_bresp;
+ input [4:0]m_axi_buser;
+ input [4:0]m_axi_bvalid;
+ output [4:0]m_axi_bready;
+ output [4:0]m_axi_arid;
+ output [159:0]m_axi_araddr;
+ output [39:0]m_axi_arlen;
+ output [14:0]m_axi_arsize;
+ output [9:0]m_axi_arburst;
+ output [4:0]m_axi_arlock;
+ output [19:0]m_axi_arcache;
+ output [14:0]m_axi_arprot;
+ output [19:0]m_axi_arregion;
+ output [19:0]m_axi_arqos;
+ output [4:0]m_axi_aruser;
+ output [4:0]m_axi_arvalid;
+ input [4:0]m_axi_arready;
+ input [4:0]m_axi_rid;
+ input [159:0]m_axi_rdata;
+ input [9:0]m_axi_rresp;
+ input [4:0]m_axi_rlast;
+ input [4:0]m_axi_ruser;
+ input [4:0]m_axi_rvalid;
+ output [4:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
- wire [11:0]\^m_axi_araddr ;
+ wire [6:0]\^m_axi_araddr ;
wire [2:0]\^m_axi_arprot ;
- wire [3:0]m_axi_arready;
- wire [2:0]\^m_axi_arvalid ;
- wire [127:108]\^m_axi_awaddr ;
- wire [3:0]m_axi_awready;
- wire [2:0]\^m_axi_awvalid ;
- wire [2:0]\^m_axi_bready ;
- wire [7:0]m_axi_bresp;
- wire [3:0]m_axi_bvalid;
- wire [127:0]m_axi_rdata;
- wire [2:0]\^m_axi_rready ;
- wire [7:0]m_axi_rresp;
- wire [3:0]m_axi_rvalid;
- wire [3:0]m_axi_wready;
- wire [2:0]\^m_axi_wvalid ;
+ wire [4:0]m_axi_arready;
+ wire [4:0]m_axi_arvalid;
+ wire [159:135]\^m_axi_awaddr ;
+ wire [4:0]m_axi_awready;
+ wire [4:0]m_axi_awvalid;
+ wire [4:0]m_axi_bready;
+ wire [9:0]m_axi_bresp;
+ wire [4:0]m_axi_bvalid;
+ wire [159:0]m_axi_rdata;
+ wire [4:0]m_axi_rready;
+ wire [9:0]m_axi_rresp;
+ wire [4:0]m_axi_rvalid;
+ wire [4:0]m_axi_wready;
+ wire [4:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
@@ -1838,14 +1676,18 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
- assign m_axi_araddr[127:108] = \^m_axi_awaddr [127:108];
- assign m_axi_araddr[107:96] = \^m_axi_araddr [11:0];
- assign m_axi_araddr[95:76] = \^m_axi_awaddr [127:108];
- assign m_axi_araddr[75:64] = \^m_axi_araddr [11:0];
- assign m_axi_araddr[63:44] = \^m_axi_awaddr [127:108];
- assign m_axi_araddr[43:32] = \^m_axi_araddr [11:0];
- assign m_axi_araddr[31:12] = \^m_axi_awaddr [127:108];
- assign m_axi_araddr[11:0] = \^m_axi_araddr [11:0];
+ assign m_axi_araddr[159:135] = \^m_axi_awaddr [159:135];
+ assign m_axi_araddr[134:128] = \^m_axi_araddr [6:0];
+ assign m_axi_araddr[127:103] = \^m_axi_awaddr [159:135];
+ assign m_axi_araddr[102:96] = \^m_axi_araddr [6:0];
+ assign m_axi_araddr[95:71] = \^m_axi_awaddr [159:135];
+ assign m_axi_araddr[70:64] = \^m_axi_araddr [6:0];
+ assign m_axi_araddr[63:39] = \^m_axi_awaddr [159:135];
+ assign m_axi_araddr[38:32] = \^m_axi_araddr [6:0];
+ assign m_axi_araddr[31:7] = \^m_axi_awaddr [159:135];
+ assign m_axi_araddr[6:0] = \^m_axi_araddr [6:0];
+ assign m_axi_arburst[9] = \<const0> ;
+ assign m_axi_arburst[8] = \<const0> ;
assign m_axi_arburst[7] = \<const0> ;
assign m_axi_arburst[6] = \<const0> ;
assign m_axi_arburst[5] = \<const0> ;
@@ -1854,6 +1696,10 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_arburst[2] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
+ assign m_axi_arcache[19] = \<const0> ;
+ assign m_axi_arcache[18] = \<const0> ;
+ assign m_axi_arcache[17] = \<const0> ;
+ assign m_axi_arcache[16] = \<const0> ;
assign m_axi_arcache[15] = \<const0> ;
assign m_axi_arcache[14] = \<const0> ;
assign m_axi_arcache[13] = \<const0> ;
@@ -1870,10 +1716,19 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
+ assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
+ assign m_axi_arlen[39] = \<const0> ;
+ assign m_axi_arlen[38] = \<const0> ;
+ assign m_axi_arlen[37] = \<const0> ;
+ assign m_axi_arlen[36] = \<const0> ;
+ assign m_axi_arlen[35] = \<const0> ;
+ assign m_axi_arlen[34] = \<const0> ;
+ assign m_axi_arlen[33] = \<const0> ;
+ assign m_axi_arlen[32] = \<const0> ;
assign m_axi_arlen[31] = \<const0> ;
assign m_axi_arlen[30] = \<const0> ;
assign m_axi_arlen[29] = \<const0> ;
@@ -1906,14 +1761,20 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
+ assign m_axi_arlock[4] = \<const0> ;
assign m_axi_arlock[3] = \<const0> ;
assign m_axi_arlock[2] = \<const0> ;
assign m_axi_arlock[1] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
+ assign m_axi_arprot[14:12] = \^m_axi_arprot [2:0];
assign m_axi_arprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
+ assign m_axi_arqos[19] = \<const0> ;
+ assign m_axi_arqos[18] = \<const0> ;
+ assign m_axi_arqos[17] = \<const0> ;
+ assign m_axi_arqos[16] = \<const0> ;
assign m_axi_arqos[15] = \<const0> ;
assign m_axi_arqos[14] = \<const0> ;
assign m_axi_arqos[13] = \<const0> ;
@@ -1930,6 +1791,10 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
+ assign m_axi_arregion[19] = \<const0> ;
+ assign m_axi_arregion[18] = \<const0> ;
+ assign m_axi_arregion[17] = \<const0> ;
+ assign m_axi_arregion[16] = \<const0> ;
assign m_axi_arregion[15] = \<const0> ;
assign m_axi_arregion[14] = \<const0> ;
assign m_axi_arregion[13] = \<const0> ;
@@ -1946,6 +1811,9 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
+ assign m_axi_arsize[14] = \<const0> ;
+ assign m_axi_arsize[13] = \<const0> ;
+ assign m_axi_arsize[12] = \<const0> ;
assign m_axi_arsize[11] = \<const0> ;
assign m_axi_arsize[10] = \<const0> ;
assign m_axi_arsize[9] = \<const0> ;
@@ -1958,20 +1826,23 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
+ assign m_axi_aruser[4] = \<const0> ;
assign m_axi_aruser[3] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
- assign m_axi_arvalid[3] = \<const0> ;
- assign m_axi_arvalid[2:0] = \^m_axi_arvalid [2:0];
- assign m_axi_awaddr[127:108] = \^m_axi_awaddr [127:108];
- assign m_axi_awaddr[107:96] = \^m_axi_araddr [11:0];
- assign m_axi_awaddr[95:76] = \^m_axi_awaddr [127:108];
- assign m_axi_awaddr[75:64] = \^m_axi_araddr [11:0];
- assign m_axi_awaddr[63:44] = \^m_axi_awaddr [127:108];
- assign m_axi_awaddr[43:32] = \^m_axi_araddr [11:0];
- assign m_axi_awaddr[31:12] = \^m_axi_awaddr [127:108];
- assign m_axi_awaddr[11:0] = \^m_axi_araddr [11:0];
+ assign m_axi_awaddr[159:135] = \^m_axi_awaddr [159:135];
+ assign m_axi_awaddr[134:128] = \^m_axi_araddr [6:0];
+ assign m_axi_awaddr[127:103] = \^m_axi_awaddr [159:135];
+ assign m_axi_awaddr[102:96] = \^m_axi_araddr [6:0];
+ assign m_axi_awaddr[95:71] = \^m_axi_awaddr [159:135];
+ assign m_axi_awaddr[70:64] = \^m_axi_araddr [6:0];
+ assign m_axi_awaddr[63:39] = \^m_axi_awaddr [159:135];
+ assign m_axi_awaddr[38:32] = \^m_axi_araddr [6:0];
+ assign m_axi_awaddr[31:7] = \^m_axi_awaddr [159:135];
+ assign m_axi_awaddr[6:0] = \^m_axi_araddr [6:0];
+ assign m_axi_awburst[9] = \<const0> ;
+ assign m_axi_awburst[8] = \<const0> ;
assign m_axi_awburst[7] = \<const0> ;
assign m_axi_awburst[6] = \<const0> ;
assign m_axi_awburst[5] = \<const0> ;
@@ -1980,6 +1851,10 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_awburst[2] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
+ assign m_axi_awcache[19] = \<const0> ;
+ assign m_axi_awcache[18] = \<const0> ;
+ assign m_axi_awcache[17] = \<const0> ;
+ assign m_axi_awcache[16] = \<const0> ;
assign m_axi_awcache[15] = \<const0> ;
assign m_axi_awcache[14] = \<const0> ;
assign m_axi_awcache[13] = \<const0> ;
@@ -1996,10 +1871,19 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
+ assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
+ assign m_axi_awlen[39] = \<const0> ;
+ assign m_axi_awlen[38] = \<const0> ;
+ assign m_axi_awlen[37] = \<const0> ;
+ assign m_axi_awlen[36] = \<const0> ;
+ assign m_axi_awlen[35] = \<const0> ;
+ assign m_axi_awlen[34] = \<const0> ;
+ assign m_axi_awlen[33] = \<const0> ;
+ assign m_axi_awlen[32] = \<const0> ;
assign m_axi_awlen[31] = \<const0> ;
assign m_axi_awlen[30] = \<const0> ;
assign m_axi_awlen[29] = \<const0> ;
@@ -2032,14 +1916,20 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
+ assign m_axi_awlock[4] = \<const0> ;
assign m_axi_awlock[3] = \<const0> ;
assign m_axi_awlock[2] = \<const0> ;
assign m_axi_awlock[1] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
+ assign m_axi_awprot[14:12] = \^m_axi_arprot [2:0];
assign m_axi_awprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
+ assign m_axi_awqos[19] = \<const0> ;
+ assign m_axi_awqos[18] = \<const0> ;
+ assign m_axi_awqos[17] = \<const0> ;
+ assign m_axi_awqos[16] = \<const0> ;
assign m_axi_awqos[15] = \<const0> ;
assign m_axi_awqos[14] = \<const0> ;
assign m_axi_awqos[13] = \<const0> ;
@@ -2056,6 +1946,10 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
+ assign m_axi_awregion[19] = \<const0> ;
+ assign m_axi_awregion[18] = \<const0> ;
+ assign m_axi_awregion[17] = \<const0> ;
+ assign m_axi_awregion[16] = \<const0> ;
assign m_axi_awregion[15] = \<const0> ;
assign m_axi_awregion[14] = \<const0> ;
assign m_axi_awregion[13] = \<const0> ;
@@ -2072,6 +1966,9 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
+ assign m_axi_awsize[14] = \<const0> ;
+ assign m_axi_awsize[13] = \<const0> ;
+ assign m_axi_awsize[12] = \<const0> ;
assign m_axi_awsize[11] = \<const0> ;
assign m_axi_awsize[10] = \<const0> ;
assign m_axi_awsize[9] = \<const0> ;
@@ -2084,38 +1981,36 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
+ assign m_axi_awuser[4] = \<const0> ;
assign m_axi_awuser[3] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
- assign m_axi_awvalid[3] = \<const0> ;
- assign m_axi_awvalid[2:0] = \^m_axi_awvalid [2:0];
- assign m_axi_bready[3] = \<const0> ;
- assign m_axi_bready[2:0] = \^m_axi_bready [2:0];
- assign m_axi_rready[3] = \<const0> ;
- assign m_axi_rready[2:0] = \^m_axi_rready [2:0];
+ assign m_axi_wdata[159:128] = s_axi_wdata;
assign m_axi_wdata[127:96] = s_axi_wdata;
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
+ assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
+ assign m_axi_wlast[4] = \<const0> ;
assign m_axi_wlast[3] = \<const0> ;
assign m_axi_wlast[2] = \<const0> ;
assign m_axi_wlast[1] = \<const0> ;
assign m_axi_wlast[0] = \<const0> ;
+ assign m_axi_wstrb[19:16] = s_axi_wstrb;
assign m_axi_wstrb[15:12] = s_axi_wstrb;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
+ assign m_axi_wuser[4] = \<const0> ;
assign m_axi_wuser[3] = \<const0> ;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
- assign m_axi_wvalid[3] = \<const0> ;
- assign m_axi_wvalid[2:0] = \^m_axi_wvalid [2:0];
assign s_axi_bid[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
@@ -2128,18 +2023,18 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
- .m_axi_arvalid(\^m_axi_arvalid ),
+ .m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
- .m_axi_awvalid(\^m_axi_awvalid ),
- .m_axi_bready(\^m_axi_bready ),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
- .m_axi_rready(\^m_axi_rready ),
+ .m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
- .m_axi_wvalid(\^m_axi_wvalid ),
+ .m_axi_wvalid(m_axi_wvalid),
.\m_payload_i_reg[34] ({s_axi_rdata,s_axi_rresp}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
@@ -2158,15 +2053,14 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
.s_axi_wvalid(s_axi_wvalid));
endmodule
-(* ORIG_REF_NAME = "axi_crossbar_v2_1_33_crossbar_sasd" *)
module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
- (Q,
- \m_payload_i_reg[34] ,
- s_axi_wready,
- m_axi_wvalid,
- m_axi_awvalid,
+ (Q,
+ \m_payload_i_reg[34] ,
s_axi_bvalid,
+ s_axi_wready,
m_axi_bready,
+ m_axi_awvalid,
+ m_axi_wvalid,
m_axi_arvalid,
s_axi_bresp,
s_axi_awready,
@@ -2175,51 +2069,51 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
m_axi_rready,
aresetn,
aclk,
- s_axi_rready,
s_axi_awvalid,
s_axi_arvalid,
- m_axi_awready,
- s_axi_wvalid,
s_axi_bready,
- m_axi_rdata,
+ s_axi_wvalid,
+ s_axi_rready,
+ m_axi_bresp,
m_axi_rresp,
- m_axi_bvalid,
- m_axi_arready,
+ m_axi_rdata,
m_axi_rvalid,
- m_axi_bresp,
+ m_axi_arready,
+ m_axi_bvalid,
m_axi_wready,
+ m_axi_awready,
s_axi_arprot,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr);
output [34:0]Q;
output [33:0]\m_payload_i_reg[34] ;
- output [0:0]s_axi_wready;
- output [2:0]m_axi_wvalid;
- output [2:0]m_axi_awvalid;
output [0:0]s_axi_bvalid;
- output [2:0]m_axi_bready;
- output [2:0]m_axi_arvalid;
+ output [0:0]s_axi_wready;
+ output [4:0]m_axi_bready;
+ output [4:0]m_axi_awvalid;
+ output [4:0]m_axi_wvalid;
+ output [4:0]m_axi_arvalid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
- output [2:0]m_axi_rready;
+ output [4:0]m_axi_rready;
input aresetn;
input aclk;
- input [0:0]s_axi_rready;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_arvalid;
- input [3:0]m_axi_awready;
- input [0:0]s_axi_wvalid;
input [0:0]s_axi_bready;
- input [127:0]m_axi_rdata;
- input [7:0]m_axi_rresp;
- input [3:0]m_axi_bvalid;
- input [3:0]m_axi_arready;
- input [3:0]m_axi_rvalid;
- input [7:0]m_axi_bresp;
- input [3:0]m_axi_wready;
+ input [0:0]s_axi_wvalid;
+ input [0:0]s_axi_rready;
+ input [9:0]m_axi_bresp;
+ input [9:0]m_axi_rresp;
+ input [159:0]m_axi_rdata;
+ input [4:0]m_axi_rvalid;
+ input [4:0]m_axi_arready;
+ input [4:0]m_axi_bvalid;
+ input [4:0]m_axi_wready;
+ input [4:0]m_axi_awready;
input [2:0]s_axi_arprot;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
@@ -2229,60 +2123,55 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
- wire addr_arbiter_inst_n_10;
- wire addr_arbiter_inst_n_4;
- wire addr_arbiter_inst_n_5;
- wire addr_arbiter_inst_n_52;
- wire addr_arbiter_inst_n_60;
- wire addr_arbiter_inst_n_61;
- wire addr_arbiter_inst_n_62;
- wire addr_arbiter_inst_n_63;
- wire addr_arbiter_inst_n_69;
- wire addr_arbiter_inst_n_70;
- wire addr_arbiter_inst_n_73;
- wire addr_arbiter_inst_n_74;
- wire addr_arbiter_inst_n_9;
- wire any_error;
+ wire addr_arbiter_inst_n_21;
+ wire addr_arbiter_inst_n_22;
+ wire addr_arbiter_inst_n_24;
+ wire addr_arbiter_inst_n_36;
+ wire addr_arbiter_inst_n_37;
+ wire addr_arbiter_inst_n_38;
+ wire addr_arbiter_inst_n_80;
+ wire addr_arbiter_inst_n_81;
wire aresetn;
wire aresetn_d;
- wire \gen_decerr.decerr_slave_inst_n_2 ;
- wire \gen_decerr.decerr_slave_inst_n_3 ;
+ wire f_mux_return2;
+ wire f_mux_return3;
+ wire f_mux_return__1;
+ wire f_mux_return__3;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
- wire \gen_decerr.decerr_slave_inst_n_6 ;
- wire \gen_decerr.decerr_slave_inst_n_7 ;
wire \gen_decerr.decerr_slave_inst_n_8 ;
wire [2:0]m_atarget_enc;
- wire [4:0]m_atarget_hot;
- wire [2:0]m_atarget_hot0;
- wire [3:0]m_axi_arready;
- wire [2:0]m_axi_arvalid;
- wire [3:0]m_axi_awready;
- wire [2:0]m_axi_awvalid;
- wire [2:0]m_axi_bready;
- wire [7:0]m_axi_bresp;
- wire [3:0]m_axi_bvalid;
- wire [127:0]m_axi_rdata;
- wire [2:0]m_axi_rready;
- wire [7:0]m_axi_rresp;
- wire [3:0]m_axi_rvalid;
- wire [3:0]m_axi_wready;
- wire [2:0]m_axi_wvalid;
+ wire [5:0]m_atarget_hot;
+ wire [5:0]m_atarget_hot0;
+ wire [4:0]m_axi_arready;
+ wire [4:0]m_axi_arvalid;
+ wire [4:0]m_axi_awready;
+ wire [4:0]m_axi_awvalid;
+ wire [4:0]m_axi_bready;
+ wire [9:0]m_axi_bresp;
+ wire [4:0]m_axi_bvalid;
+ wire [159:0]m_axi_rdata;
+ wire [4:0]m_axi_rready;
+ wire [9:0]m_axi_rresp;
+ wire [4:0]m_axi_rvalid;
+ wire [4:0]m_axi_wready;
+ wire [4:0]m_axi_wvalid;
wire [33:0]\m_payload_i_reg[34] ;
wire [1:0]m_ready_d;
- wire [1:1]m_ready_d0;
- wire [0:0]m_ready_d0_0;
+ wire [1:0]m_ready_d0;
+ wire [2:0]m_ready_d0_0;
wire [2:0]m_ready_d_1;
wire m_valid_i;
- wire [4:4]mi_bvalid;
- wire [4:4]mi_wready;
- wire p_0_in1_in;
+ wire mi_arvalid_en;
+ wire [5:5]mi_bvalid;
+ wire [5:5]mi_wready;
wire p_1_in;
wire reg_slice_r_n_2;
wire reg_slice_r_n_37;
wire reg_slice_r_n_38;
- wire reg_slice_r_n_43;
- wire reg_slice_r_n_44;
+ wire reg_slice_r_n_39;
+ wire reg_slice_r_n_45;
+ wire reg_slice_r_n_46;
wire reset;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
@@ -2302,55 +2191,58 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire splitter_ar_n_0;
+ wire splitter_ar_n_1;
+ wire splitter_aw_n_0;
+ wire splitter_aw_n_1;
+ wire splitter_aw_n_2;
wire splitter_aw_n_3;
wire splitter_aw_n_4;
+ wire splitter_aw_n_5;
wire sr_rvalid;
mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd addr_arbiter_inst
- (.D({addr_arbiter_inst_n_5,m_atarget_hot0}),
+ (.D({addr_arbiter_inst_n_36,addr_arbiter_inst_n_37,addr_arbiter_inst_n_38}),
.E(p_1_in),
- .Q(Q),
+ .Q(m_atarget_hot),
.SR(reset),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
- .aresetn_d_reg(addr_arbiter_inst_n_4),
- .\aresetn_d_reg[0] (addr_arbiter_inst_n_62),
- .\aresetn_d_reg[1] (addr_arbiter_inst_n_63),
- .aresetn_d_reg_0(addr_arbiter_inst_n_9),
- .aresetn_d_reg_1(addr_arbiter_inst_n_10),
- .\gen_axilite.s_axi_awready_i_reg (addr_arbiter_inst_n_73),
- .\gen_axilite.s_axi_bvalid_i_reg ({m_atarget_hot[4],m_atarget_hot[2:0]}),
- .\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_61),
- .\gen_no_arbiter.grant_rnw_reg_1 (addr_arbiter_inst_n_70),
- .\gen_no_arbiter.m_amesg_i_reg[19]_0 (any_error),
- .\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0 (\gen_decerr.decerr_slave_inst_n_8 ),
- .\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1 (reg_slice_r_n_2),
- .\gen_no_arbiter.m_valid_i_reg_0 (splitter_aw_n_3),
- .m_atarget_enc(m_atarget_enc),
+ .\aresetn_d_reg[0] (addr_arbiter_inst_n_22),
+ .\aresetn_d_reg[1] (addr_arbiter_inst_n_24),
+ .f_mux_return__1(f_mux_return__1),
+ .f_mux_return__3(f_mux_return__3),
+ .\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_81),
+ .\gen_no_arbiter.grant_rnw_reg_0 (m_ready_d0_0[2]),
+ .\gen_no_arbiter.m_amesg_i_reg[48]_0 (Q),
+ .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 (m_atarget_hot0),
+ .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 (reg_slice_r_n_2),
+ .\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_inst_n_21),
+ .\gen_no_arbiter.m_valid_i_reg_1 (splitter_aw_n_2),
+ .\gen_no_arbiter.m_valid_i_reg_2 (\gen_decerr.decerr_slave_inst_n_8 ),
+ .\gen_no_arbiter.m_valid_i_reg_3 (splitter_aw_n_5),
+ .\m_atarget_hot_reg[5] (addr_arbiter_inst_n_80),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
- .m_axi_wready(m_axi_wready[3:2]),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d_1),
- .m_ready_d0(m_ready_d0_0),
- .m_ready_d0_0(m_ready_d0),
- .\m_ready_d[2]_i_3 (\gen_decerr.decerr_slave_inst_n_4 ),
- .\m_ready_d[2]_i_3_0 (splitter_aw_n_4),
+ .m_ready_d0(m_ready_d0),
+ .m_ready_d0_0(m_ready_d0_0[1:0]),
.m_ready_d_1(m_ready_d),
- .\m_ready_d_reg[1] (addr_arbiter_inst_n_69),
- .\m_ready_d_reg[1]_0 (splitter_ar_n_0),
+ .\m_ready_d_reg[1] (reg_slice_r_n_37),
+ .\m_ready_d_reg[1]_0 (splitter_ar_n_1),
.\m_ready_d_reg[1]_1 (\gen_decerr.decerr_slave_inst_n_5 ),
- .\m_ready_d_reg[2] (addr_arbiter_inst_n_74),
+ .\m_ready_d_reg[1]_2 (splitter_ar_n_0),
.m_valid_i(m_valid_i),
- .m_valid_i_reg({reg_slice_r_n_43,reg_slice_r_n_44}),
- .m_valid_i_reg_0(reg_slice_r_n_38),
- .m_valid_i_reg_1(\gen_decerr.decerr_slave_inst_n_6 ),
+ .m_valid_i_reg({reg_slice_r_n_45,reg_slice_r_n_46}),
+ .m_valid_i_reg_0(reg_slice_r_n_39),
+ .m_valid_i_reg_1(\gen_decerr.decerr_slave_inst_n_4 ),
+ .m_valid_i_reg_2(reg_slice_r_n_38),
+ .mi_arvalid_en(mi_arvalid_en),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
- .p_0_in1_in(p_0_in1_in),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
@@ -2360,14 +2252,11 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
- .s_axi_bready_0_sp_1(addr_arbiter_inst_n_60),
.s_axi_bvalid(s_axi_bvalid),
- .s_axi_bvalid_0_sp_1(\gen_decerr.decerr_slave_inst_n_3 ),
.s_axi_rready(s_axi_rready),
+ .s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
- .s_axi_wready_0_sp_1(\gen_decerr.decerr_slave_inst_n_7 ),
.s_axi_wvalid(s_axi_wvalid),
- .s_axi_wvalid_0_sp_1(addr_arbiter_inst_n_52),
.sr_rvalid(sr_rvalid));
FDRE #(
.INIT(1'b0))
@@ -2378,35 +2267,44 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
.Q(aresetn_d),
.R(1'b0));
mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave \gen_decerr.decerr_slave_inst
- (.Q(m_atarget_hot[4]),
+ (.Q(m_atarget_hot[5]),
.SR(reset),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
- .\gen_axilite.s_axi_arready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_5 ),
- .\gen_axilite.s_axi_awready_i_reg_0 (addr_arbiter_inst_n_74),
- .\gen_axilite.s_axi_bvalid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_3 ),
- .\gen_axilite.s_axi_bvalid_i_reg_1 (addr_arbiter_inst_n_73),
- .\gen_axilite.s_axi_rvalid_i_reg_0 (\gen_decerr.decerr_slave_inst_n_6 ),
- .\gen_axilite.s_axi_rvalid_i_reg_1 (addr_arbiter_inst_n_69),
- .m_atarget_enc(m_atarget_enc),
- .\m_atarget_enc_reg[1] (\gen_decerr.decerr_slave_inst_n_2 ),
- .m_axi_arready(m_axi_arready[2]),
- .m_axi_bvalid(m_axi_bvalid[2]),
- .\m_axi_bvalid[2] (\gen_decerr.decerr_slave_inst_n_4 ),
- .m_axi_rvalid(m_axi_rvalid[1]),
- .m_axi_wready(m_axi_wready),
- .m_axi_wready_0_sp_1(\gen_decerr.decerr_slave_inst_n_8 ),
- .m_axi_wready_3_sp_1(\gen_decerr.decerr_slave_inst_n_7 ),
- .\m_ready_d_reg[0] (splitter_aw_n_4),
+ .f_mux_return2(f_mux_return2),
+ .f_mux_return3(f_mux_return3),
+ .f_mux_return__1(f_mux_return__1),
+ .f_mux_return__3(f_mux_return__3),
+ .\gen_axilite.s_axi_awready_i_reg_0 (addr_arbiter_inst_n_81),
+ .\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_80),
+ .m_axi_arready(m_axi_arready[0]),
+ .m_axi_arready_0_sp_1(\gen_decerr.decerr_slave_inst_n_5 ),
+ .m_axi_awready(m_axi_awready[0]),
+ .m_axi_awready_0_sp_1(\gen_decerr.decerr_slave_inst_n_8 ),
+ .m_axi_bvalid({m_axi_bvalid[4:3],m_axi_bvalid[0]}),
+ .m_axi_rvalid(m_axi_rvalid[0]),
+ .m_axi_rvalid_0_sp_1(\gen_decerr.decerr_slave_inst_n_4 ),
+ .m_axi_wready({m_axi_wready[4:3],m_axi_wready[0]}),
+ .m_ready_d(m_ready_d_1[1:0]),
+ .m_ready_d0(m_ready_d0_0[1:0]),
+ .\m_ready_d[2]_i_2 (m_atarget_enc),
+ .\m_ready_d_reg[2] (splitter_aw_n_3),
+ .\m_ready_d_reg[2]_0 (splitter_aw_n_0),
+ .\m_ready_d_reg[2]_1 (addr_arbiter_inst_n_21),
+ .\m_ready_d_reg[2]_2 (splitter_aw_n_4),
+ .\m_ready_d_reg[2]_3 (splitter_aw_n_1),
+ .mi_arvalid_en(mi_arvalid_en),
.mi_bvalid(mi_bvalid),
- .mi_wready(mi_wready));
+ .mi_wready(mi_wready),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_wvalid(s_axi_wvalid));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
- .D(addr_arbiter_inst_n_9),
+ .D(addr_arbiter_inst_n_38),
.Q(m_atarget_enc[0]),
.R(1'b0));
FDRE #(
@@ -2414,7 +2312,7 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
\m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
- .D(addr_arbiter_inst_n_10),
+ .D(addr_arbiter_inst_n_37),
.Q(m_atarget_enc[1]),
.R(1'b0));
FDRE #(
@@ -2422,9 +2320,9 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
\m_atarget_enc_reg[2]
(.C(aclk),
.CE(1'b1),
- .D(any_error),
+ .D(addr_arbiter_inst_n_36),
.Q(m_atarget_enc[2]),
- .R(reset));
+ .R(1'b0));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[0]
@@ -2449,14 +2347,30 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
.D(m_atarget_hot0[2]),
.Q(m_atarget_hot[2]),
.R(reset));
+ FDRE #(
+ .INIT(1'b0))
+ \m_atarget_hot_reg[3]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(m_atarget_hot0[3]),
+ .Q(m_atarget_hot[3]),
+ .R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[4]
(.C(aclk),
.CE(1'b1),
- .D(addr_arbiter_inst_n_5),
+ .D(m_atarget_hot0[4]),
.Q(m_atarget_hot[4]),
.R(reset));
+ FDRE #(
+ .INIT(1'b0))
+ \m_atarget_hot_reg[5]
+ (.C(aclk),
+ .CE(1'b1),
+ .D(m_atarget_hot0[5]),
+ .Q(m_atarget_hot[5]),
+ .R(reset));
mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice reg_slice_r
(.E(p_1_in),
.Q({\m_payload_i_reg[34] ,reg_slice_r_n_37}),
@@ -2464,140 +2378,172 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
- .\aresetn_d_reg[1]_0 ({reg_slice_r_n_43,reg_slice_r_n_44}),
- .m_atarget_enc(m_atarget_enc),
+ .\aresetn_d_reg[1]_0 ({reg_slice_r_n_45,reg_slice_r_n_46}),
+ .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv (splitter_ar_n_0),
+ .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 (\gen_decerr.decerr_slave_inst_n_5 ),
+ .\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 (splitter_ar_n_1),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
- .\m_axi_rready[2] (m_atarget_hot[2:0]),
+ .\m_axi_rready[4] (m_atarget_hot[4:0]),
.m_axi_rresp(m_axi_rresp),
- .m_axi_rvalid({m_axi_rvalid[3:2],m_axi_rvalid[0]}),
+ .m_axi_rvalid(m_axi_rvalid[4:1]),
+ .\m_axi_rvalid[4] (reg_slice_r_n_39),
.m_axi_rvalid_2_sp_1(reg_slice_r_n_38),
- .m_ready_d(m_ready_d[0]),
+ .\m_payload_i_reg[0]_0 (m_atarget_enc),
+ .m_ready_d(m_ready_d),
+ .\m_ready_d_reg[1] (reg_slice_r_n_2),
.m_valid_i(m_valid_i),
- .m_valid_i_reg_0(reg_slice_r_n_2),
- .m_valid_i_reg_1(addr_arbiter_inst_n_63),
- .p_0_in1_in(p_0_in1_in),
+ .m_valid_i_reg_0(addr_arbiter_inst_n_24),
+ .mi_arvalid_en(mi_arvalid_en),
.s_axi_rready(s_axi_rready),
- .s_axi_rvalid(s_axi_rvalid),
- .s_ready_i_reg_0(addr_arbiter_inst_n_62),
+ .s_ready_i_reg_0(addr_arbiter_inst_n_22),
.sr_rvalid(sr_rvalid));
- LUT5 #(
- .INIT(32'hFFFF0038))
+ LUT6 #(
+ .INIT(64'hAABEAABAAAAEAAAA))
\s_axi_bresp[0]_INST_0
- (.I0(m_axi_bresp[2]),
+ (.I0(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
.I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[1]),
- .I4(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
+ .I2(m_atarget_enc[1]),
+ .I3(m_atarget_enc[2]),
+ .I4(m_axi_bresp[2]),
+ .I5(m_axi_bresp[4]),
.O(s_axi_bresp[0]));
LUT6 #(
- .INIT(64'h00CA000F00CA0000))
+ .INIT(64'h0FF00A0C0F000A0C))
\s_axi_bresp[0]_INST_0_i_1
- (.I0(m_axi_bresp[4]),
- .I1(m_axi_bresp[6]),
- .I2(m_atarget_enc[0]),
+ (.I0(m_axi_bresp[8]),
+ .I1(m_axi_bresp[0]),
+ .I2(m_atarget_enc[1]),
.I3(m_atarget_enc[2]),
- .I4(m_atarget_enc[1]),
- .I5(m_axi_bresp[0]),
+ .I4(m_atarget_enc[0]),
+ .I5(m_axi_bresp[6]),
.O(\s_axi_bresp[0]_INST_0_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF000E))
+ LUT6 #(
+ .INIT(64'hAABEAABAAAAEAAAA))
\s_axi_bresp[1]_INST_0
- (.I0(m_axi_bresp[1]),
- .I1(m_atarget_enc[2]),
+ (.I0(\s_axi_bresp[1]_INST_0_i_1_n_0 ),
+ .I1(m_atarget_enc[0]),
.I2(m_atarget_enc[1]),
- .I3(m_atarget_enc[0]),
- .I4(\s_axi_bresp[1]_INST_0_i_1_n_0 ),
+ .I3(m_atarget_enc[2]),
+ .I4(m_axi_bresp[3]),
+ .I5(m_axi_bresp[5]),
.O(s_axi_bresp[1]));
LUT6 #(
- .INIT(64'h0A0F0C000A000C00))
+ .INIT(64'h0FF00A0C0F000A0C))
\s_axi_bresp[1]_INST_0_i_1
- (.I0(m_axi_bresp[7]),
- .I1(m_axi_bresp[5]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[1]),
+ (.I0(m_axi_bresp[9]),
+ .I1(m_axi_bresp[1]),
+ .I2(m_atarget_enc[1]),
+ .I3(m_atarget_enc[2]),
.I4(m_atarget_enc[0]),
- .I5(m_axi_bresp[3]),
+ .I5(m_axi_bresp[7]),
.O(\s_axi_bresp[1]_INST_0_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT3 #(
+ .INIT(8'h04))
+ \s_axi_wready[0]_INST_0_i_2
+ (.I0(m_atarget_enc[1]),
+ .I1(m_atarget_enc[2]),
+ .I2(m_atarget_enc[0]),
+ .O(f_mux_return2));
+ (* SOFT_HLUTNM = "soft_lutpair23" *)
+ LUT3 #(
+ .INIT(8'h40))
+ \s_axi_wready[0]_INST_0_i_3
+ (.I0(m_atarget_enc[2]),
+ .I1(m_atarget_enc[1]),
+ .I2(m_atarget_enc[0]),
+ .O(f_mux_return3));
mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0 splitter_ar
- (.Q(reg_slice_r_n_37),
+ (.Q(m_atarget_enc),
.aclk(aclk),
.aresetn_d(aresetn_d),
- .m_atarget_enc(m_atarget_enc),
- .m_axi_arready({m_axi_arready[3],m_axi_arready[1:0]}),
- .m_axi_arready_1_sp_1(splitter_ar_n_0),
+ .m_axi_arready(m_axi_arready[4:1]),
+ .\m_axi_arready[4] (splitter_ar_n_1),
+ .m_axi_arready_2_sp_1(splitter_ar_n_0),
.m_ready_d(m_ready_d),
- .m_ready_d0(m_ready_d0),
- .\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_70),
- .\m_ready_d_reg[0]_1 (addr_arbiter_inst_n_4),
- .\m_ready_d_reg[1]_0 (reg_slice_r_n_2),
- .s_axi_rready(s_axi_rready),
- .sr_rvalid(sr_rvalid));
+ .m_ready_d0(m_ready_d0));
mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter splitter_aw
- (.aclk(aclk),
+ (.Q(m_atarget_enc),
+ .aclk(aclk),
.aresetn_d(aresetn_d),
- .m_atarget_enc(m_atarget_enc),
- .m_axi_awready(m_axi_awready),
- .m_axi_bvalid({m_axi_bvalid[3],m_axi_bvalid[1:0]}),
- .m_axi_bvalid_0_sp_1(splitter_aw_n_4),
+ .m_axi_awready(m_axi_awready[4:1]),
+ .\m_axi_awready[4] (splitter_aw_n_5),
+ .m_axi_awready_2_sp_1(splitter_aw_n_2),
+ .m_axi_bvalid(m_axi_bvalid[4:1]),
+ .\m_axi_bvalid[4] (splitter_aw_n_3),
+ .m_axi_bvalid_2_sp_1(splitter_aw_n_0),
+ .m_axi_wready(m_axi_wready[4:1]),
+ .\m_axi_wready[4] (splitter_aw_n_4),
+ .m_axi_wready_2_sp_1(splitter_aw_n_1),
.m_ready_d(m_ready_d_1),
- .m_ready_d0(m_ready_d0_0),
- .\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_60),
- .\m_ready_d_reg[0]_1 (\gen_decerr.decerr_slave_inst_n_3 ),
- .\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_7 ),
- .\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_52),
- .\m_ready_d_reg[2]_0 (splitter_aw_n_3),
- .\m_ready_d_reg[2]_1 (addr_arbiter_inst_n_61),
- .\m_ready_d_reg[2]_2 (\gen_decerr.decerr_slave_inst_n_2 ));
+ .m_ready_d0(m_ready_d0_0));
endmodule
-(* ORIG_REF_NAME = "axi_crossbar_v2_1_33_decerr_slave" *)
module mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave
(mi_bvalid,
mi_wready,
- \m_atarget_enc_reg[1] ,
- \gen_axilite.s_axi_bvalid_i_reg_0 ,
- \m_axi_bvalid[2] ,
- \gen_axilite.s_axi_arready_i_reg_0 ,
- \gen_axilite.s_axi_rvalid_i_reg_0 ,
- m_axi_wready_3_sp_1,
- m_axi_wready_0_sp_1,
+ m_ready_d0,
+ m_axi_rvalid_0_sp_1,
+ m_axi_arready_0_sp_1,
+ f_mux_return__3,
+ f_mux_return__1,
+ m_axi_awready_0_sp_1,
SR,
- \gen_axilite.s_axi_bvalid_i_reg_1 ,
+ \gen_axilite.s_axi_bvalid_i_reg_0 ,
aclk,
\gen_axilite.s_axi_awready_i_reg_0 ,
- m_atarget_enc,
- Q,
- \gen_axilite.s_axi_rvalid_i_reg_1 ,
+ \m_ready_d_reg[2] ,
+ \m_ready_d_reg[2]_0 ,
+ s_axi_bready,
+ \m_ready_d_reg[2]_1 ,
+ m_ready_d,
+ \m_ready_d_reg[2]_2 ,
+ \m_ready_d_reg[2]_3 ,
+ s_axi_wvalid,
aresetn_d,
- m_axi_bvalid,
- \m_ready_d_reg[0] ,
- m_axi_arready,
+ mi_arvalid_en,
+ Q,
m_axi_rvalid,
+ \m_ready_d[2]_i_2 ,
+ m_axi_arready,
+ m_axi_bvalid,
+ f_mux_return2,
+ f_mux_return3,
m_axi_wready,
+ m_axi_awready,
aa_rready);
output [0:0]mi_bvalid;
output [0:0]mi_wready;
- output \m_atarget_enc_reg[1] ;
- output \gen_axilite.s_axi_bvalid_i_reg_0 ;
- output \m_axi_bvalid[2] ;
- output \gen_axilite.s_axi_arready_i_reg_0 ;
- output \gen_axilite.s_axi_rvalid_i_reg_0 ;
- output m_axi_wready_3_sp_1;
- output m_axi_wready_0_sp_1;
+ output [1:0]m_ready_d0;
+ output m_axi_rvalid_0_sp_1;
+ output m_axi_arready_0_sp_1;
+ output f_mux_return__3;
+ output f_mux_return__1;
+ output m_axi_awready_0_sp_1;
input [0:0]SR;
- input \gen_axilite.s_axi_bvalid_i_reg_1 ;
+ input \gen_axilite.s_axi_bvalid_i_reg_0 ;
input aclk;
input \gen_axilite.s_axi_awready_i_reg_0 ;
- input [2:0]m_atarget_enc;
- input [0:0]Q;
- input \gen_axilite.s_axi_rvalid_i_reg_1 ;
+ input \m_ready_d_reg[2] ;
+ input \m_ready_d_reg[2]_0 ;
+ input [0:0]s_axi_bready;
+ input \m_ready_d_reg[2]_1 ;
+ input [1:0]m_ready_d;
+ input \m_ready_d_reg[2]_2 ;
+ input \m_ready_d_reg[2]_3 ;
+ input [0:0]s_axi_wvalid;
input aresetn_d;
- input [0:0]m_axi_bvalid;
- input \m_ready_d_reg[0] ;
- input [0:0]m_axi_arready;
+ input mi_arvalid_en;
+ input [0:0]Q;
input [0:0]m_axi_rvalid;
- input [3:0]m_axi_wready;
+ input [2:0]\m_ready_d[2]_i_2 ;
+ input [0:0]m_axi_arready;
+ input [2:0]m_axi_bvalid;
+ input f_mux_return2;
+ input f_mux_return3;
+ input [2:0]m_axi_wready;
+ input [0:0]m_axi_awready;
input aa_rready;
wire [0:0]Q;
@@ -2605,39 +2551,51 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave
wire aa_rready;
wire aclk;
wire aresetn_d;
+ wire f_mux_return2;
+ wire f_mux_return3;
+ wire f_mux_return__1;
+ wire f_mux_return__3;
wire \gen_axilite.s_axi_arready_i_i_1_n_0 ;
- wire \gen_axilite.s_axi_arready_i_reg_0 ;
wire \gen_axilite.s_axi_awready_i_reg_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
- wire \gen_axilite.s_axi_bvalid_i_reg_1 ;
wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
- wire \gen_axilite.s_axi_rvalid_i_reg_0 ;
- wire \gen_axilite.s_axi_rvalid_i_reg_1 ;
- wire [2:0]m_atarget_enc;
- wire \m_atarget_enc_reg[1] ;
wire [0:0]m_axi_arready;
- wire [0:0]m_axi_bvalid;
- wire \m_axi_bvalid[2] ;
+ wire m_axi_arready_0_sn_1;
+ wire [0:0]m_axi_awready;
+ wire m_axi_awready_0_sn_1;
+ wire [2:0]m_axi_bvalid;
wire [0:0]m_axi_rvalid;
- wire [3:0]m_axi_wready;
- wire m_axi_wready_0_sn_1;
- wire m_axi_wready_3_sn_1;
- wire \m_ready_d_reg[0] ;
- wire [4:4]mi_arready;
+ wire m_axi_rvalid_0_sn_1;
+ wire [2:0]m_axi_wready;
+ wire [1:0]m_ready_d;
+ wire [1:0]m_ready_d0;
+ wire [2:0]\m_ready_d[2]_i_2 ;
+ wire \m_ready_d_reg[2] ;
+ wire \m_ready_d_reg[2]_0 ;
+ wire \m_ready_d_reg[2]_1 ;
+ wire \m_ready_d_reg[2]_2 ;
+ wire \m_ready_d_reg[2]_3 ;
+ wire [5:5]mi_arready;
+ wire mi_arvalid_en;
wire [0:0]mi_bvalid;
- wire [4:4]mi_rvalid;
+ wire [5:5]mi_rvalid;
wire [0:0]mi_wready;
+ wire [0:0]s_axi_bready;
+ wire \s_axi_bvalid[0]_INST_0_i_2_n_0 ;
+ wire \s_axi_wready[0]_INST_0_i_4_n_0 ;
+ wire [0:0]s_axi_wvalid;
- assign m_axi_wready_0_sp_1 = m_axi_wready_0_sn_1;
- assign m_axi_wready_3_sp_1 = m_axi_wready_3_sn_1;
+ assign m_axi_arready_0_sp_1 = m_axi_arready_0_sn_1;
+ assign m_axi_awready_0_sp_1 = m_axi_awready_0_sn_1;
+ assign m_axi_rvalid_0_sp_1 = m_axi_rvalid_0_sn_1;
LUT5 #(
- .INIT(32'hF07F0000))
+ .INIT(32'hA02AA0AA))
\gen_axilite.s_axi_arready_i_i_1
- (.I0(Q),
- .I1(\gen_axilite.s_axi_rvalid_i_reg_1 ),
+ (.I0(aresetn_d),
+ .I1(mi_arvalid_en),
.I2(mi_arready),
.I3(mi_rvalid),
- .I4(aresetn_d),
+ .I4(Q),
.O(\gen_axilite.s_axi_arready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
@@ -2660,16 +2618,16 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave
\gen_axilite.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
- .D(\gen_axilite.s_axi_bvalid_i_reg_1 ),
+ .D(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.Q(mi_bvalid),
.R(SR));
LUT5 #(
- .INIT(32'h08F8F0F0))
+ .INIT(32'h55C0FF00))
\gen_axilite.s_axi_rvalid_i_i_1
- (.I0(mi_arready),
- .I1(\gen_axilite.s_axi_rvalid_i_reg_1 ),
- .I2(mi_rvalid),
- .I3(aa_rready),
+ (.I0(aa_rready),
+ .I1(mi_arvalid_en),
+ .I2(mi_arready),
+ .I3(mi_rvalid),
.I4(Q),
.O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
FDRE #(
@@ -2681,189 +2639,205 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave
.Q(mi_rvalid),
.R(SR));
LUT5 #(
- .INIT(32'hFDCFFDFF))
- \m_ready_d[1]_i_4
- (.I0(mi_arready),
- .I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[1]),
- .I3(m_atarget_enc[2]),
- .I4(m_axi_arready),
- .O(\gen_axilite.s_axi_arready_i_reg_0 ));
- LUT4 #(
- .INIT(16'h0400))
- \m_ready_d[2]_i_5
- (.I0(m_atarget_enc[1]),
- .I1(m_atarget_enc[2]),
- .I2(m_atarget_enc[0]),
- .I3(mi_wready),
- .O(\m_atarget_enc_reg[1] ));
+ .INIT(32'h0C00000A))
+ \m_ready_d[1]_i_5
+ (.I0(m_axi_arready),
+ .I1(mi_arready),
+ .I2(\m_ready_d[2]_i_2 [1]),
+ .I3(\m_ready_d[2]_i_2 [2]),
+ .I4(\m_ready_d[2]_i_2 [0]),
+ .O(m_axi_arready_0_sn_1));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFE000000))
+ \m_ready_d[2]_i_3
+ (.I0(\m_ready_d_reg[2]_2 ),
+ .I1(\s_axi_wready[0]_INST_0_i_4_n_0 ),
+ .I2(\m_ready_d_reg[2]_3 ),
+ .I3(s_axi_wvalid),
+ .I4(\m_ready_d_reg[2]_1 ),
+ .I5(m_ready_d[1]),
+ .O(m_ready_d0[1]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFE000000))
+ \m_ready_d[2]_i_4
+ (.I0(\m_ready_d_reg[2] ),
+ .I1(\s_axi_bvalid[0]_INST_0_i_2_n_0 ),
+ .I2(\m_ready_d_reg[2]_0 ),
+ .I3(s_axi_bready),
+ .I4(\m_ready_d_reg[2]_1 ),
+ .I5(m_ready_d[0]),
+ .O(m_ready_d0[0]));
LUT5 #(
- .INIT(32'hFDCFFDFF))
- \m_ready_d[2]_i_8
- (.I0(m_axi_bvalid),
- .I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[1]),
- .I4(mi_bvalid),
- .O(\m_axi_bvalid[2] ));
+ .INIT(32'h0C00000A))
+ \m_ready_d[2]_i_6
+ (.I0(m_axi_awready),
+ .I1(mi_wready),
+ .I2(\m_ready_d[2]_i_2 [1]),
+ .I3(\m_ready_d[2]_i_2 [2]),
+ .I4(\m_ready_d[2]_i_2 [0]),
+ .O(m_axi_awready_0_sn_1));
LUT5 #(
- .INIT(32'hFCDFFFDF))
+ .INIT(32'h0C00000A))
m_valid_i_i_5
- (.I0(mi_rvalid),
- .I1(m_atarget_enc[1]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[0]),
- .I4(m_axi_rvalid),
- .O(\gen_axilite.s_axi_rvalid_i_reg_0 ));
+ (.I0(m_axi_rvalid),
+ .I1(mi_rvalid),
+ .I2(\m_ready_d[2]_i_2 [1]),
+ .I3(\m_ready_d[2]_i_2 [2]),
+ .I4(\m_ready_d[2]_i_2 [0]),
+ .O(m_axi_rvalid_0_sn_1));
LUT6 #(
- .INIT(64'h00000000FFD3FFDF))
+ .INIT(64'hFFFFFFFFFFFFF888))
\s_axi_bvalid[0]_INST_0_i_1
- (.I0(mi_bvalid),
- .I1(m_atarget_enc[1]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[0]),
- .I4(m_axi_bvalid),
- .I5(\m_ready_d_reg[0] ),
- .O(\gen_axilite.s_axi_bvalid_i_reg_0 ));
+ (.I0(m_axi_bvalid[2]),
+ .I1(f_mux_return2),
+ .I2(m_axi_bvalid[1]),
+ .I3(f_mux_return3),
+ .I4(\s_axi_bvalid[0]_INST_0_i_2_n_0 ),
+ .I5(\m_ready_d_reg[2]_0 ),
+ .O(f_mux_return__3));
+ LUT5 #(
+ .INIT(32'h0C00000A))
+ \s_axi_bvalid[0]_INST_0_i_2
+ (.I0(m_axi_bvalid[0]),
+ .I1(mi_bvalid),
+ .I2(\m_ready_d[2]_i_2 [1]),
+ .I3(\m_ready_d[2]_i_2 [2]),
+ .I4(\m_ready_d[2]_i_2 [0]),
+ .O(\s_axi_bvalid[0]_INST_0_i_2_n_0 ));
LUT6 #(
- .INIT(64'h00000000F4FFF7FF))
+ .INIT(64'hFFFFFFFFFFFFF888))
\s_axi_wready[0]_INST_0_i_1
- (.I0(m_axi_wready[3]),
- .I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[1]),
- .I4(m_axi_wready[2]),
- .I5(m_axi_wready_0_sn_1),
- .O(m_axi_wready_3_sn_1));
- LUT6 #(
- .INIT(64'h00000FCA000000CA))
- \s_axi_wready[0]_INST_0_i_2
- (.I0(m_axi_wready[0]),
- .I1(m_axi_wready[1]),
- .I2(m_atarget_enc[0]),
- .I3(m_atarget_enc[2]),
- .I4(m_atarget_enc[1]),
- .I5(mi_wready),
- .O(m_axi_wready_0_sn_1));
+ (.I0(m_axi_wready[2]),
+ .I1(f_mux_return2),
+ .I2(m_axi_wready[1]),
+ .I3(f_mux_return3),
+ .I4(\s_axi_wready[0]_INST_0_i_4_n_0 ),
+ .I5(\m_ready_d_reg[2]_3 ),
+ .O(f_mux_return__1));
+ LUT5 #(
+ .INIT(32'h00A0000C))
+ \s_axi_wready[0]_INST_0_i_4
+ (.I0(mi_wready),
+ .I1(m_axi_wready[0]),
+ .I2(\m_ready_d[2]_i_2 [2]),
+ .I3(\m_ready_d[2]_i_2 [1]),
+ .I4(\m_ready_d[2]_i_2 [0]),
+ .O(\s_axi_wready[0]_INST_0_i_4_n_0 ));
endmodule
-(* ORIG_REF_NAME = "axi_crossbar_v2_1_33_splitter" *)
module mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter
- (m_ready_d,
- \m_ready_d_reg[2]_0 ,
- m_axi_bvalid_0_sp_1,
- m_atarget_enc,
- \m_ready_d_reg[1]_0 ,
- \m_ready_d_reg[1]_1 ,
- m_ready_d0,
- \m_ready_d_reg[2]_1 ,
- \m_ready_d_reg[2]_2 ,
- m_axi_awready,
+ (m_axi_bvalid_2_sp_1,
+ m_axi_wready_2_sp_1,
+ m_axi_awready_2_sp_1,
+ \m_axi_bvalid[4] ,
+ \m_axi_wready[4] ,
+ \m_axi_awready[4] ,
+ m_ready_d,
m_axi_bvalid,
+ Q,
+ m_axi_wready,
+ m_axi_awready,
aresetn_d,
- \m_ready_d_reg[0]_0 ,
- \m_ready_d_reg[0]_1 ,
+ m_ready_d0,
aclk);
+ output m_axi_bvalid_2_sp_1;
+ output m_axi_wready_2_sp_1;
+ output m_axi_awready_2_sp_1;
+ output \m_axi_bvalid[4] ;
+ output \m_axi_wready[4] ;
+ output \m_axi_awready[4] ;
output [2:0]m_ready_d;
- output \m_ready_d_reg[2]_0 ;
- output m_axi_bvalid_0_sp_1;
- input [2:0]m_atarget_enc;
- input \m_ready_d_reg[1]_0 ;
- input \m_ready_d_reg[1]_1 ;
- input [0:0]m_ready_d0;
- input \m_ready_d_reg[2]_1 ;
- input \m_ready_d_reg[2]_2 ;
+ input [3:0]m_axi_bvalid;
+ input [2:0]Q;
+ input [3:0]m_axi_wready;
input [3:0]m_axi_awready;
- input [2:0]m_axi_bvalid;
input aresetn_d;
- input \m_ready_d_reg[0]_0 ;
- input \m_ready_d_reg[0]_1 ;
+ input [2:0]m_ready_d0;
input aclk;
+ wire [2:0]Q;
wire aclk;
wire aresetn_d;
- wire [2:0]m_atarget_enc;
wire [3:0]m_axi_awready;
- wire [2:0]m_axi_bvalid;
- wire m_axi_bvalid_0_sn_1;
+ wire \m_axi_awready[4] ;
+ wire m_axi_awready_2_sn_1;
+ wire [3:0]m_axi_bvalid;
+ wire \m_axi_bvalid[4] ;
+ wire m_axi_bvalid_2_sn_1;
+ wire [3:0]m_axi_wready;
+ wire \m_axi_wready[4] ;
+ wire m_axi_wready_2_sn_1;
wire [2:0]m_ready_d;
- wire [0:0]m_ready_d0;
+ wire [2:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
- wire \m_ready_d[2]_i_3_n_0 ;
- wire \m_ready_d[2]_i_4_n_0 ;
- wire \m_ready_d[2]_i_6_n_0 ;
- wire \m_ready_d_reg[0]_0 ;
- wire \m_ready_d_reg[0]_1 ;
- wire \m_ready_d_reg[1]_0 ;
- wire \m_ready_d_reg[1]_1 ;
- wire \m_ready_d_reg[2]_0 ;
- wire \m_ready_d_reg[2]_1 ;
- wire \m_ready_d_reg[2]_2 ;
- assign m_axi_bvalid_0_sp_1 = m_axi_bvalid_0_sn_1;
- LUT5 #(
- .INIT(32'hF2000000))
+ assign m_axi_awready_2_sp_1 = m_axi_awready_2_sn_1;
+ assign m_axi_bvalid_2_sp_1 = m_axi_bvalid_2_sn_1;
+ assign m_axi_wready_2_sp_1 = m_axi_wready_2_sn_1;
+ LUT4 #(
+ .INIT(16'h2A00))
\m_ready_d[0]_i_1
- (.I0(\m_ready_d_reg[0]_0 ),
- .I1(\m_ready_d_reg[0]_1 ),
- .I2(m_ready_d[0]),
- .I3(\m_ready_d[2]_i_3_n_0 ),
- .I4(aresetn_d),
+ (.I0(aresetn_d),
+ .I1(m_ready_d0[2]),
+ .I2(m_ready_d0[1]),
+ .I3(m_ready_d0[0]),
.O(\m_ready_d[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'hBA000000))
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT4 #(
+ .INIT(16'h20A0))
\m_ready_d[1]_i_1
- (.I0(m_ready_d[1]),
- .I1(\m_ready_d_reg[1]_0 ),
- .I2(\m_ready_d_reg[1]_1 ),
- .I3(\m_ready_d[2]_i_3_n_0 ),
- .I4(aresetn_d),
+ (.I0(aresetn_d),
+ .I1(m_ready_d0[2]),
+ .I2(m_ready_d0[1]),
+ .I3(m_ready_d0[0]),
.O(\m_ready_d[1]_i_1_n_0 ));
- LUT3 #(
- .INIT(8'h40))
+ (* SOFT_HLUTNM = "soft_lutpair22" *)
+ LUT4 #(
+ .INIT(16'h0888))
\m_ready_d[2]_i_1
- (.I0(\m_ready_d_reg[2]_0 ),
- .I1(\m_ready_d[2]_i_3_n_0 ),
- .I2(aresetn_d),
+ (.I0(aresetn_d),
+ .I1(m_ready_d0[2]),
+ .I2(m_ready_d0[1]),
+ .I3(m_ready_d0[0]),
.O(\m_ready_d[2]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h4445444444454445))
- \m_ready_d[2]_i_2
- (.I0(m_ready_d[2]),
- .I1(\m_ready_d_reg[2]_1 ),
- .I2(\m_ready_d[2]_i_4_n_0 ),
- .I3(\m_ready_d_reg[2]_2 ),
- .I4(\m_ready_d[2]_i_6_n_0 ),
- .I5(m_axi_awready[1]),
- .O(\m_ready_d_reg[2]_0 ));
LUT5 #(
- .INIT(32'hFF45FFFF))
- \m_ready_d[2]_i_3
- (.I0(m_ready_d[1]),
- .I1(\m_ready_d_reg[1]_0 ),
- .I2(\m_ready_d_reg[1]_1 ),
- .I3(\m_ready_d_reg[2]_0 ),
- .I4(m_ready_d0),
- .O(\m_ready_d[2]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h00CA000F00CA0000))
- \m_ready_d[2]_i_4
- (.I0(m_axi_awready[2]),
- .I1(m_axi_awready[3]),
- .I2(m_atarget_enc[0]),
- .I3(m_atarget_enc[2]),
- .I4(m_atarget_enc[1]),
- .I5(m_axi_awready[0]),
- .O(\m_ready_d[2]_i_4_n_0 ));
- LUT3 #(
- .INIT(8'hEF))
- \m_ready_d[2]_i_6
- (.I0(m_atarget_enc[1]),
- .I1(m_atarget_enc[2]),
- .I2(m_atarget_enc[0]),
- .O(\m_ready_d[2]_i_6_n_0 ));
+ .INIT(32'h0C0000A0))
+ \m_ready_d[2]_i_10
+ (.I0(m_axi_bvalid[3]),
+ .I1(m_axi_bvalid[2]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(\m_axi_bvalid[4] ));
+ LUT5 #(
+ .INIT(32'h0C0000A0))
+ \m_ready_d[2]_i_5
+ (.I0(m_axi_awready[3]),
+ .I1(m_axi_awready[2]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(\m_axi_awready[4] ));
+ LUT5 #(
+ .INIT(32'h000C0A00))
+ \m_ready_d[2]_i_7
+ (.I0(m_axi_awready[1]),
+ .I1(m_axi_awready[0]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(m_axi_awready_2_sn_1));
+ LUT5 #(
+ .INIT(32'h0C0000A0))
+ \m_ready_d[2]_i_8
+ (.I0(m_axi_wready[3]),
+ .I1(m_axi_wready[2]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(\m_axi_wready[4] ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
@@ -2888,91 +2862,91 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
- LUT6 #(
- .INIT(64'h00F000CA000000CA))
- \s_axi_bvalid[0]_INST_0_i_2
- (.I0(m_axi_bvalid[0]),
- .I1(m_axi_bvalid[1]),
- .I2(m_atarget_enc[0]),
- .I3(m_atarget_enc[2]),
- .I4(m_atarget_enc[1]),
- .I5(m_axi_bvalid[2]),
- .O(m_axi_bvalid_0_sn_1));
+ LUT5 #(
+ .INIT(32'h000C0A00))
+ \s_axi_bvalid[0]_INST_0_i_3
+ (.I0(m_axi_bvalid[1]),
+ .I1(m_axi_bvalid[0]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(m_axi_bvalid_2_sn_1));
+ LUT5 #(
+ .INIT(32'h000C0A00))
+ \s_axi_wready[0]_INST_0_i_5
+ (.I0(m_axi_wready[1]),
+ .I1(m_axi_wready[0]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(m_axi_wready_2_sn_1));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_33_splitter" *)
module mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0
- (m_axi_arready_1_sp_1,
+ (m_axi_arready_2_sp_1,
+ \m_axi_arready[4] ,
m_ready_d,
m_axi_arready,
- m_atarget_enc,
+ Q,
aresetn_d,
m_ready_d0,
- \m_ready_d_reg[1]_0 ,
- sr_rvalid,
- Q,
- s_axi_rready,
- \m_ready_d_reg[0]_0 ,
- \m_ready_d_reg[0]_1 ,
aclk);
- output m_axi_arready_1_sp_1;
+ output m_axi_arready_2_sp_1;
+ output \m_axi_arready[4] ;
output [1:0]m_ready_d;
- input [2:0]m_axi_arready;
- input [2:0]m_atarget_enc;
+ input [3:0]m_axi_arready;
+ input [2:0]Q;
input aresetn_d;
- input [0:0]m_ready_d0;
- input \m_ready_d_reg[1]_0 ;
- input sr_rvalid;
- input [0:0]Q;
- input [0:0]s_axi_rready;
- input \m_ready_d_reg[0]_0 ;
- input \m_ready_d_reg[0]_1 ;
+ input [1:0]m_ready_d0;
input aclk;
- wire [0:0]Q;
+ wire [2:0]Q;
wire aclk;
wire aresetn_d;
- wire [2:0]m_atarget_enc;
- wire [2:0]m_axi_arready;
- wire m_axi_arready_1_sn_1;
+ wire [3:0]m_axi_arready;
+ wire \m_axi_arready[4] ;
+ wire m_axi_arready_2_sn_1;
wire [1:0]m_ready_d;
- wire [0:0]m_ready_d0;
+ wire [1:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
- wire \m_ready_d_reg[0]_0 ;
- wire \m_ready_d_reg[0]_1 ;
- wire \m_ready_d_reg[1]_0 ;
- wire [0:0]s_axi_rready;
- wire sr_rvalid;
- assign m_axi_arready_1_sp_1 = m_axi_arready_1_sn_1;
- LUT6 #(
- .INIT(64'h00000000FFFF0080))
+ assign m_axi_arready_2_sp_1 = m_axi_arready_2_sn_1;
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
+ LUT3 #(
+ .INIT(8'h20))
\m_ready_d[0]_i_1
- (.I0(sr_rvalid),
- .I1(Q),
- .I2(s_axi_rready),
- .I3(\m_ready_d_reg[0]_0 ),
- .I4(m_ready_d[0]),
- .I5(\m_ready_d_reg[0]_1 ),
+ (.I0(aresetn_d),
+ .I1(m_ready_d0[1]),
+ .I2(m_ready_d0[0]),
.O(\m_ready_d[0]_i_1_n_0 ));
+ (* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
- .INIT(8'h80))
+ .INIT(8'h08))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
- .I1(m_ready_d0),
- .I2(\m_ready_d_reg[1]_0 ),
+ .I1(m_ready_d0[1]),
+ .I2(m_ready_d0[0]),
.O(\m_ready_d[1]_i_1_n_0 ));
- LUT6 #(
- .INIT(64'h00C000AF00C000A0))
- \m_ready_d[1]_i_5
- (.I0(m_axi_arready[1]),
+ LUT5 #(
+ .INIT(32'h0C0000A0))
+ \m_ready_d[1]_i_4
+ (.I0(m_axi_arready[3]),
.I1(m_axi_arready[2]),
- .I2(m_atarget_enc[0]),
- .I3(m_atarget_enc[2]),
- .I4(m_atarget_enc[1]),
- .I5(m_axi_arready[0]),
- .O(m_axi_arready_1_sn_1));
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(\m_axi_arready[4] ));
+ LUT5 #(
+ .INIT(32'h000C0A00))
+ \m_ready_d[1]_i_6
+ (.I0(m_axi_arready[1]),
+ .I1(m_axi_arready[0]),
+ .I2(Q[2]),
+ .I3(Q[1]),
+ .I4(Q[0]),
+ .O(m_axi_arready_2_sn_1));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
@@ -2991,52 +2965,57 @@ module mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0
.R(1'b0));
endmodule
-(* ORIG_REF_NAME = "axi_register_slice_v2_1_32_axic_register_slice" *)
module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
(sr_rvalid,
aa_rready,
- m_valid_i_reg_0,
+ \m_ready_d_reg[1] ,
Q,
m_axi_rvalid_2_sp_1,
- s_axi_rvalid,
+ \m_axi_rvalid[4] ,
m_axi_rready,
\aresetn_d_reg[1]_0 ,
- m_valid_i_reg_1,
+ m_valid_i_reg_0,
aclk,
s_ready_i_reg_0,
- m_atarget_enc,
+ m_ready_d,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ,
+ mi_arvalid_en,
s_axi_rready,
- aa_grant_rnw,
m_valid_i,
- m_ready_d,
- m_axi_rdata,
+ aa_grant_rnw,
m_axi_rresp,
+ m_axi_rdata,
+ \m_payload_i_reg[0]_0 ,
m_axi_rvalid,
- p_0_in1_in,
- \m_axi_rready[2] ,
+ \m_axi_rready[4] ,
SR,
E);
output sr_rvalid;
output aa_rready;
- output m_valid_i_reg_0;
+ output \m_ready_d_reg[1] ;
output [34:0]Q;
output m_axi_rvalid_2_sp_1;
- output [0:0]s_axi_rvalid;
- output [2:0]m_axi_rready;
+ output \m_axi_rvalid[4] ;
+ output [4:0]m_axi_rready;
output [1:0]\aresetn_d_reg[1]_0 ;
- input m_valid_i_reg_1;
+ input m_valid_i_reg_0;
input aclk;
input s_ready_i_reg_0;
- input [2:0]m_atarget_enc;
+ input [1:0]m_ready_d;
+ input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ;
+ input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
+ input \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ;
+ input mi_arvalid_en;
input [0:0]s_axi_rready;
- input aa_grant_rnw;
input m_valid_i;
- input [0:0]m_ready_d;
- input [127:0]m_axi_rdata;
- input [7:0]m_axi_rresp;
- input [2:0]m_axi_rvalid;
- input p_0_in1_in;
- input [2:0]\m_axi_rready[2] ;
+ input aa_grant_rnw;
+ input [9:0]m_axi_rresp;
+ input [159:0]m_axi_rdata;
+ input [2:0]\m_payload_i_reg[0]_0 ;
+ input [3:0]m_axi_rvalid;
+ input [4:0]\m_axi_rready[4] ;
input [0:0]SR;
input [0:0]E;
@@ -3047,36 +3026,63 @@ module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
wire aa_rready;
wire aclk;
wire [1:0]\aresetn_d_reg[1]_0 ;
- wire [2:0]m_atarget_enc;
- wire [127:0]m_axi_rdata;
- wire [2:0]m_axi_rready;
- wire [2:0]\m_axi_rready[2] ;
- wire [7:0]m_axi_rresp;
- wire [2:0]m_axi_rvalid;
+ wire \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5_n_0 ;
+ wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv ;
+ wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ;
+ wire \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ;
+ wire [159:0]m_axi_rdata;
+ wire [4:0]m_axi_rready;
+ wire [4:0]\m_axi_rready[4] ;
+ wire [9:0]m_axi_rresp;
+ wire [3:0]m_axi_rvalid;
+ wire \m_axi_rvalid[4] ;
wire m_axi_rvalid_2_sn_1;
wire \m_payload_i[10]_i_2_n_0 ;
+ wire \m_payload_i[10]_i_3_n_0 ;
wire \m_payload_i[11]_i_2_n_0 ;
+ wire \m_payload_i[11]_i_3_n_0 ;
wire \m_payload_i[12]_i_2_n_0 ;
+ wire \m_payload_i[12]_i_3_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
+ wire \m_payload_i[13]_i_3_n_0 ;
wire \m_payload_i[14]_i_2_n_0 ;
+ wire \m_payload_i[14]_i_3_n_0 ;
wire \m_payload_i[15]_i_2_n_0 ;
+ wire \m_payload_i[15]_i_3_n_0 ;
wire \m_payload_i[16]_i_2_n_0 ;
+ wire \m_payload_i[16]_i_3_n_0 ;
wire \m_payload_i[17]_i_2_n_0 ;
+ wire \m_payload_i[17]_i_3_n_0 ;
wire \m_payload_i[18]_i_2_n_0 ;
+ wire \m_payload_i[18]_i_3_n_0 ;
wire \m_payload_i[19]_i_2_n_0 ;
+ wire \m_payload_i[19]_i_3_n_0 ;
wire \m_payload_i[1]_i_2_n_0 ;
+ wire \m_payload_i[1]_i_3_n_0 ;
wire \m_payload_i[20]_i_2_n_0 ;
+ wire \m_payload_i[20]_i_3_n_0 ;
wire \m_payload_i[21]_i_2_n_0 ;
+ wire \m_payload_i[21]_i_3_n_0 ;
wire \m_payload_i[22]_i_2_n_0 ;
+ wire \m_payload_i[22]_i_3_n_0 ;
wire \m_payload_i[23]_i_2_n_0 ;
+ wire \m_payload_i[23]_i_3_n_0 ;
wire \m_payload_i[24]_i_2_n_0 ;
+ wire \m_payload_i[24]_i_3_n_0 ;
wire \m_payload_i[25]_i_2_n_0 ;
+ wire \m_payload_i[25]_i_3_n_0 ;
wire \m_payload_i[26]_i_2_n_0 ;
+ wire \m_payload_i[26]_i_3_n_0 ;
wire \m_payload_i[27]_i_2_n_0 ;
+ wire \m_payload_i[27]_i_3_n_0 ;
wire \m_payload_i[28]_i_2_n_0 ;
+ wire \m_payload_i[28]_i_3_n_0 ;
wire \m_payload_i[29]_i_2_n_0 ;
+ wire \m_payload_i[29]_i_3_n_0 ;
wire \m_payload_i[2]_i_2_n_0 ;
+ wire \m_payload_i[2]_i_3_n_0 ;
wire \m_payload_i[30]_i_2_n_0 ;
+ wire \m_payload_i[30]_i_3_n_0 ;
wire \m_payload_i[31]_i_2_n_0 ;
wire \m_payload_i[31]_i_3_n_0 ;
wire \m_payload_i[32]_i_2_n_0 ;
@@ -3086,20 +3092,28 @@ module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
wire \m_payload_i[34]_i_3_n_0 ;
wire \m_payload_i[34]_i_4_n_0 ;
wire \m_payload_i[34]_i_5_n_0 ;
+ wire \m_payload_i[34]_i_6_n_0 ;
wire \m_payload_i[3]_i_2_n_0 ;
+ wire \m_payload_i[3]_i_3_n_0 ;
wire \m_payload_i[4]_i_2_n_0 ;
+ wire \m_payload_i[4]_i_3_n_0 ;
wire \m_payload_i[5]_i_2_n_0 ;
+ wire \m_payload_i[5]_i_3_n_0 ;
wire \m_payload_i[6]_i_2_n_0 ;
+ wire \m_payload_i[6]_i_3_n_0 ;
wire \m_payload_i[7]_i_2_n_0 ;
+ wire \m_payload_i[7]_i_3_n_0 ;
wire \m_payload_i[8]_i_2_n_0 ;
+ wire \m_payload_i[8]_i_3_n_0 ;
wire \m_payload_i[9]_i_2_n_0 ;
- wire [0:0]m_ready_d;
+ wire \m_payload_i[9]_i_3_n_0 ;
+ wire [2:0]\m_payload_i_reg[0]_0 ;
+ wire [1:0]m_ready_d;
+ wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire m_valid_i_reg_0;
- wire m_valid_i_reg_1;
- wire p_0_in1_in;
+ wire mi_arvalid_en;
wire [0:0]s_axi_rready;
- wire [0:0]s_axi_rvalid;
wire s_ready_i_reg_0;
wire [34:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
@@ -3156,731 +3170,1097 @@ module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
.D(\aresetn_d_reg[1]_0 [0]),
.Q(\aresetn_d_reg[1]_0 [1]),
.R(SR));
+ LUT6 #(
+ .INIT(64'hAAAAAAA888888888))
+ \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3
+ (.I0(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_5_n_0 ),
+ .I1(m_ready_d[1]),
+ .I2(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv ),
+ .I3(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0 ),
+ .I4(\gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1 ),
+ .I5(mi_arvalid_en),
+ .O(\m_ready_d_reg[1] ));
+ LUT6 #(
+ .INIT(64'hEAAAAAAA00000000))
+ \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5
+ (.I0(m_ready_d[0]),
+ .I1(Q[0]),
+ .I2(sr_rvalid),
+ .I3(s_axi_rready),
+ .I4(m_valid_i),
+ .I5(aa_grant_rnw),
+ .O(\gen_no_arbiter.m_grant_hot_i[0]_inv_i_5_n_0 ));
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
- (.I0(aa_rready),
- .I1(\m_axi_rready[2] [0]),
+ (.I0(\m_axi_rready[4] [0]),
+ .I1(aa_rready),
.O(m_axi_rready[0]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
- (.I0(aa_rready),
- .I1(\m_axi_rready[2] [1]),
+ (.I0(\m_axi_rready[4] [1]),
+ .I1(aa_rready),
.O(m_axi_rready[1]));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
+ (* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[2]_INST_0
- (.I0(aa_rready),
- .I1(\m_axi_rready[2] [2]),
+ (.I0(\m_axi_rready[4] [2]),
+ .I1(aa_rready),
.O(m_axi_rready[2]));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \m_axi_rready[3]_INST_0
+ (.I0(\m_axi_rready[4] [3]),
+ .I1(aa_rready),
+ .O(m_axi_rready[3]));
+ (* SOFT_HLUTNM = "soft_lutpair19" *)
+ LUT2 #(
+ .INIT(4'h8))
+ \m_axi_rready[4]_INST_0
+ (.I0(\m_axi_rready[4] [4]),
+ .I1(aa_rready),
+ .O(m_axi_rready[4]));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[10]_i_1
- (.I0(m_axi_rdata[7]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[10]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
- .I3(aa_rready),
- .I4(\m_payload_i[10]_i_2_n_0 ),
+ .I3(m_axi_rdata[7]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[10]_i_3_n_0 ),
.O(skid_buffer[10]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[10]_i_2
- (.I0(m_axi_rdata[71]),
- .I1(\m_payload_i[32]_i_2_n_0 ),
- .I2(m_axi_rdata[103]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(m_axi_rdata[39]),
+ (.I0(m_axi_rdata[135]),
+ .I1(m_axi_rdata[103]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[10]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFF222))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[10]_i_3
+ (.I0(m_axi_rdata[71]),
+ .I1(m_axi_rdata[39]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[10]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[11]_i_1
- (.I0(\skid_buffer_reg_n_0_[11] ),
+ (.I0(\m_payload_i[11]_i_2_n_0 ),
.I1(aa_rready),
- .I2(m_axi_rdata[72]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(\m_payload_i[11]_i_2_n_0 ),
+ .I2(\skid_buffer_reg_n_0_[11] ),
+ .I3(m_axi_rdata[8]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[11]_i_3_n_0 ),
.O(skid_buffer[11]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[11]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[40]),
- .I2(m_axi_rdata[8]),
- .I3(\m_payload_i[31]_i_2_n_0 ),
- .I4(m_axi_rdata[104]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[136]),
+ .I1(m_axi_rdata[104]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[11]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[11]_i_3
+ (.I0(m_axi_rdata[72]),
+ .I1(m_axi_rdata[40]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[11]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[12]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[12] ),
- .I3(m_axi_rdata[105]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[12]_i_2_n_0 ),
+ (.I0(\m_payload_i[12]_i_2_n_0 ),
+ .I1(m_axi_rdata[9]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[137]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[12]_i_3_n_0 ),
.O(skid_buffer[12]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[12]_i_2
- (.I0(\m_payload_i[31]_i_2_n_0 ),
- .I1(m_axi_rdata[9]),
- .I2(m_axi_rdata[41]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[73]),
- .I5(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[105]),
+ .I1(m_axi_rdata[73]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[12]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[12]_i_3
+ (.I0(\skid_buffer_reg_n_0_[12] ),
+ .I1(m_axi_rdata[41]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[12]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[13]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[13] ),
- .I3(m_axi_rdata[106]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[13]_i_2_n_0 ),
+ (.I0(\m_payload_i[13]_i_2_n_0 ),
+ .I1(m_axi_rdata[10]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[138]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[13]_i_3_n_0 ),
.O(skid_buffer[13]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[13]_i_2
- (.I0(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[106]),
.I1(m_axi_rdata[74]),
- .I2(m_axi_rdata[42]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[10]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[13]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[13]_i_3
+ (.I0(\skid_buffer_reg_n_0_[13] ),
+ .I1(m_axi_rdata[42]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[13]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[14]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[14] ),
- .I3(m_axi_rdata[75]),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(\m_payload_i[14]_i_2_n_0 ),
+ (.I0(\m_payload_i[14]_i_2_n_0 ),
+ .I1(m_axi_rdata[11]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[139]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[14]_i_3_n_0 ),
.O(skid_buffer[14]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[14]_i_2
- (.I0(\m_payload_i[34]_i_4_n_0 ),
- .I1(m_axi_rdata[107]),
- .I2(m_axi_rdata[43]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[11]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(m_axi_rdata[107]),
+ .I1(m_axi_rdata[75]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[14]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[14]_i_3
+ (.I0(\skid_buffer_reg_n_0_[14] ),
+ .I1(m_axi_rdata[43]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[14]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[15]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[15] ),
- .I3(m_axi_rdata[44]),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(\m_payload_i[15]_i_2_n_0 ),
+ (.I0(\m_payload_i[15]_i_2_n_0 ),
+ .I1(m_axi_rdata[12]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[140]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[15]_i_3_n_0 ),
.O(skid_buffer[15]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[15]_i_2
- (.I0(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[108]),
.I1(m_axi_rdata[76]),
- .I2(m_axi_rdata[108]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(m_axi_rdata[12]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[15]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[15]_i_3
+ (.I0(\skid_buffer_reg_n_0_[15] ),
+ .I1(m_axi_rdata[44]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[15]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[16]_i_1
- (.I0(m_axi_rdata[13]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[16]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
- .I3(aa_rready),
- .I4(\m_payload_i[16]_i_2_n_0 ),
+ .I3(m_axi_rdata[13]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[16]_i_3_n_0 ),
.O(skid_buffer[16]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[16]_i_2
- (.I0(m_axi_rdata[45]),
- .I1(\m_payload_i[33]_i_2_n_0 ),
- .I2(m_axi_rdata[109]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(m_axi_rdata[77]),
+ (.I0(m_axi_rdata[141]),
+ .I1(m_axi_rdata[109]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[16]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[16]_i_3
+ (.I0(m_axi_rdata[77]),
+ .I1(m_axi_rdata[45]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[16]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[17]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[17] ),
- .I3(m_axi_rdata[46]),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(\m_payload_i[17]_i_2_n_0 ),
+ (.I0(\m_payload_i[17]_i_2_n_0 ),
+ .I1(m_axi_rdata[14]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[142]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[17]_i_3_n_0 ),
.O(skid_buffer[17]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[17]_i_2
- (.I0(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[110]),
.I1(m_axi_rdata[78]),
- .I2(m_axi_rdata[110]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(m_axi_rdata[14]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[17]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[17]_i_3
+ (.I0(\skid_buffer_reg_n_0_[17] ),
+ .I1(m_axi_rdata[46]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[17]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[18]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[18] ),
- .I3(m_axi_rdata[111]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[18]_i_2_n_0 ),
+ (.I0(\m_payload_i[18]_i_2_n_0 ),
+ .I1(m_axi_rdata[15]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[143]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[18]_i_3_n_0 ),
.O(skid_buffer[18]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[18]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[47]),
- .I2(m_axi_rdata[79]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[15]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(m_axi_rdata[111]),
+ .I1(m_axi_rdata[79]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[18]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[18]_i_3
+ (.I0(\skid_buffer_reg_n_0_[18] ),
+ .I1(m_axi_rdata[47]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[18]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[19]_i_1
- (.I0(m_axi_rdata[16]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[19]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
- .I3(aa_rready),
- .I4(\m_payload_i[19]_i_2_n_0 ),
+ .I3(m_axi_rdata[16]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[19]_i_3_n_0 ),
.O(skid_buffer[19]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[19]_i_2
- (.I0(m_axi_rdata[48]),
- .I1(\m_payload_i[33]_i_2_n_0 ),
- .I2(m_axi_rdata[112]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(m_axi_rdata[80]),
+ (.I0(m_axi_rdata[144]),
+ .I1(m_axi_rdata[112]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[19]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[19]_i_3
+ (.I0(m_axi_rdata[80]),
+ .I1(m_axi_rdata[48]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[19]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[1]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[1] ),
- .I3(m_axi_rresp[4]),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(\m_payload_i[1]_i_2_n_0 ),
+ (.I0(\m_payload_i[1]_i_2_n_0 ),
+ .I1(m_axi_rresp[0]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rresp[8]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[1]_i_3_n_0 ),
.O(skid_buffer[1]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[1]_i_2
- (.I0(\m_payload_i[31]_i_2_n_0 ),
- .I1(m_axi_rresp[0]),
- .I2(m_axi_rresp[2]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rresp[6]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rresp[6]),
+ .I1(m_axi_rresp[4]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[1]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[1]_i_3
+ (.I0(\skid_buffer_reg_n_0_[1] ),
+ .I1(m_axi_rresp[2]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[1]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[20]_i_1
- (.I0(m_axi_rdata[17]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[20]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
- .I3(aa_rready),
- .I4(\m_payload_i[20]_i_2_n_0 ),
+ .I3(m_axi_rdata[17]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[20]_i_3_n_0 ),
.O(skid_buffer[20]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[20]_i_2
- (.I0(m_axi_rdata[49]),
- .I1(\m_payload_i[33]_i_2_n_0 ),
- .I2(m_axi_rdata[113]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(m_axi_rdata[81]),
+ (.I0(m_axi_rdata[145]),
+ .I1(m_axi_rdata[113]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[20]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFF222))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[20]_i_3
+ (.I0(m_axi_rdata[81]),
+ .I1(m_axi_rdata[49]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[20]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[21]_i_1
- (.I0(\skid_buffer_reg_n_0_[21] ),
+ (.I0(\m_payload_i[21]_i_2_n_0 ),
.I1(aa_rready),
- .I2(m_axi_rdata[50]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(\m_payload_i[21]_i_2_n_0 ),
+ .I2(\skid_buffer_reg_n_0_[21] ),
+ .I3(m_axi_rdata[18]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[21]_i_3_n_0 ),
.O(skid_buffer[21]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[21]_i_2
- (.I0(\m_payload_i[32]_i_2_n_0 ),
- .I1(m_axi_rdata[82]),
- .I2(m_axi_rdata[18]),
- .I3(\m_payload_i[31]_i_2_n_0 ),
- .I4(m_axi_rdata[114]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[146]),
+ .I1(m_axi_rdata[114]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[21]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[21]_i_3
+ (.I0(m_axi_rdata[82]),
+ .I1(m_axi_rdata[50]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[21]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[22]_i_1
- (.I0(m_axi_rdata[19]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[22]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
- .I3(aa_rready),
- .I4(\m_payload_i[22]_i_2_n_0 ),
+ .I3(m_axi_rdata[19]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[22]_i_3_n_0 ),
.O(skid_buffer[22]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[22]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[51]),
- .I2(m_axi_rdata[83]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[115]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[147]),
+ .I1(m_axi_rdata[115]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[22]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFF222))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[22]_i_3
+ (.I0(m_axi_rdata[83]),
+ .I1(m_axi_rdata[51]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[22]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[23]_i_1
- (.I0(\skid_buffer_reg_n_0_[23] ),
+ (.I0(\m_payload_i[23]_i_2_n_0 ),
.I1(aa_rready),
- .I2(m_axi_rdata[84]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(\m_payload_i[23]_i_2_n_0 ),
+ .I2(\skid_buffer_reg_n_0_[23] ),
+ .I3(m_axi_rdata[20]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[23]_i_3_n_0 ),
.O(skid_buffer[23]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[23]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[52]),
- .I2(m_axi_rdata[20]),
- .I3(\m_payload_i[31]_i_2_n_0 ),
- .I4(m_axi_rdata[116]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[148]),
+ .I1(m_axi_rdata[116]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[23]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[23]_i_3
+ (.I0(m_axi_rdata[84]),
+ .I1(m_axi_rdata[52]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[23]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[24]_i_1
- (.I0(m_axi_rdata[21]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[24]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
- .I3(aa_rready),
- .I4(\m_payload_i[24]_i_2_n_0 ),
+ .I3(m_axi_rdata[21]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[24]_i_3_n_0 ),
.O(skid_buffer[24]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[24]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[53]),
- .I2(m_axi_rdata[85]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[117]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[149]),
+ .I1(m_axi_rdata[117]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[24]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[24]_i_3
+ (.I0(m_axi_rdata[85]),
+ .I1(m_axi_rdata[53]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[24]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[25]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[25] ),
- .I3(m_axi_rdata[86]),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(\m_payload_i[25]_i_2_n_0 ),
+ (.I0(\m_payload_i[25]_i_2_n_0 ),
+ .I1(m_axi_rdata[22]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[150]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[25]_i_3_n_0 ),
.O(skid_buffer[25]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[25]_i_2
- (.I0(\m_payload_i[34]_i_4_n_0 ),
- .I1(m_axi_rdata[118]),
- .I2(m_axi_rdata[54]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[22]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(m_axi_rdata[118]),
+ .I1(m_axi_rdata[86]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[25]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[25]_i_3
+ (.I0(\skid_buffer_reg_n_0_[25] ),
+ .I1(m_axi_rdata[54]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[25]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[26]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[26] ),
- .I3(m_axi_rdata[55]),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(\m_payload_i[26]_i_2_n_0 ),
+ (.I0(\m_payload_i[26]_i_2_n_0 ),
+ .I1(m_axi_rdata[23]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[151]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[26]_i_3_n_0 ),
.O(skid_buffer[26]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[26]_i_2
- (.I0(\m_payload_i[34]_i_4_n_0 ),
- .I1(m_axi_rdata[119]),
- .I2(m_axi_rdata[87]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[23]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(m_axi_rdata[119]),
+ .I1(m_axi_rdata[87]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[26]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[26]_i_3
+ (.I0(\skid_buffer_reg_n_0_[26] ),
+ .I1(m_axi_rdata[55]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[26]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[27]_i_1
- (.I0(m_axi_rdata[24]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[27]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
- .I3(aa_rready),
- .I4(\m_payload_i[27]_i_2_n_0 ),
+ .I3(m_axi_rdata[24]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[27]_i_3_n_0 ),
.O(skid_buffer[27]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[27]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[56]),
- .I2(m_axi_rdata[88]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[120]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[152]),
+ .I1(m_axi_rdata[120]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[27]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[27]_i_3
+ (.I0(m_axi_rdata[88]),
+ .I1(m_axi_rdata[56]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[27]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[28]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[28] ),
- .I3(m_axi_rdata[121]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[28]_i_2_n_0 ),
+ (.I0(\m_payload_i[28]_i_2_n_0 ),
+ .I1(m_axi_rdata[25]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[153]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[28]_i_3_n_0 ),
.O(skid_buffer[28]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[28]_i_2
- (.I0(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[121]),
.I1(m_axi_rdata[89]),
- .I2(m_axi_rdata[57]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[25]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[28]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[28]_i_3
+ (.I0(\skid_buffer_reg_n_0_[28] ),
+ .I1(m_axi_rdata[57]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[28]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[29]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[29] ),
- .I3(m_axi_rdata[58]),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(\m_payload_i[29]_i_2_n_0 ),
+ (.I0(\m_payload_i[29]_i_2_n_0 ),
+ .I1(m_axi_rdata[26]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[154]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[29]_i_3_n_0 ),
.O(skid_buffer[29]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[29]_i_2
- (.I0(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[122]),
.I1(m_axi_rdata[90]),
- .I2(m_axi_rdata[122]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(m_axi_rdata[26]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[29]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[29]_i_3
+ (.I0(\skid_buffer_reg_n_0_[29] ),
+ .I1(m_axi_rdata[58]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[29]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[2]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[2] ),
- .I3(m_axi_rresp[3]),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(\m_payload_i[2]_i_2_n_0 ),
+ (.I0(\m_payload_i[2]_i_2_n_0 ),
+ .I1(m_axi_rresp[1]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rresp[9]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[2]_i_3_n_0 ),
.O(skid_buffer[2]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[2]_i_2
- (.I0(\m_payload_i[31]_i_2_n_0 ),
- .I1(m_axi_rresp[1]),
- .I2(m_axi_rresp[5]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rresp[7]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rresp[7]),
+ .I1(m_axi_rresp[5]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[2]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[2]_i_3
+ (.I0(\skid_buffer_reg_n_0_[2] ),
+ .I1(m_axi_rresp[3]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[2]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[30]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[30] ),
- .I3(m_axi_rdata[123]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[30]_i_2_n_0 ),
+ (.I0(\m_payload_i[30]_i_2_n_0 ),
+ .I1(m_axi_rdata[27]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[155]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[30]_i_3_n_0 ),
.O(skid_buffer[30]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[30]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[59]),
- .I2(m_axi_rdata[91]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[27]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(m_axi_rdata[123]),
+ .I1(m_axi_rdata[91]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[30]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFF8FFF888))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[30]_i_3
+ (.I0(\skid_buffer_reg_n_0_[30] ),
+ .I1(m_axi_rdata[59]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[30]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[31]_i_1
- (.I0(m_axi_rdata[28]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
- .I2(\m_payload_i[34]_i_3_n_0 ),
- .I3(aa_rready),
- .I4(\skid_buffer_reg_n_0_[31] ),
+ (.I0(\m_payload_i[31]_i_2_n_0 ),
+ .I1(m_axi_rdata[28]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[156]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
.I5(\m_payload_i[31]_i_3_n_0 ),
.O(skid_buffer[31]));
- LUT4 #(
- .INIT(16'h0002))
+ LUT6 #(
+ .INIT(64'h0000AC0000000000))
\m_payload_i[31]_i_2
- (.I0(aa_rready),
- .I1(m_atarget_enc[2]),
- .I2(m_atarget_enc[1]),
- .I3(m_atarget_enc[0]),
+ (.I0(m_axi_rdata[124]),
+ .I1(m_axi_rdata[92]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[31]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h00F000C0AAAAAAAA))
\m_payload_i[31]_i_3
- (.I0(\m_payload_i[34]_i_4_n_0 ),
- .I1(m_axi_rdata[124]),
- .I2(m_axi_rdata[60]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[92]),
- .I5(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(\skid_buffer_reg_n_0_[31] ),
+ .I1(m_axi_rdata[60]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[31]_i_3_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFF222))
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[32]_i_1
- (.I0(\skid_buffer_reg_n_0_[32] ),
+ (.I0(\m_payload_i[32]_i_2_n_0 ),
.I1(aa_rready),
- .I2(m_axi_rdata[93]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(\m_payload_i[32]_i_3_n_0 ),
+ .I2(\skid_buffer_reg_n_0_[32] ),
+ .I3(m_axi_rdata[29]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[32]_i_3_n_0 ),
.O(skid_buffer[32]));
- LUT4 #(
- .INIT(16'h0020))
+ LUT6 #(
+ .INIT(64'h000AC00000000000))
\m_payload_i[32]_i_2
- (.I0(aa_rready),
- .I1(m_atarget_enc[2]),
- .I2(m_atarget_enc[1]),
- .I3(m_atarget_enc[0]),
+ (.I0(m_axi_rdata[157]),
+ .I1(m_axi_rdata[125]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[32]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h00000AC000000000))
\m_payload_i[32]_i_3
- (.I0(\m_payload_i[33]_i_2_n_0 ),
+ (.I0(m_axi_rdata[93]),
.I1(m_axi_rdata[61]),
- .I2(m_axi_rdata[29]),
- .I3(\m_payload_i[31]_i_2_n_0 ),
- .I4(m_axi_rdata[125]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[32]_i_3_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[33]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[33] ),
- .I3(m_axi_rdata[62]),
- .I4(\m_payload_i[33]_i_2_n_0 ),
+ (.I0(\m_payload_i[33]_i_2_n_0 ),
+ .I1(m_axi_rdata[30]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[158]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
.I5(\m_payload_i[33]_i_3_n_0 ),
.O(skid_buffer[33]));
- LUT4 #(
- .INIT(16'h0008))
+ LUT6 #(
+ .INIT(64'h0000AC0000000000))
\m_payload_i[33]_i_2
- (.I0(aa_rready),
- .I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[1]),
+ (.I0(m_axi_rdata[126]),
+ .I1(m_axi_rdata[94]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[33]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h00F000C0AAAAAAAA))
\m_payload_i[33]_i_3
- (.I0(\m_payload_i[32]_i_2_n_0 ),
- .I1(m_axi_rdata[94]),
- .I2(m_axi_rdata[126]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(m_axi_rdata[30]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\skid_buffer_reg_n_0_[33] ),
+ .I1(m_axi_rdata[62]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[33]_i_3_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[34]_i_2
(.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[34] ),
- .I3(m_axi_rdata[127]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[34]_i_5_n_0 ),
+ .I1(m_axi_rdata[31]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[159]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[34]_i_6_n_0 ),
.O(skid_buffer[34]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT3 #(
- .INIT(8'h04))
+ LUT6 #(
+ .INIT(64'h0000AC0000000000))
\m_payload_i[34]_i_3
- (.I0(m_atarget_enc[0]),
- .I1(m_atarget_enc[2]),
- .I2(m_atarget_enc[1]),
+ (.I0(m_axi_rdata[127]),
+ .I1(m_axi_rdata[95]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[34]_i_3_n_0 ));
LUT4 #(
- .INIT(16'h0800))
+ .INIT(16'h0100))
\m_payload_i[34]_i_4
- (.I0(aa_rready),
- .I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[2]),
- .I3(m_atarget_enc[1]),
+ (.I0(\m_payload_i_reg[0]_0 [0]),
+ .I1(\m_payload_i_reg[0]_0 [1]),
+ .I2(\m_payload_i_reg[0]_0 [2]),
+ .I3(aa_rready),
.O(\m_payload_i[34]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT4 #(
+ .INIT(16'h0400))
\m_payload_i[34]_i_5
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[63]),
- .I2(m_axi_rdata[95]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[31]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i_reg[0]_0 [0]),
+ .I1(\m_payload_i_reg[0]_0 [2]),
+ .I2(\m_payload_i_reg[0]_0 [1]),
+ .I3(aa_rready),
.O(\m_payload_i[34]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[34]_i_6
+ (.I0(\skid_buffer_reg_n_0_[34] ),
+ .I1(m_axi_rdata[63]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[34]_i_6_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[3]_i_1
- (.I0(m_axi_rdata[0]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[3]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
- .I3(aa_rready),
- .I4(\m_payload_i[3]_i_2_n_0 ),
+ .I3(m_axi_rdata[0]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[3]_i_3_n_0 ),
.O(skid_buffer[3]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[3]_i_2
- (.I0(m_axi_rdata[32]),
- .I1(\m_payload_i[33]_i_2_n_0 ),
- .I2(m_axi_rdata[96]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(m_axi_rdata[64]),
+ (.I0(m_axi_rdata[128]),
+ .I1(m_axi_rdata[96]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[3]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[3]_i_3
+ (.I0(m_axi_rdata[64]),
+ .I1(m_axi_rdata[32]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[3]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[4]_i_1
- (.I0(m_axi_rdata[1]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[4]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
- .I3(aa_rready),
- .I4(\m_payload_i[4]_i_2_n_0 ),
+ .I3(m_axi_rdata[1]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[4]_i_3_n_0 ),
.O(skid_buffer[4]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
- \m_payload_i[4]_i_2
+ .INIT(64'h000AC00000000000))
+ \m_payload_i[4]_i_2
+ (.I0(m_axi_rdata[129]),
+ .I1(m_axi_rdata[97]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[4]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[4]_i_3
(.I0(m_axi_rdata[65]),
- .I1(\m_payload_i[32]_i_2_n_0 ),
- .I2(m_axi_rdata[97]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(\m_payload_i[33]_i_2_n_0 ),
- .I5(m_axi_rdata[33]),
- .O(\m_payload_i[4]_i_2_n_0 ));
+ .I1(m_axi_rdata[33]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[4]_i_3_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[5]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[5] ),
- .I3(m_axi_rdata[66]),
- .I4(\m_payload_i[32]_i_2_n_0 ),
- .I5(\m_payload_i[5]_i_2_n_0 ),
+ (.I0(\m_payload_i[5]_i_2_n_0 ),
+ .I1(m_axi_rdata[2]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[130]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[5]_i_3_n_0 ),
.O(skid_buffer[5]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[5]_i_2
- (.I0(\m_payload_i[31]_i_2_n_0 ),
- .I1(m_axi_rdata[2]),
- .I2(m_axi_rdata[98]),
- .I3(\m_payload_i[34]_i_4_n_0 ),
- .I4(m_axi_rdata[34]),
- .I5(\m_payload_i[33]_i_2_n_0 ),
+ (.I0(m_axi_rdata[98]),
+ .I1(m_axi_rdata[66]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[5]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFFFB8B8B8))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[5]_i_3
+ (.I0(\skid_buffer_reg_n_0_[5] ),
+ .I1(m_axi_rdata[34]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[5]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[6]_i_1
- (.I0(\m_payload_i[34]_i_3_n_0 ),
- .I1(aa_rready),
- .I2(\skid_buffer_reg_n_0_[6] ),
- .I3(m_axi_rdata[99]),
- .I4(\m_payload_i[34]_i_4_n_0 ),
- .I5(\m_payload_i[6]_i_2_n_0 ),
+ (.I0(\m_payload_i[6]_i_2_n_0 ),
+ .I1(m_axi_rdata[3]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[131]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[6]_i_3_n_0 ),
.O(skid_buffer[6]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[6]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[35]),
- .I2(m_axi_rdata[67]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[3]),
- .I5(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(m_axi_rdata[99]),
+ .I1(m_axi_rdata[67]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[6]_i_2_n_0 ));
LUT6 #(
- .INIT(64'hFFFFFFFFF8FFF888))
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[6]_i_3
+ (.I0(\skid_buffer_reg_n_0_[6] ),
+ .I1(m_axi_rdata[35]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[6]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFEAEAEA))
\m_payload_i[7]_i_1
- (.I0(m_axi_rdata[4]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
- .I2(\m_payload_i[34]_i_3_n_0 ),
- .I3(aa_rready),
- .I4(\skid_buffer_reg_n_0_[7] ),
- .I5(\m_payload_i[7]_i_2_n_0 ),
+ (.I0(\m_payload_i[7]_i_2_n_0 ),
+ .I1(m_axi_rdata[4]),
+ .I2(\m_payload_i[34]_i_4_n_0 ),
+ .I3(m_axi_rdata[132]),
+ .I4(\m_payload_i[34]_i_5_n_0 ),
+ .I5(\m_payload_i[7]_i_3_n_0 ),
.O(skid_buffer[7]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h0000AC0000000000))
\m_payload_i[7]_i_2
- (.I0(\m_payload_i[34]_i_4_n_0 ),
- .I1(m_axi_rdata[100]),
- .I2(m_axi_rdata[36]),
- .I3(\m_payload_i[33]_i_2_n_0 ),
- .I4(m_axi_rdata[68]),
- .I5(\m_payload_i[32]_i_2_n_0 ),
+ (.I0(m_axi_rdata[100]),
+ .I1(m_axi_rdata[68]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[7]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF88F8))
+ LUT6 #(
+ .INIT(64'h00F000C0AAAAAAAA))
+ \m_payload_i[7]_i_3
+ (.I0(\skid_buffer_reg_n_0_[7] ),
+ .I1(m_axi_rdata[36]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[7]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[8]_i_1
- (.I0(m_axi_rdata[5]),
- .I1(\m_payload_i[31]_i_2_n_0 ),
+ (.I0(\m_payload_i[8]_i_2_n_0 ),
+ .I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
- .I3(aa_rready),
- .I4(\m_payload_i[8]_i_2_n_0 ),
+ .I3(m_axi_rdata[5]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[8]_i_3_n_0 ),
.O(skid_buffer[8]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[8]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[37]),
- .I2(m_axi_rdata[69]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(m_axi_rdata[101]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[133]),
+ .I1(m_axi_rdata[101]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[8]_i_2_n_0 ));
- LUT5 #(
- .INIT(32'hFFFFF222))
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[8]_i_3
+ (.I0(m_axi_rdata[69]),
+ .I1(m_axi_rdata[37]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[8]_i_3_n_0 ));
+ LUT6 #(
+ .INIT(64'hFFFFFFFFFFBABABA))
\m_payload_i[9]_i_1
- (.I0(\skid_buffer_reg_n_0_[9] ),
+ (.I0(\m_payload_i[9]_i_2_n_0 ),
.I1(aa_rready),
- .I2(m_axi_rdata[70]),
- .I3(\m_payload_i[32]_i_2_n_0 ),
- .I4(\m_payload_i[9]_i_2_n_0 ),
+ .I2(\skid_buffer_reg_n_0_[9] ),
+ .I3(m_axi_rdata[6]),
+ .I4(\m_payload_i[34]_i_4_n_0 ),
+ .I5(\m_payload_i[9]_i_3_n_0 ),
.O(skid_buffer[9]));
LUT6 #(
- .INIT(64'hFFFFF888F888F888))
+ .INIT(64'h000AC00000000000))
\m_payload_i[9]_i_2
- (.I0(\m_payload_i[33]_i_2_n_0 ),
- .I1(m_axi_rdata[38]),
- .I2(m_axi_rdata[6]),
- .I3(\m_payload_i[31]_i_2_n_0 ),
- .I4(m_axi_rdata[102]),
- .I5(\m_payload_i[34]_i_4_n_0 ),
+ (.I0(m_axi_rdata[134]),
+ .I1(m_axi_rdata[102]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
.O(\m_payload_i[9]_i_2_n_0 ));
+ LUT6 #(
+ .INIT(64'h00000AC000000000))
+ \m_payload_i[9]_i_3
+ (.I0(m_axi_rdata[70]),
+ .I1(m_axi_rdata[38]),
+ .I2(\m_payload_i_reg[0]_0 [0]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [2]),
+ .I5(aa_rready),
+ .O(\m_payload_i[9]_i_3_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
@@ -4091,40 +4471,32 @@ module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
- LUT6 #(
- .INIT(64'h000000007FFFFFFF))
- \m_ready_d[1]_i_3
- (.I0(sr_rvalid),
- .I1(Q[0]),
- .I2(s_axi_rready),
- .I3(aa_grant_rnw),
- .I4(m_valid_i),
- .I5(m_ready_d),
- .O(m_valid_i_reg_0));
- LUT6 #(
- .INIT(64'h00CA000F00CA0000))
+ LUT5 #(
+ .INIT(32'h0C0000A0))
m_valid_i_i_4
- (.I0(m_axi_rvalid[1]),
+ (.I0(m_axi_rvalid[3]),
.I1(m_axi_rvalid[2]),
- .I2(m_atarget_enc[0]),
- .I3(m_atarget_enc[2]),
- .I4(m_atarget_enc[1]),
- .I5(m_axi_rvalid[0]),
+ .I2(\m_payload_i_reg[0]_0 [2]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [0]),
+ .O(\m_axi_rvalid[4] ));
+ LUT5 #(
+ .INIT(32'h000C0A00))
+ m_valid_i_i_6
+ (.I0(m_axi_rvalid[1]),
+ .I1(m_axi_rvalid[0]),
+ .I2(\m_payload_i_reg[0]_0 [2]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
+ .I4(\m_payload_i_reg[0]_0 [0]),
.O(m_axi_rvalid_2_sn_1));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
- .D(m_valid_i_reg_1),
+ .D(m_valid_i_reg_0),
.Q(sr_rvalid),
.R(1'b0));
- LUT2 #(
- .INIT(4'h2))
- \s_axi_rvalid[0]_INST_0
- (.I0(sr_rvalid),
- .I1(p_0_in1_in),
- .O(s_axi_rvalid));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
@@ -4133,15 +4505,14 @@ module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
.D(s_ready_i_reg_0),
.Q(aa_rready),
.R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT5 #(
- .INIT(32'h03FFAAAA))
+ (* SOFT_HLUTNM = "soft_lutpair18" *)
+ LUT4 #(
+ .INIT(16'h2EEE))
\skid_buffer[0]_i_1
(.I0(\skid_buffer_reg_n_0_[0] ),
- .I1(m_atarget_enc[0]),
- .I2(m_atarget_enc[1]),
- .I3(m_atarget_enc[2]),
- .I4(aa_rready),
+ .I1(aa_rready),
+ .I2(\m_payload_i_reg[0]_0 [2]),
+ .I3(\m_payload_i_reg[0]_0 [1]),
.O(skid_buffer[0]));
FDRE \skid_buffer_reg[0]
(.C(aclk),
@@ -4354,6 +4725,299 @@ module mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
+
+(* CHECK_LICENSE_TYPE = "mb_design_1_xbar_0,axi_crossbar_v2_1_33_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_33_axi_crossbar,Vivado 2024.1.2" *)
+(* NotValidForBitStream *)
+module mb_design_1_xbar_0
+ (aclk,
+ aresetn,
+ s_axi_awaddr,
+ s_axi_awprot,
+ s_axi_awvalid,
+ s_axi_awready,
+ s_axi_wdata,
+ s_axi_wstrb,
+ s_axi_wvalid,
+ s_axi_wready,
+ s_axi_bresp,
+ s_axi_bvalid,
+ s_axi_bready,
+ s_axi_araddr,
+ s_axi_arprot,
+ s_axi_arvalid,
+ s_axi_arready,
+ s_axi_rdata,
+ s_axi_rresp,
+ s_axi_rvalid,
+ s_axi_rready,
+ m_axi_awaddr,
+ m_axi_awprot,
+ m_axi_awvalid,
+ m_axi_awready,
+ m_axi_wdata,
+ m_axi_wstrb,
+ m_axi_wvalid,
+ m_axi_wready,
+ m_axi_bresp,
+ m_axi_bvalid,
+ m_axi_bready,
+ m_axi_araddr,
+ m_axi_arprot,
+ m_axi_arvalid,
+ m_axi_arready,
+ m_axi_rdata,
+ m_axi_rresp,
+ m_axi_rvalid,
+ m_axi_rready);
+ (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input aclk;
+ (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *) input aresetn;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [0:0]s_axi_rready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128]" *) output [159:0]m_axi_awaddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12]" *) output [14:0]m_axi_awprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4]" *) output [4:0]m_axi_awvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4]" *) input [4:0]m_axi_awready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128]" *) output [159:0]m_axi_wdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16]" *) output [19:0]m_axi_wstrb;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4]" *) output [4:0]m_axi_wvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4]" *) input [4:0]m_axi_wready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8]" *) input [9:0]m_axi_bresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4]" *) input [4:0]m_axi_bvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4]" *) output [4:0]m_axi_bready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128]" *) output [159:0]m_axi_araddr;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12]" *) output [14:0]m_axi_arprot;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4]" *) output [4:0]m_axi_arvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4]" *) input [4:0]m_axi_arready;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128]" *) input [159:0]m_axi_rdata;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8]" *) input [9:0]m_axi_rresp;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4]" *) input [4:0]m_axi_rvalid;
+ (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [4:0]m_axi_rready;
+
+ wire aclk;
+ wire aresetn;
+ wire [159:0]m_axi_araddr;
+ wire [14:0]m_axi_arprot;
+ wire [4:0]m_axi_arready;
+ wire [4:0]m_axi_arvalid;
+ wire [159:0]m_axi_awaddr;
+ wire [14:0]m_axi_awprot;
+ wire [4:0]m_axi_awready;
+ wire [4:0]m_axi_awvalid;
+ wire [4:0]m_axi_bready;
+ wire [9:0]m_axi_bresp;
+ wire [4:0]m_axi_bvalid;
+ wire [159:0]m_axi_rdata;
+ wire [4:0]m_axi_rready;
+ wire [9:0]m_axi_rresp;
+ wire [4:0]m_axi_rvalid;
+ wire [159:0]m_axi_wdata;
+ wire [4:0]m_axi_wready;
+ wire [19:0]m_axi_wstrb;
+ wire [4:0]m_axi_wvalid;
+ wire [31:0]s_axi_araddr;
+ wire [2:0]s_axi_arprot;
+ wire [0:0]s_axi_arready;
+ wire [0:0]s_axi_arvalid;
+ wire [31:0]s_axi_awaddr;
+ wire [2:0]s_axi_awprot;
+ wire [0:0]s_axi_awready;
+ wire [0:0]s_axi_awvalid;
+ wire [0:0]s_axi_bready;
+ wire [1:0]s_axi_bresp;
+ wire [0:0]s_axi_bvalid;
+ wire [31:0]s_axi_rdata;
+ wire [0:0]s_axi_rready;
+ wire [1:0]s_axi_rresp;
+ wire [0:0]s_axi_rvalid;
+ wire [31:0]s_axi_wdata;
+ wire [0:0]s_axi_wready;
+ wire [3:0]s_axi_wstrb;
+ wire [0:0]s_axi_wvalid;
+ wire [9:0]NLW_inst_m_axi_arburst_UNCONNECTED;
+ wire [19:0]NLW_inst_m_axi_arcache_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_arid_UNCONNECTED;
+ wire [39:0]NLW_inst_m_axi_arlen_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_arlock_UNCONNECTED;
+ wire [19:0]NLW_inst_m_axi_arqos_UNCONNECTED;
+ wire [19:0]NLW_inst_m_axi_arregion_UNCONNECTED;
+ wire [14:0]NLW_inst_m_axi_arsize_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_aruser_UNCONNECTED;
+ wire [9:0]NLW_inst_m_axi_awburst_UNCONNECTED;
+ wire [19:0]NLW_inst_m_axi_awcache_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_awid_UNCONNECTED;
+ wire [39:0]NLW_inst_m_axi_awlen_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_awlock_UNCONNECTED;
+ wire [19:0]NLW_inst_m_axi_awqos_UNCONNECTED;
+ wire [19:0]NLW_inst_m_axi_awregion_UNCONNECTED;
+ wire [14:0]NLW_inst_m_axi_awsize_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_awuser_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_wid_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_wlast_UNCONNECTED;
+ wire [4:0]NLW_inst_m_axi_wuser_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
+ wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
+
+ (* C_AXI_ADDR_WIDTH = "32" *)
+ (* C_AXI_ARUSER_WIDTH = "1" *)
+ (* C_AXI_AWUSER_WIDTH = "1" *)
+ (* C_AXI_BUSER_WIDTH = "1" *)
+ (* C_AXI_DATA_WIDTH = "32" *)
+ (* C_AXI_ID_WIDTH = "1" *)
+ (* C_AXI_PROTOCOL = "2" *)
+ (* C_AXI_RUSER_WIDTH = "1" *)
+ (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
+ (* C_AXI_WUSER_WIDTH = "1" *)
+ (* C_CONNECTIVITY_MODE = "0" *)
+ (* C_DEBUG = "1" *)
+ (* C_FAMILY = "artix7" *)
+ (* C_M_AXI_ADDR_WIDTH = "160'b0000000000000000000000000000011100000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100" *)
+ (* C_M_AXI_BASE_ADDR = "320'b00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000" *)
+ (* C_M_AXI_READ_CONNECTIVITY = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
+ (* C_M_AXI_READ_ISSUING = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
+ (* C_M_AXI_SECURE = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
+ (* C_M_AXI_WRITE_CONNECTIVITY = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
+ (* C_M_AXI_WRITE_ISSUING = "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
+ (* C_NUM_ADDR_RANGES = "1" *)
+ (* C_NUM_MASTER_SLOTS = "5" *)
+ (* C_NUM_SLAVE_SLOTS = "1" *)
+ (* C_R_REGISTER = "1" *)
+ (* C_S_AXI_ARB_PRIORITY = "0" *)
+ (* C_S_AXI_BASE_ID = "0" *)
+ (* C_S_AXI_READ_ACCEPTANCE = "1" *)
+ (* C_S_AXI_SINGLE_THREAD = "1" *)
+ (* C_S_AXI_THREAD_ID_WIDTH = "0" *)
+ (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
+ (* DowngradeIPIdentifiedWarnings = "yes" *)
+ (* P_ADDR_DECODE = "1" *)
+ (* P_AXI3 = "1" *)
+ (* P_AXI4 = "0" *)
+ (* P_AXILITE = "2" *)
+ (* P_AXILITE_SIZE = "3'b010" *)
+ (* P_FAMILY = "artix7" *)
+ (* P_INCR = "2'b01" *)
+ (* P_LEN = "8" *)
+ (* P_LOCK = "1" *)
+ (* P_M_AXI_ERR_MODE = "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
+ (* P_M_AXI_SUPPORTS_READ = "5'b11111" *)
+ (* P_M_AXI_SUPPORTS_WRITE = "5'b11111" *)
+ (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
+ (* P_RANGE_CHECK = "1" *)
+ (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
+ (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
+ (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
+ (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
+ mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar inst
+ (.aclk(aclk),
+ .aresetn(aresetn),
+ .m_axi_araddr(m_axi_araddr),
+ .m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[9:0]),
+ .m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[19:0]),
+ .m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[4:0]),
+ .m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[39:0]),
+ .m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[4:0]),
+ .m_axi_arprot(m_axi_arprot),
+ .m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[19:0]),
+ .m_axi_arready(m_axi_arready),
+ .m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[19:0]),
+ .m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[14:0]),
+ .m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[4:0]),
+ .m_axi_arvalid(m_axi_arvalid),
+ .m_axi_awaddr(m_axi_awaddr),
+ .m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[9:0]),
+ .m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[19:0]),
+ .m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[4:0]),
+ .m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[39:0]),
+ .m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[4:0]),
+ .m_axi_awprot(m_axi_awprot),
+ .m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[19:0]),
+ .m_axi_awready(m_axi_awready),
+ .m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[19:0]),
+ .m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[14:0]),
+ .m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[4:0]),
+ .m_axi_awvalid(m_axi_awvalid),
+ .m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .m_axi_bready(m_axi_bready),
+ .m_axi_bresp(m_axi_bresp),
+ .m_axi_buser({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .m_axi_bvalid(m_axi_bvalid),
+ .m_axi_rdata(m_axi_rdata),
+ .m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .m_axi_rlast({1'b1,1'b1,1'b1,1'b1,1'b1}),
+ .m_axi_rready(m_axi_rready),
+ .m_axi_rresp(m_axi_rresp),
+ .m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .m_axi_rvalid(m_axi_rvalid),
+ .m_axi_wdata(m_axi_wdata),
+ .m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[4:0]),
+ .m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[4:0]),
+ .m_axi_wready(m_axi_wready),
+ .m_axi_wstrb(m_axi_wstrb),
+ .m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[4:0]),
+ .m_axi_wvalid(m_axi_wvalid),
+ .s_axi_araddr(s_axi_araddr),
+ .s_axi_arburst({1'b0,1'b0}),
+ .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arid(1'b0),
+ .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arlock(1'b0),
+ .s_axi_arprot(s_axi_arprot),
+ .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_arready(s_axi_arready),
+ .s_axi_arsize({1'b0,1'b0,1'b0}),
+ .s_axi_aruser(1'b0),
+ .s_axi_arvalid(s_axi_arvalid),
+ .s_axi_awaddr(s_axi_awaddr),
+ .s_axi_awburst({1'b0,1'b0}),
+ .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awid(1'b0),
+ .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awlock(1'b0),
+ .s_axi_awprot(s_axi_awprot),
+ .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
+ .s_axi_awready(s_axi_awready),
+ .s_axi_awsize({1'b0,1'b0,1'b0}),
+ .s_axi_awuser(1'b0),
+ .s_axi_awvalid(s_axi_awvalid),
+ .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
+ .s_axi_bready(s_axi_bready),
+ .s_axi_bresp(s_axi_bresp),
+ .s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
+ .s_axi_bvalid(s_axi_bvalid),
+ .s_axi_rdata(s_axi_rdata),
+ .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
+ .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
+ .s_axi_rready(s_axi_rready),
+ .s_axi_rresp(s_axi_rresp),
+ .s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
+ .s_axi_rvalid(s_axi_rvalid),
+ .s_axi_wdata(s_axi_wdata),
+ .s_axi_wid(1'b0),
+ .s_axi_wlast(1'b1),
+ .s_axi_wready(s_axi_wready),
+ .s_axi_wstrb(s_axi_wstrb),
+ .s_axi_wuser(1'b0),
+ .s_axi_wvalid(s_axi_wvalid));
+endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.vhdl
index 4ba4bd81e16c744d3f5ad131653370abc3d2574b..fd19cd9903cd06cbb28c410b94ef1bb6928ebcee 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.vhdl
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.vhdl
@@ -2,10 +2,10 @@
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--- Date : Tue Mar 4 22:38:42 2025
+-- Date : Thu Mar 20 17:31:25 2025
-- Host : hogtest running 64-bit unknown
--- Command : write_vhdl -force -mode funcsim
--- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_sim_netlist.vhdl
+-- Command : write_vhdl -force -mode funcsim -rename_top mb_design_1_xbar_0 -prefix
+-- mb_design_1_xbar_0_ mb_design_1_xbar_0_sim_netlist.vhdl
-- Design : mb_design_1_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -17,62 +17,57 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd is
port (
- p_0_in1_in : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
- aresetn_d_reg : out STD_LOGIC;
- D : out STD_LOGIC_VECTOR ( 3 downto 0 );
- aresetn_d_reg_0 : out STD_LOGIC;
- aresetn_d_reg_1 : out STD_LOGIC;
- \gen_no_arbiter.m_amesg_i_reg[19]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
- Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
- m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
- s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_wvalid_0_sp_1 : out STD_LOGIC;
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_bready_0_sp_1 : out STD_LOGIC;
- \gen_no_arbiter.grant_rnw_reg_0\ : out STD_LOGIC;
+ s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ \gen_no_arbiter.grant_rnw_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ \gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : out STD_LOGIC;
- \aresetn_d_reg[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
- m_ready_d0_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
- \m_ready_d_reg[1]\ : out STD_LOGIC;
- \gen_no_arbiter.grant_rnw_reg_1\ : out STD_LOGIC;
+ \aresetn_d_reg[1]\ : out STD_LOGIC;
+ m_ready_d0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ mi_arvalid_en : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
- \gen_axilite.s_axi_awready_i_reg\ : out STD_LOGIC;
- \m_ready_d_reg[2]\ : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
+ D : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
+ \gen_no_arbiter.m_amesg_i_reg[48]_0\ : out STD_LOGIC_VECTOR ( 34 downto 0 );
+ \m_atarget_hot_reg[5]\ : out STD_LOGIC;
+ \gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC;
aclk : in STD_LOGIC;
- aresetn_d : in STD_LOGIC;
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\ : in STD_LOGIC;
+ m_ready_d0_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
- \gen_no_arbiter.m_valid_i_reg_0\ : in STD_LOGIC;
+ aresetn_d : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_wready_0_sp_1 : in STD_LOGIC;
- \gen_axilite.s_axi_bvalid_i_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0\ : in STD_LOGIC;
- s_axi_bvalid_0_sp_1 : in STD_LOGIC;
+ \f_mux_return__3\ : in STD_LOGIC;
+ \f_mux_return__1\ : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
- \m_ready_d[2]_i_3\ : in STD_LOGIC;
- \m_ready_d[2]_i_3_0\ : in STD_LOGIC;
+ \gen_no_arbiter.m_valid_i_reg_1\ : in STD_LOGIC;
+ \gen_no_arbiter.m_valid_i_reg_2\ : in STD_LOGIC;
+ \gen_no_arbiter.m_valid_i_reg_3\ : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
- aa_rready : in STD_LOGIC;
- m_ready_d_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
+ m_valid_i_reg_2 : in STD_LOGIC;
+ aa_rready : in STD_LOGIC;
+ m_ready_d_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
+ \m_ready_d_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1\ : in STD_LOGIC;
- m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
- m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ \m_ready_d_reg[1]_2\ : in STD_LOGIC;
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -80,159 +75,173 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd is
mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_33_addr_arbiter_sasd";
end mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd;
architecture STRUCTURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd is
- signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
+ signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aa_grant_rnw\ : STD_LOGIC;
- signal \gen_axilite.s_axi_bvalid_i_i_2_n_0\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\ : STD_LOGIC;
+ signal \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
- signal \^gen_no_arbiter.grant_rnw_reg_0\ : STD_LOGIC;
+ signal \^gen_no_arbiter.m_amesg_i_reg[48]_0\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\ : STD_LOGIC;
- signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_10_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_2_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_5_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_6_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_7_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_8_n_0\ : STD_LOGIC;
- signal \m_atarget_hot[4]_i_9_n_0\ : STD_LOGIC;
- signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[2]_i_3_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[3]_i_3_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_12_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_13_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_14_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_15_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_16_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_2_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_6_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_8_n_0\ : STD_LOGIC;
+ signal \m_atarget_hot[5]_i_9_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
- signal m_valid_i_i_3_n_0 : STD_LOGIC;
- signal \^p_0_in1_in\ : STD_LOGIC;
+ signal mi_awvalid_en : STD_LOGIC;
+ signal p_0_in1_in : STD_LOGIC;
+ signal p_3_in : STD_LOGIC;
+ signal p_4_in : STD_LOGIC;
+ signal r_transfer_en : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
- signal s_axi_bready_0_sn_1 : STD_LOGIC;
- signal s_axi_bvalid_0_sn_1 : STD_LOGIC;
- signal s_axi_wready_0_sn_1 : STD_LOGIC;
- signal s_axi_wvalid_0_sn_1 : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
- signal target_mi_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal target_mi_enc : STD_LOGIC_VECTOR ( 2 to 2 );
attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \gen_axilite.s_axi_awready_i_i_2\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair5";
+ attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_3\ : label is "soft_lutpair6";
+ attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_4\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\ : label is "soft_lutpair3";
attribute inverted : string;
attribute inverted of \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : label is "yes";
- attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair11";
- attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \m_atarget_enc[2]_i_1\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair13";
- attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair14";
- attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair6";
- attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair9";
- attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair10";
- attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair8";
- attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair3";
+ attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \m_atarget_enc[2]_i_1\ : label is "soft_lutpair1";
+ attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair17";
+ attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_3\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \m_atarget_hot[4]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_1\ : label is "soft_lutpair2";
+ attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_16\ : label is "soft_lutpair7";
+ attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair13";
+ attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair14";
+ attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair9";
+ attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair10";
+ attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair11";
+ attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_bready[0]_INST_0\ : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair5";
- attribute SOFT_HLUTNM of \m_ready_d[0]_i_2__0\ : label is "soft_lutpair4";
- attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair3";
- attribute SOFT_HLUTNM of \m_ready_d[1]_i_2__0\ : label is "soft_lutpair1";
- attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair12";
- attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair0";
- attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair7";
- attribute SOFT_HLUTNM of \s_axi_arready[0]_INST_0\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair15";
- attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair2";
- attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair12";
+ attribute SOFT_HLUTNM of \m_ready_d[2]_i_9\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair15";
+ attribute SOFT_HLUTNM of m_valid_i_i_3 : label is "soft_lutpair0";
+ attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair8";
+ attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0\ : label is "soft_lutpair4";
+ attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair15";
begin
- Q(34 downto 0) <= \^q\(34 downto 0);
+ E(0) <= \^e\(0);
SR(0) <= \^sr\(0);
aa_grant_rnw <= \^aa_grant_rnw\;
- \gen_no_arbiter.grant_rnw_reg_0\ <= \^gen_no_arbiter.grant_rnw_reg_0\;
- m_ready_d0(0) <= \^m_ready_d0\(0);
+ \gen_no_arbiter.m_amesg_i_reg[48]_0\(34 downto 0) <= \^gen_no_arbiter.m_amesg_i_reg[48]_0\(34 downto 0);
m_valid_i <= \^m_valid_i\;
- p_0_in1_in <= \^p_0_in1_in\;
- s_axi_bready_0_sp_1 <= s_axi_bready_0_sn_1;
- s_axi_bvalid_0_sn_1 <= s_axi_bvalid_0_sp_1;
- s_axi_wready_0_sn_1 <= s_axi_wready_0_sp_1;
- s_axi_wvalid_0_sp_1 <= s_axi_wvalid_0_sn_1;
-\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
+\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
- INIT => X"FFEFFFFF00100000"
+ INIT => X"DFFF2000"
)
port map (
- I0 => \^gen_no_arbiter.grant_rnw_reg_0\,
- I1 => m_ready_d(2),
- I2 => \gen_axilite.s_axi_bvalid_i_reg\(3),
- I3 => mi_bvalid(0),
- I4 => s_axi_wvalid_0_sn_1,
- I5 => mi_wready(0),
- O => \m_ready_d_reg[2]\
+ I0 => p_4_in,
+ I1 => mi_bvalid(0),
+ I2 => Q(5),
+ I3 => mi_awvalid_en,
+ I4 => mi_wready(0),
+ O => \gen_axilite.s_axi_bvalid_i_reg\
);
-\gen_axilite.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
+\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"B"
+ INIT => X"5F5FC0005F5F0000"
)
port map (
- I0 => \^aa_grant_rnw\,
- I1 => \^m_valid_i\,
- O => \^gen_no_arbiter.grant_rnw_reg_0\
+ I0 => p_3_in,
+ I1 => p_4_in,
+ I2 => Q(5),
+ I3 => mi_wready(0),
+ I4 => mi_bvalid(0),
+ I5 => mi_awvalid_en,
+ O => \m_atarget_hot_reg[5]\
);
-\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
+\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0008FF00FF08FF00"
+ INIT => X"0400"
)
port map (
- I0 => mi_wready(0),
- I1 => s_axi_wvalid_0_sn_1,
- I2 => \gen_axilite.s_axi_bvalid_i_i_2_n_0\,
- I3 => mi_bvalid(0),
- I4 => \gen_axilite.s_axi_bvalid_i_reg\(3),
- I5 => s_axi_bready_0_sn_1,
- O => \gen_axilite.s_axi_awready_i_reg\
+ I0 => m_ready_d(0),
+ I1 => s_axi_bready(0),
+ I2 => \^aa_grant_rnw\,
+ I3 => \^m_valid_i\,
+ O => p_3_in
);
-\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT3
+\gen_axilite.s_axi_bvalid_i_i_3\: unisim.vcomponents.LUT4
generic map(
- INIT => X"FB"
+ INIT => X"0400"
)
port map (
- I0 => m_ready_d(2),
- I1 => \^m_valid_i\,
+ I0 => m_ready_d(1),
+ I1 => s_axi_wvalid(0),
I2 => \^aa_grant_rnw\,
- O => \gen_axilite.s_axi_bvalid_i_i_2_n_0\
+ I3 => \^m_valid_i\,
+ O => p_4_in
+ );
+\gen_axilite.s_axi_bvalid_i_i_4\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"04"
+ )
+ port map (
+ I0 => \^aa_grant_rnw\,
+ I1 => \^m_valid_i\,
+ I2 => m_ready_d(2),
+ O => mi_awvalid_en
);
\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
- INIT => X"40"
+ INIT => X"08"
)
port map (
- I0 => m_ready_d_1(1),
+ I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
- I2 => \^aa_grant_rnw\,
- O => \m_ready_d_reg[1]\
+ I2 => m_ready_d_1(1),
+ O => mi_arvalid_en
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF53FF00005000"
+ INIT => X"DFCFDFFF10001000"
)
port map (
I0 => s_awvalid_reg,
- I1 => s_axi_awvalid(0),
- I2 => s_axi_arvalid(0),
- I3 => \^p_0_in1_in\,
- I4 => \^m_valid_i\,
+ I1 => \^m_valid_i\,
+ I2 => p_0_in1_in,
+ I3 => s_axi_arvalid(0),
+ I4 => s_axi_awvalid(0),
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
@@ -640,332 +649,319 @@ begin
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(10),
- Q => \^q\(9),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(11),
- Q => \^q\(10),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(12),
- Q => \^q\(11),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(13),
- Q => \^q\(12),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(14),
- Q => \^q\(13),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(15),
- Q => \^q\(14),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(16),
- Q => \^q\(15),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(17),
- Q => \^q\(16),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(18),
- Q => \^q\(17),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(19),
- Q => \^q\(18),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(1),
- Q => \^q\(0),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(20),
- Q => \^q\(19),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(21),
- Q => \^q\(20),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(22),
- Q => \^q\(21),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(23),
- Q => \^q\(22),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(24),
- Q => \^q\(23),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(25),
- Q => \^q\(24),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(26),
- Q => \^q\(25),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(27),
- Q => \^q\(26),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(28),
- Q => \^q\(27),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(29),
- Q => \^q\(28),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(2),
- Q => \^q\(1),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(30),
- Q => \^q\(29),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(31),
- Q => \^q\(30),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(32),
- Q => \^q\(31),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(3),
- Q => \^q\(2),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(46),
- Q => \^q\(32),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(47),
- Q => \^q\(33),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(48),
- Q => \^q\(34),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(4),
- Q => \^q\(3),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(5),
- Q => \^q\(4),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(6),
- Q => \^q\(5),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(7),
- Q => \^q\(6),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(8),
- Q => \^q\(7),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
- CE => \^p_0_in1_in\,
+ CE => p_0_in1_in,
D => s_amesg(9),
- Q => \^q\(8),
+ Q => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_inv_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FF555755FFFFFFFF"
+ INIT => X"DDD5D5D5D5D5D5D5"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\,
- I1 => s_axi_awvalid(0),
- I2 => s_axi_arvalid(0),
- I3 => \^p_0_in1_in\,
- I4 => \^m_valid_i\,
- I5 => aresetn_d,
+ I1 => \^m_valid_i\,
+ I2 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\,
+ I3 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\,
+ I4 => m_ready_d0_0(0),
+ I5 => m_ready_d0_0(1),
O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\
);
-\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\: unisim.vcomponents.LUT6
+\gen_no_arbiter.m_grant_hot_i[0]_inv_i_2\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00EFFFFFFFEFFFFF"
+ INIT => X"0FEF0000"
)
port map (
- I0 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\,
- I1 => \gen_no_arbiter.m_valid_i_reg_0\,
- I2 => \^m_ready_d0\(0),
- I3 => \^aa_grant_rnw\,
- I4 => \^m_valid_i\,
- I5 => \m_ready_d[0]_i_4_n_0\,
+ I0 => s_axi_awvalid(0),
+ I1 => s_axi_arvalid(0),
+ I2 => p_0_in1_in,
+ I3 => \^m_valid_i\,
+ I4 => aresetn_d,
O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\
);
-\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\: unisim.vcomponents.LUT6
+\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00000000FF2FFFFF"
+ INIT => X"00000000FFFEAAAA"
)
port map (
- I0 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\,
- I1 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0\,
- I2 => s_axi_wvalid(0),
- I3 => \^aa_grant_rnw\,
+ I0 => m_ready_d(2),
+ I1 => \gen_no_arbiter.m_valid_i_reg_1\,
+ I2 => \gen_no_arbiter.m_valid_i_reg_2\,
+ I3 => \gen_no_arbiter.m_valid_i_reg_3\,
I4 => \^m_valid_i\,
- I5 => m_ready_d(1),
- O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_3_n_0\
- );
-\gen_no_arbiter.m_grant_hot_i[0]_inv_i_4\: unisim.vcomponents.LUT5
- generic map(
- INIT => X"F3F7FFF7"
- )
- port map (
- I0 => m_axi_wready(0),
- I1 => m_atarget_enc(1),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(0),
- I4 => m_axi_wready(1),
+ I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]_inv\: unisim.vcomponents.FDRE
@@ -976,17 +972,20 @@ begin
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_1_n_0\,
- Q => \^p_0_in1_in\,
+ Q => p_0_in1_in,
R => '0'
);
-\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
+\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"B1"
+ INIT => X"111D1D1D1D1D1D1D"
)
port map (
- I0 => \^m_valid_i\,
- I1 => \^p_0_in1_in\,
- I2 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_n_0\,
+ I0 => p_0_in1_in,
+ I1 => \^m_valid_i\,
+ I2 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\,
+ I3 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_4_n_0\,
+ I4 => m_ready_d0_0(0),
+ I5 => m_ready_d0_0(1),
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
@@ -1006,7 +1005,7 @@ begin
)
port map (
I0 => \^m_valid_i\,
- I1 => \^p_0_in1_in\,
+ I1 => p_0_in1_in,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
@@ -1021,449 +1020,645 @@ begin
Q => s_ready_i,
R => '0'
);
-\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT2
+\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"8"
+ INIT => X"AAAAAAAAAA00AA02"
)
port map (
- I0 => target_mi_enc(0),
- I1 => aresetn_d,
- O => aresetn_d_reg_0
+ I0 => aresetn_d,
+ I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
+ I2 => target_mi_enc(2),
+ I3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
+ I4 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
+ I5 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
+ O => D(0)
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
- I0 => target_mi_enc(1),
- I1 => aresetn_d,
- O => aresetn_d_reg_1
+ I0 => aresetn_d,
+ I1 => \m_atarget_hot[5]_i_2_n_0\,
+ O => D(1)
);
-\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT3
+\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT5
generic map(
- INIT => X"02"
+ INIT => X"CCCD0000"
)
port map (
- I0 => \m_atarget_hot[4]_i_2_n_0\,
- I1 => target_mi_enc(1),
- I2 => target_mi_enc(0),
- O => \gen_no_arbiter.m_amesg_i_reg[19]_0\(0)
+ I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
+ I1 => target_mi_enc(2),
+ I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
+ I3 => \m_atarget_hot[5]_i_2_n_0\,
+ I4 => aresetn_d,
+ O => D(2)
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT2
generic map(
- INIT => X"1"
+ INIT => X"2"
)
port map (
- I0 => \^p_0_in1_in\,
- I1 => \m_atarget_hot[4]_i_2_n_0\,
- O => D(0)
+ I0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
+ I1 => p_0_in1_in,
+ O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT2
generic map(
- INIT => X"2"
+ INIT => X"4"
)
port map (
- I0 => target_mi_enc(0),
- I1 => \^p_0_in1_in\,
- O => D(1)
+ I0 => p_0_in1_in,
+ I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
+ O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(1)
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT2
generic map(
- INIT => X"2"
+ INIT => X"4"
)
port map (
- I0 => target_mi_enc(1),
- I1 => \^p_0_in1_in\,
- O => D(2)
+ I0 => p_0_in1_in,
+ I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
+ O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(2)
+ );
+\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"8000000000000000"
+ )
+ port map (
+ I0 => \m_atarget_hot[5]_i_9_n_0\,
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
+ I3 => \m_atarget_hot[2]_i_3_n_0\,
+ I4 => \m_atarget_hot[5]_i_15_n_0\,
+ I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
+ O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\
);
-\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT4
+\m_atarget_hot[2]_i_3\: unisim.vcomponents.LUT2
generic map(
- INIT => X"0002"
+ INIT => X"2"
)
port map (
- I0 => \m_atarget_hot[4]_i_2_n_0\,
- I1 => target_mi_enc(1),
- I2 => target_mi_enc(0),
- I3 => \^p_0_in1_in\,
- O => D(3)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
+ O => \m_atarget_hot[2]_i_3_n_0\
);
-\m_atarget_hot[4]_i_10\: unisim.vcomponents.LUT6
+\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT2
generic map(
- INIT => X"FFFFFFFFFFFFFFFE"
+ INIT => X"4"
)
port map (
- I0 => \^q\(22),
- I1 => \^q\(23),
- I2 => \^q\(25),
- I3 => \^q\(24),
- I4 => \^q\(21),
- I5 => \^q\(20),
- O => \m_atarget_hot[4]_i_10_n_0\
+ I0 => p_0_in1_in,
+ I1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
+ O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(3)
);
-\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT4
+\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FEFF"
+ INIT => X"0080000000000000"
)
port map (
- I0 => \m_atarget_hot[4]_i_5_n_0\,
- I1 => \m_atarget_hot[4]_i_6_n_0\,
- I2 => \m_atarget_hot[4]_i_7_n_0\,
- I3 => \m_atarget_hot[4]_i_8_n_0\,
- O => \m_atarget_hot[4]_i_2_n_0\
+ I0 => \m_atarget_hot[5]_i_9_n_0\,
+ I1 => \m_atarget_hot[3]_i_3_n_0\,
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
+ I4 => \m_atarget_hot[5]_i_15_n_0\,
+ I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
+ O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\
);
-\m_atarget_hot[4]_i_3\: unisim.vcomponents.LUT6
+\m_atarget_hot[3]_i_3\: unisim.vcomponents.LUT2
generic map(
- INIT => X"0000000000000002"
+ INIT => X"2"
)
port map (
- I0 => \m_atarget_hot[4]_i_8_n_0\,
- I1 => \m_atarget_hot[4]_i_9_n_0\,
- I2 => \^q\(18),
- I3 => \^q\(17),
- I4 => \^q\(19),
- I5 => \^q\(16),
- O => target_mi_enc(1)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
+ O => \m_atarget_hot[3]_i_3_n_0\
);
-\m_atarget_hot[4]_i_4\: unisim.vcomponents.LUT6
+\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT2
generic map(
- INIT => X"0000000000000002"
+ INIT => X"4"
)
port map (
- I0 => \m_atarget_hot[4]_i_8_n_0\,
- I1 => \m_atarget_hot[4]_i_10_n_0\,
- I2 => \^q\(18),
- I3 => \^q\(17),
- I4 => \^q\(19),
- I5 => \^q\(16),
- O => target_mi_enc(0)
+ I0 => p_0_in1_in,
+ I1 => target_mi_enc(2),
+ O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(4)
);
-\m_atarget_hot[4]_i_5\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT5
generic map(
- INIT => X"FFFE"
+ INIT => X"00000001"
)
port map (
- I0 => \^q\(18),
- I1 => \^q\(17),
- I2 => \^q\(19),
- I3 => \^q\(16),
- O => \m_atarget_hot[4]_i_5_n_0\
+ I0 => p_0_in1_in,
+ I1 => \m_atarget_hot[5]_i_2_n_0\,
+ I2 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
+ I3 => target_mi_enc(2),
+ I4 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
+ O => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(5)
);
-\m_atarget_hot[4]_i_6\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_10\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFEF"
+ INIT => X"0000000000000001"
)
port map (
- I0 => \^q\(13),
- I1 => \^q\(15),
- I2 => \^q\(22),
- I3 => \^q\(14),
- O => \m_atarget_hot[4]_i_6_n_0\
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
+ I4 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(20),
+ I5 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(25),
+ O => \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
-\m_atarget_hot[4]_i_7\: unisim.vcomponents.LUT6
+\m_atarget_hot[5]_i_11\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFFFFFFD"
+ INIT => X"0000000000000001"
)
port map (
- I0 => \^q\(24),
- I1 => \^q\(25),
- I2 => \^q\(23),
- I3 => \^q\(12),
- I4 => \^q\(21),
- I5 => \^q\(20),
- O => \m_atarget_hot[4]_i_7_n_0\
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(15),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(14),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(18),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(19),
+ I4 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(16),
+ I5 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(17),
+ O => \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\
);
-\m_atarget_hot[4]_i_8\: unisim.vcomponents.LUT6
+\m_atarget_hot[5]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
- I0 => \^q\(27),
- I1 => \^q\(28),
- I2 => \^q\(31),
- I3 => \^q\(26),
- I4 => \^q\(29),
- I5 => \^q\(30),
- O => \m_atarget_hot[4]_i_8_n_0\
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(26),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(27),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(28),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(29),
+ I4 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(30),
+ I5 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(31),
+ O => \m_atarget_hot[5]_i_12_n_0\
);
-\m_atarget_hot[4]_i_9\: unisim.vcomponents.LUT6
+\m_atarget_hot[5]_i_13\: unisim.vcomponents.LUT3
generic map(
- INIT => X"FFFFFFFFFFFFFDFF"
+ INIT => X"01"
)
port map (
- I0 => \^q\(24),
- I1 => \^q\(25),
- I2 => \^q\(20),
- I3 => \^q\(21),
- I4 => \^q\(23),
- I5 => \^q\(22),
- O => \m_atarget_hot[4]_i_9_n_0\
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(9),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(8),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(7),
+ O => \m_atarget_hot[5]_i_13_n_0\
);
-\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_14\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0080"
+ INIT => X"0001"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(0),
- I1 => \^aa_grant_rnw\,
- I2 => \^m_valid_i\,
- I3 => m_ready_d_1(1),
- O => m_axi_arvalid(0)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(13),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(12),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(11),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(10),
+ O => \m_atarget_hot[5]_i_14_n_0\
);
-\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_15\: unisim.vcomponents.LUT2
generic map(
- INIT => X"0080"
+ INIT => X"1"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(1),
- I1 => \^aa_grant_rnw\,
- I2 => \^m_valid_i\,
- I3 => m_ready_d_1(1),
- O => m_axi_arvalid(1)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(25),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(20),
+ O => \m_atarget_hot[5]_i_15_n_0\
);
-\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_16\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0080"
+ INIT => X"0100"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(2),
- I1 => \^aa_grant_rnw\,
- I2 => \^m_valid_i\,
- I3 => m_ready_d_1(1),
- O => m_axi_arvalid(2)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(13),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(12),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
+ O => \m_atarget_hot[5]_i_16_n_0\
);
-\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_2\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0020"
+ INIT => X"C800"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(0),
- I1 => \^aa_grant_rnw\,
- I2 => \^m_valid_i\,
- I3 => m_ready_d(2),
- O => m_axi_awvalid(0)
+ I0 => \m_atarget_hot[5]_i_6_n_0\,
+ I1 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
+ I2 => \m_atarget_hot[5]_i_8_n_0\,
+ I3 => \m_atarget_hot[5]_i_9_n_0\,
+ O => \m_atarget_hot[5]_i_2_n_0\
);
-\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"0020"
+ INIT => X"0001000000000000"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(1),
- I1 => \^aa_grant_rnw\,
- I2 => \^m_valid_i\,
- I3 => m_ready_d(2),
- O => m_axi_awvalid(1)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(17),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(16),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(19),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(18),
+ I4 => \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
+ I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
+ O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\
);
-\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
+\m_atarget_hot[5]_i_4\: unisim.vcomponents.LUT5
generic map(
- INIT => X"0020"
+ INIT => X"80000000"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(2),
- I1 => \^aa_grant_rnw\,
- I2 => \^m_valid_i\,
- I3 => m_ready_d(2),
- O => m_axi_awvalid(2)
+ I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
+ I1 => \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\,
+ I2 => \m_atarget_hot[5]_i_12_n_0\,
+ I3 => \m_atarget_hot[5]_i_13_n_0\,
+ I4 => \m_atarget_hot[5]_i_14_n_0\,
+ O => target_mi_enc(2)
);
-\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
+\m_atarget_hot[5]_i_5\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00200000"
+ INIT => X"0800000000000000"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(0),
- I1 => m_ready_d(0),
- I2 => \^m_valid_i\,
- I3 => \^aa_grant_rnw\,
- I4 => s_axi_bready(0),
- O => m_axi_bready(0)
+ I0 => \gen_addr_decoder.addr_decoder_inst/gen_target[4].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\,
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
+ I3 => \m_atarget_hot[5]_i_15_n_0\,
+ I4 => \m_atarget_hot[5]_i_16_n_0\,
+ I5 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
+ O => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\
);
-\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
+\m_atarget_hot[5]_i_6\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00200000"
+ INIT => X"0000000000000020"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(1),
- I1 => m_ready_d(0),
- I2 => \^m_valid_i\,
- I3 => \^aa_grant_rnw\,
- I4 => s_axi_bready(0),
- O => m_axi_bready(1)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
+ I4 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(20),
+ I5 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(25),
+ O => \m_atarget_hot[5]_i_6_n_0\
);
-\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
+\m_atarget_hot[5]_i_7\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00200000"
+ INIT => X"0000000100000000"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(2),
- I1 => m_ready_d(0),
- I2 => \^m_valid_i\,
- I3 => \^aa_grant_rnw\,
- I4 => s_axi_bready(0),
- O => m_axi_bready(2)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(28),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(29),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(26),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(27),
+ I4 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(31),
+ I5 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(30),
+ O => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
-\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
+\m_atarget_hot[5]_i_8\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00200000"
+ INIT => X"0000000000000080"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(0),
- I1 => m_ready_d(1),
- I2 => \^m_valid_i\,
- I3 => \^aa_grant_rnw\,
- I4 => s_axi_wvalid(0),
- O => m_axi_wvalid(0)
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(23),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(24),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(22),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(21),
+ I4 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(20),
+ I5 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(25),
+ O => \m_atarget_hot[5]_i_8_n_0\
);
-\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
+\m_atarget_hot[5]_i_9\: unisim.vcomponents.LUT4
generic map(
- INIT => X"00200000"
+ INIT => X"0001"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(1),
- I1 => m_ready_d(1),
+ I0 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(17),
+ I1 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(16),
+ I2 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(19),
+ I3 => \^gen_no_arbiter.m_amesg_i_reg[48]_0\(18),
+ O => \m_atarget_hot[5]_i_9_n_0\
+ );
+\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"2000"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => m_ready_d_1(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
- I4 => s_axi_wvalid(0),
- O => m_axi_wvalid(1)
+ O => m_axi_arvalid(0)
);
-\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
+\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"00200000"
+ INIT => X"2000"
)
port map (
- I0 => \gen_axilite.s_axi_bvalid_i_reg\(2),
- I1 => m_ready_d(1),
+ I0 => Q(1),
+ I1 => m_ready_d_1(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
- I4 => s_axi_wvalid(0),
- O => m_axi_wvalid(2)
+ O => m_axi_arvalid(1)
);
-\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
+\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0080FFFF"
+ INIT => X"2000"
)
port map (
- I0 => s_axi_rready(0),
- I1 => \^aa_grant_rnw\,
+ I0 => Q(2),
+ I1 => m_ready_d_1(1),
I2 => \^m_valid_i\,
- I3 => m_ready_d_1(0),
- I4 => sr_rvalid,
- O => E(0)
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_arvalid(2)
);
-\m_ready_d[0]_i_2\: unisim.vcomponents.LUT4
+\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0020"
+ INIT => X"2000"
)
port map (
- I0 => s_axi_bready(0),
- I1 => \^aa_grant_rnw\,
+ I0 => Q(3),
+ I1 => m_ready_d_1(1),
I2 => \^m_valid_i\,
- I3 => m_ready_d(0),
- O => s_axi_bready_0_sn_1
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_arvalid(3)
);
-\m_ready_d[0]_i_2__0\: unisim.vcomponents.LUT2
+\m_axi_arvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"7"
+ INIT => X"2000"
)
port map (
- I0 => \^aa_grant_rnw\,
- I1 => \^m_valid_i\,
- O => \gen_no_arbiter.grant_rnw_reg_1\
+ I0 => Q(4),
+ I1 => m_ready_d_1(1),
+ I2 => \^m_valid_i\,
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_arvalid(4)
);
-\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
+\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"B"
+ INIT => X"0020"
)
port map (
- I0 => \m_ready_d[0]_i_4_n_0\,
- I1 => aresetn_d,
- O => aresetn_d_reg
+ I0 => Q(0),
+ I1 => m_ready_d(2),
+ I2 => \^m_valid_i\,
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_awvalid(0)
);
-\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
+\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"00000000F8F0F8F8"
+ INIT => X"0020"
)
port map (
- I0 => \^aa_grant_rnw\,
- I1 => \^m_valid_i\,
- I2 => m_ready_d_1(1),
- I3 => \m_ready_d_reg[1]_0\,
- I4 => \m_ready_d_reg[1]_1\,
- I5 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1\,
- O => \m_ready_d[0]_i_4_n_0\
+ I0 => Q(1),
+ I1 => m_ready_d(2),
+ I2 => \^m_valid_i\,
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_awvalid(1)
);
-\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
+\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
- I0 => s_axi_wvalid(0),
- I1 => \^aa_grant_rnw\,
+ I0 => Q(2),
+ I1 => m_ready_d(2),
I2 => \^m_valid_i\,
- I3 => m_ready_d(1),
- O => s_axi_wvalid_0_sn_1
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_awvalid(2)
);
-\m_ready_d[1]_i_2__0\: unisim.vcomponents.LUT5
+\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"FDF0F0F0"
+ INIT => X"0020"
)
port map (
- I0 => \m_ready_d_reg[1]_1\,
- I1 => \m_ready_d_reg[1]_0\,
- I2 => m_ready_d_1(1),
- I3 => \^m_valid_i\,
- I4 => \^aa_grant_rnw\,
- O => m_ready_d0_0(0)
+ I0 => Q(3),
+ I1 => m_ready_d(2),
+ I2 => \^m_valid_i\,
+ I3 => \^aa_grant_rnw\,
+ O => m_axi_awvalid(3)
);
-\m_ready_d[2]_i_7\: unisim.vcomponents.LUT6
+\m_axi_awvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
- INIT => X"FFFFFFFF00D00000"
+ INIT => X"0020"
)
port map (
- I0 => \m_ready_d[2]_i_3\,
- I1 => \m_ready_d[2]_i_3_0\,
- I2 => s_axi_bready(0),
+ I0 => Q(4),
+ I1 => m_ready_d(2),
+ I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
- I4 => \^m_valid_i\,
- I5 => m_ready_d(0),
- O => \^m_ready_d0\(0)
+ O => m_axi_awvalid(4)
);
-m_valid_i_i_1: unisim.vcomponents.LUT3
+\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
- INIT => X"8A"
+ INIT => X"00000800"
)
port map (
- I0 => m_valid_i_reg(1),
- I1 => m_valid_i_i_2_n_0,
- I2 => m_valid_i_i_3_n_0,
- O => \aresetn_d_reg[1]\
+ I0 => Q(0),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_bready(0),
+ I4 => m_ready_d(0),
+ O => m_axi_bready(0)
);
-m_valid_i_i_2: unisim.vcomponents.LUT5
+\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
- INIT => X"8AAAAAAA"
+ INIT => X"00000800"
)
port map (
- I0 => sr_rvalid,
- I1 => m_ready_d_1(0),
- I2 => \^m_valid_i\,
- I3 => \^aa_grant_rnw\,
- I4 => s_axi_rready(0),
- O => m_valid_i_i_2_n_0
+ I0 => Q(1),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_bready(0),
+ I4 => m_ready_d(0),
+ O => m_axi_bready(1)
);
-m_valid_i_i_3: unisim.vcomponents.LUT6
+\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
- INIT => X"8AAAAAAA8AAA8AAA"
+ INIT => X"00000800"
)
port map (
- I0 => aa_rready,
- I1 => m_ready_d_1(0),
- I2 => \^m_valid_i\,
- I3 => \^aa_grant_rnw\,
- I4 => m_valid_i_reg_0,
- I5 => m_valid_i_reg_1,
- O => m_valid_i_i_3_n_0
+ I0 => Q(2),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_bready(0),
+ I4 => m_ready_d(0),
+ O => m_axi_bready(2)
);
-\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
+\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
- INIT => X"0040"
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_bready(0),
+ I4 => m_ready_d(0),
+ O => m_axi_bready(3)
+ );
+\m_axi_bready[4]_INST_0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(4),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_bready(0),
+ I4 => m_ready_d(0),
+ O => m_axi_bready(4)
+ );
+\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(0),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_wvalid(0),
+ I4 => m_ready_d(1),
+ O => m_axi_wvalid(0)
+ );
+\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(1),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_wvalid(0),
+ I4 => m_ready_d(1),
+ O => m_axi_wvalid(1)
+ );
+\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(2),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_wvalid(0),
+ I4 => m_ready_d(1),
+ O => m_axi_wvalid(2)
+ );
+\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(3),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_wvalid(0),
+ I4 => m_ready_d(1),
+ O => m_axi_wvalid(3)
+ );
+\m_axi_wvalid[4]_INST_0\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"00000800"
+ )
+ port map (
+ I0 => Q(4),
+ I1 => \^m_valid_i\,
+ I2 => \^aa_grant_rnw\,
+ I3 => s_axi_wvalid(0),
+ I4 => m_ready_d(1),
+ O => m_axi_wvalid(4)
+ );
+\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0800FFFF"
+ )
+ port map (
+ I0 => \^aa_grant_rnw\,
+ I1 => \^m_valid_i\,
+ I2 => m_ready_d_1(0),
+ I3 => s_axi_rready(0),
+ I4 => sr_rvalid,
+ O => \^e\(0)
+ );
+\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF88888880"
+ )
+ port map (
+ I0 => \^aa_grant_rnw\,
+ I1 => \^m_valid_i\,
+ I2 => \m_ready_d_reg[1]_0\,
+ I3 => \m_ready_d_reg[1]_1\,
+ I4 => \m_ready_d_reg[1]_2\,
+ I5 => m_ready_d_1(1),
+ O => m_ready_d0(1)
+ );
+\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF80000000"
+ )
+ port map (
+ I0 => \^aa_grant_rnw\,
+ I1 => \^m_valid_i\,
+ I2 => s_axi_rready(0),
+ I3 => sr_rvalid,
+ I4 => \m_ready_d_reg[1]\(0),
+ I5 => m_ready_d_1(0),
+ O => m_ready_d0(0)
+ );
+\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFF44444440"
+ )
+ port map (
+ I0 => \^aa_grant_rnw\,
+ I1 => \^m_valid_i\,
+ I2 => \gen_no_arbiter.m_valid_i_reg_3\,
+ I3 => \gen_no_arbiter.m_valid_i_reg_2\,
+ I4 => \gen_no_arbiter.m_valid_i_reg_1\,
+ I5 => m_ready_d(2),
+ O => \gen_no_arbiter.grant_rnw_reg_0\(0)
+ );
+\m_ready_d[2]_i_9\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"2"
+ )
+ port map (
+ I0 => \^m_valid_i\,
+ I1 => \^aa_grant_rnw\,
+ O => \gen_no_arbiter.m_valid_i_reg_0\
+ );
+m_valid_i_i_1: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"C4"
+ )
+ port map (
+ I0 => \^e\(0),
+ I1 => m_valid_i_reg(1),
+ I2 => m_valid_i_i_2_n_0,
+ O => \aresetn_d_reg[1]\
+ );
+m_valid_i_i_2: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"AAA8FFFF"
+ )
+ port map (
+ I0 => r_transfer_en,
+ I1 => m_valid_i_reg_0,
+ I2 => m_valid_i_reg_1,
+ I3 => m_valid_i_reg_2,
+ I4 => aa_rready,
+ O => m_valid_i_i_2_n_0
+ );
+m_valid_i_i_3: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"08"
+ )
+ port map (
+ I0 => \^aa_grant_rnw\,
+ I1 => \^m_valid_i\,
+ I2 => m_ready_d_1(0),
+ O => r_transfer_en
+ );
+\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
+ generic map(
+ INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
@@ -1512,8 +1707,8 @@ m_valid_i_i_3: unisim.vcomponents.LUT6
INIT => X"8"
)
port map (
- I0 => \^aa_grant_rnw\,
- I1 => s_ready_i,
+ I0 => s_ready_i,
+ I1 => \^aa_grant_rnw\,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
@@ -1527,36 +1722,45 @@ m_valid_i_i_3: unisim.vcomponents.LUT6
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00000004"
+ INIT => X"00020000"
)
port map (
- I0 => m_ready_d(0),
- I1 => \^m_valid_i\,
- I2 => \^aa_grant_rnw\,
- I3 => \^p_0_in1_in\,
- I4 => s_axi_bvalid_0_sn_1,
+ I0 => \^m_valid_i\,
+ I1 => \^aa_grant_rnw\,
+ I2 => p_0_in1_in,
+ I3 => m_ready_d(0),
+ I4 => \f_mux_return__3\,
O => s_axi_bvalid(0)
);
+\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"4"
+ )
+ port map (
+ I0 => p_0_in1_in,
+ I1 => sr_rvalid,
+ O => s_axi_rvalid(0)
+ );
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00000004"
+ INIT => X"00020000"
)
port map (
- I0 => m_ready_d(1),
- I1 => \^m_valid_i\,
- I2 => \^aa_grant_rnw\,
- I3 => \^p_0_in1_in\,
- I4 => s_axi_wready_0_sn_1,
+ I0 => \^m_valid_i\,
+ I1 => \^aa_grant_rnw\,
+ I2 => p_0_in1_in,
+ I3 => m_ready_d(1),
+ I4 => \f_mux_return__1\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
- INIT => X"8A"
+ INIT => X"B0"
)
port map (
- I0 => m_valid_i_reg(0),
- I1 => m_valid_i_i_3_n_0,
- I2 => m_valid_i_i_2_n_0,
+ I0 => \^e\(0),
+ I1 => m_valid_i_i_2_n_0,
+ I2 => m_valid_i_reg(0),
O => \aresetn_d_reg[0]\
);
end STRUCTURE;
@@ -1568,56 +1772,67 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave is
port (
mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
- \m_atarget_enc_reg[1]\ : out STD_LOGIC;
- \gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC;
- \m_axi_bvalid[2]\ : out STD_LOGIC;
- \gen_axilite.s_axi_arready_i_reg_0\ : out STD_LOGIC;
- \gen_axilite.s_axi_rvalid_i_reg_0\ : out STD_LOGIC;
- m_axi_wready_3_sp_1 : out STD_LOGIC;
- m_axi_wready_0_sp_1 : out STD_LOGIC;
+ m_ready_d0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ m_axi_rvalid_0_sp_1 : out STD_LOGIC;
+ m_axi_arready_0_sp_1 : out STD_LOGIC;
+ \f_mux_return__3\ : out STD_LOGIC;
+ \f_mux_return__1\ : out STD_LOGIC;
+ m_axi_awready_0_sp_1 : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
- \gen_axilite.s_axi_bvalid_i_reg_1\ : in STD_LOGIC;
+ \gen_axilite.s_axi_bvalid_i_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC;
- m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- \gen_axilite.s_axi_rvalid_i_reg_1\ : in STD_LOGIC;
+ \m_ready_d_reg[2]\ : in STD_LOGIC;
+ \m_ready_d_reg[2]_0\ : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
+ \m_ready_d_reg[2]_1\ : in STD_LOGIC;
+ m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \m_ready_d_reg[2]_2\ : in STD_LOGIC;
+ \m_ready_d_reg[2]_3\ : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
- \m_ready_d_reg[0]\ : in STD_LOGIC;
- m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
+ mi_arvalid_en : in STD_LOGIC;
+ Q : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_ready_d[2]_i_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ f_mux_return2 : in STD_LOGIC;
+ f_mux_return3 : in STD_LOGIC;
+ m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_rready : in STD_LOGIC
);
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave : entity is "axi_crossbar_v2_1_33_decerr_slave";
end mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave;
architecture STRUCTURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave is
signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC;
- signal m_axi_wready_0_sn_1 : STD_LOGIC;
- signal m_axi_wready_3_sn_1 : STD_LOGIC;
- signal mi_arready : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal m_axi_arready_0_sn_1 : STD_LOGIC;
+ signal m_axi_awready_0_sn_1 : STD_LOGIC;
+ signal m_axi_rvalid_0_sn_1 : STD_LOGIC;
+ signal mi_arready : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
- signal mi_rvalid : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal mi_rvalid : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal \s_axi_bvalid[0]_INST_0_i_2_n_0\ : STD_LOGIC;
+ signal \s_axi_wready[0]_INST_0_i_4_n_0\ : STD_LOGIC;
begin
- m_axi_wready_0_sp_1 <= m_axi_wready_0_sn_1;
- m_axi_wready_3_sp_1 <= m_axi_wready_3_sn_1;
+ m_axi_arready_0_sp_1 <= m_axi_arready_0_sn_1;
+ m_axi_awready_0_sp_1 <= m_axi_awready_0_sn_1;
+ m_axi_rvalid_0_sp_1 <= m_axi_rvalid_0_sn_1;
mi_bvalid(0) <= \^mi_bvalid\(0);
mi_wready(0) <= \^mi_wready\(0);
\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5
generic map(
- INIT => X"F07F0000"
+ INIT => X"A02AA0AA"
)
port map (
- I0 => Q(0),
- I1 => \gen_axilite.s_axi_rvalid_i_reg_1\,
- I2 => mi_arready(4),
- I3 => mi_rvalid(4),
- I4 => aresetn_d,
+ I0 => aresetn_d,
+ I1 => mi_arvalid_en,
+ I2 => mi_arready(5),
+ I3 => mi_rvalid(5),
+ I4 => Q(0),
O => \gen_axilite.s_axi_arready_i_i_1_n_0\
);
\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
@@ -1628,7 +1843,7 @@ begin
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_arready_i_i_1_n_0\,
- Q => mi_arready(4),
+ Q => mi_arready(5),
R => '0'
);
\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
@@ -1649,19 +1864,19 @@ begin
port map (
C => aclk,
CE => '1',
- D => \gen_axilite.s_axi_bvalid_i_reg_1\,
+ D => \gen_axilite.s_axi_bvalid_i_reg_0\,
Q => \^mi_bvalid\(0),
R => SR(0)
);
\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
- INIT => X"08F8F0F0"
+ INIT => X"55C0FF00"
)
port map (
- I0 => mi_arready(4),
- I1 => \gen_axilite.s_axi_rvalid_i_reg_1\,
- I2 => mi_rvalid(4),
- I3 => aa_rready,
+ I0 => aa_rready,
+ I1 => mi_arvalid_en,
+ I2 => mi_arready(5),
+ I3 => mi_rvalid(5),
I4 => Q(0),
O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\
);
@@ -1673,94 +1888,120 @@ begin
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\,
- Q => mi_rvalid(4),
+ Q => mi_rvalid(5),
R => SR(0)
);
-\m_ready_d[1]_i_4\: unisim.vcomponents.LUT5
+\m_ready_d[1]_i_5\: unisim.vcomponents.LUT5
generic map(
- INIT => X"FDCFFDFF"
+ INIT => X"0C00000A"
)
port map (
- I0 => mi_arready(4),
- I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(1),
- I3 => m_atarget_enc(2),
- I4 => m_axi_arready(0),
- O => \gen_axilite.s_axi_arready_i_reg_0\
+ I0 => m_axi_arready(0),
+ I1 => mi_arready(5),
+ I2 => \m_ready_d[2]_i_2\(1),
+ I3 => \m_ready_d[2]_i_2\(2),
+ I4 => \m_ready_d[2]_i_2\(0),
+ O => m_axi_arready_0_sn_1
);
-\m_ready_d[2]_i_5\: unisim.vcomponents.LUT4
+\m_ready_d[2]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"0400"
+ INIT => X"FFFFFFFFFE000000"
)
port map (
- I0 => m_atarget_enc(1),
- I1 => m_atarget_enc(2),
- I2 => m_atarget_enc(0),
- I3 => \^mi_wready\(0),
- O => \m_atarget_enc_reg[1]\
+ I0 => \m_ready_d_reg[2]_2\,
+ I1 => \s_axi_wready[0]_INST_0_i_4_n_0\,
+ I2 => \m_ready_d_reg[2]_3\,
+ I3 => s_axi_wvalid(0),
+ I4 => \m_ready_d_reg[2]_1\,
+ I5 => m_ready_d(1),
+ O => m_ready_d0(1)
);
-\m_ready_d[2]_i_8\: unisim.vcomponents.LUT5
+\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FDCFFDFF"
+ INIT => X"FFFFFFFFFE000000"
)
port map (
- I0 => m_axi_bvalid(0),
- I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(1),
- I4 => \^mi_bvalid\(0),
- O => \m_axi_bvalid[2]\
+ I0 => \m_ready_d_reg[2]\,
+ I1 => \s_axi_bvalid[0]_INST_0_i_2_n_0\,
+ I2 => \m_ready_d_reg[2]_0\,
+ I3 => s_axi_bready(0),
+ I4 => \m_ready_d_reg[2]_1\,
+ I5 => m_ready_d(0),
+ O => m_ready_d0(0)
+ );
+\m_ready_d[2]_i_6\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0C00000A"
+ )
+ port map (
+ I0 => m_axi_awready(0),
+ I1 => \^mi_wready\(0),
+ I2 => \m_ready_d[2]_i_2\(1),
+ I3 => \m_ready_d[2]_i_2\(2),
+ I4 => \m_ready_d[2]_i_2\(0),
+ O => m_axi_awready_0_sn_1
);
m_valid_i_i_5: unisim.vcomponents.LUT5
generic map(
- INIT => X"FCDFFFDF"
+ INIT => X"0C00000A"
)
port map (
- I0 => mi_rvalid(4),
- I1 => m_atarget_enc(1),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(0),
- I4 => m_axi_rvalid(0),
- O => \gen_axilite.s_axi_rvalid_i_reg_0\
+ I0 => m_axi_rvalid(0),
+ I1 => mi_rvalid(5),
+ I2 => \m_ready_d[2]_i_2\(1),
+ I3 => \m_ready_d[2]_i_2\(2),
+ I4 => \m_ready_d[2]_i_2\(0),
+ O => m_axi_rvalid_0_sn_1
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00000000FFD3FFDF"
+ INIT => X"FFFFFFFFFFFFF888"
)
port map (
- I0 => \^mi_bvalid\(0),
- I1 => m_atarget_enc(1),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(0),
- I4 => m_axi_bvalid(0),
- I5 => \m_ready_d_reg[0]\,
- O => \gen_axilite.s_axi_bvalid_i_reg_0\
+ I0 => m_axi_bvalid(2),
+ I1 => f_mux_return2,
+ I2 => m_axi_bvalid(1),
+ I3 => f_mux_return3,
+ I4 => \s_axi_bvalid[0]_INST_0_i_2_n_0\,
+ I5 => \m_ready_d_reg[2]_0\,
+ O => \f_mux_return__3\
+ );
+\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0C00000A"
+ )
+ port map (
+ I0 => m_axi_bvalid(0),
+ I1 => \^mi_bvalid\(0),
+ I2 => \m_ready_d[2]_i_2\(1),
+ I3 => \m_ready_d[2]_i_2\(2),
+ I4 => \m_ready_d[2]_i_2\(0),
+ O => \s_axi_bvalid[0]_INST_0_i_2_n_0\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00000000F4FFF7FF"
+ INIT => X"FFFFFFFFFFFFF888"
)
port map (
- I0 => m_axi_wready(3),
- I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(1),
- I4 => m_axi_wready(2),
- I5 => m_axi_wready_0_sn_1,
- O => m_axi_wready_3_sn_1
+ I0 => m_axi_wready(2),
+ I1 => f_mux_return2,
+ I2 => m_axi_wready(1),
+ I3 => f_mux_return3,
+ I4 => \s_axi_wready[0]_INST_0_i_4_n_0\,
+ I5 => \m_ready_d_reg[2]_3\,
+ O => \f_mux_return__1\
);
-\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
+\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00000FCA000000CA"
+ INIT => X"00A0000C"
)
port map (
- I0 => m_axi_wready(0),
- I1 => m_axi_wready(1),
- I2 => m_atarget_enc(0),
- I3 => m_atarget_enc(2),
- I4 => m_atarget_enc(1),
- I5 => \^mi_wready\(0),
- O => m_axi_wready_0_sn_1
+ I0 => \^mi_wready\(0),
+ I1 => m_axi_wready(0),
+ I2 => \m_ready_d[2]_i_2\(2),
+ I3 => \m_ready_d[2]_i_2\(1),
+ I4 => \m_ready_d[2]_i_2\(0),
+ O => \s_axi_wready[0]_INST_0_i_4_n_0\
);
end STRUCTURE;
library IEEE;
@@ -1769,121 +2010,117 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter is
port (
+ m_axi_bvalid_2_sp_1 : out STD_LOGIC;
+ m_axi_wready_2_sp_1 : out STD_LOGIC;
+ m_axi_awready_2_sp_1 : out STD_LOGIC;
+ \m_axi_bvalid[4]\ : out STD_LOGIC;
+ \m_axi_wready[4]\ : out STD_LOGIC;
+ \m_axi_awready[4]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
- \m_ready_d_reg[2]_0\ : out STD_LOGIC;
- m_axi_bvalid_0_sp_1 : out STD_LOGIC;
- m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
- \m_ready_d_reg[1]_0\ : in STD_LOGIC;
- \m_ready_d_reg[1]_1\ : in STD_LOGIC;
- m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \m_ready_d_reg[2]_1\ : in STD_LOGIC;
- \m_ready_d_reg[2]_2\ : in STD_LOGIC;
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
- \m_ready_d_reg[0]_0\ : in STD_LOGIC;
- \m_ready_d_reg[0]_1\ : in STD_LOGIC;
+ m_ready_d0 : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter : entity is "axi_crossbar_v2_1_33_splitter";
end mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter;
architecture STRUCTURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter is
- signal m_axi_bvalid_0_sn_1 : STD_LOGIC;
- signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal m_axi_awready_2_sn_1 : STD_LOGIC;
+ signal m_axi_bvalid_2_sn_1 : STD_LOGIC;
+ signal m_axi_wready_2_sn_1 : STD_LOGIC;
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
- signal \m_ready_d[2]_i_3_n_0\ : STD_LOGIC;
- signal \m_ready_d[2]_i_4_n_0\ : STD_LOGIC;
- signal \m_ready_d[2]_i_6_n_0\ : STD_LOGIC;
- signal \^m_ready_d_reg[2]_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair22";
+ attribute SOFT_HLUTNM of \m_ready_d[2]_i_1\ : label is "soft_lutpair22";
begin
- m_axi_bvalid_0_sp_1 <= m_axi_bvalid_0_sn_1;
- m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
- \m_ready_d_reg[2]_0\ <= \^m_ready_d_reg[2]_0\;
-\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
+ m_axi_awready_2_sp_1 <= m_axi_awready_2_sn_1;
+ m_axi_bvalid_2_sp_1 <= m_axi_bvalid_2_sn_1;
+ m_axi_wready_2_sp_1 <= m_axi_wready_2_sn_1;
+\m_ready_d[0]_i_1\: unisim.vcomponents.LUT4
generic map(
- INIT => X"F2000000"
+ INIT => X"2A00"
)
port map (
- I0 => \m_ready_d_reg[0]_0\,
- I1 => \m_ready_d_reg[0]_1\,
- I2 => \^m_ready_d\(0),
- I3 => \m_ready_d[2]_i_3_n_0\,
- I4 => aresetn_d,
+ I0 => aresetn_d,
+ I1 => m_ready_d0(2),
+ I2 => m_ready_d0(1),
+ I3 => m_ready_d0(0),
O => \m_ready_d[0]_i_1_n_0\
);
-\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
+\m_ready_d[1]_i_1\: unisim.vcomponents.LUT4
generic map(
- INIT => X"BA000000"
+ INIT => X"20A0"
)
port map (
- I0 => \^m_ready_d\(1),
- I1 => \m_ready_d_reg[1]_0\,
- I2 => \m_ready_d_reg[1]_1\,
- I3 => \m_ready_d[2]_i_3_n_0\,
- I4 => aresetn_d,
+ I0 => aresetn_d,
+ I1 => m_ready_d0(2),
+ I2 => m_ready_d0(1),
+ I3 => m_ready_d0(0),
O => \m_ready_d[1]_i_1_n_0\
);
-\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
+\m_ready_d[2]_i_1\: unisim.vcomponents.LUT4
generic map(
- INIT => X"40"
+ INIT => X"0888"
)
port map (
- I0 => \^m_ready_d_reg[2]_0\,
- I1 => \m_ready_d[2]_i_3_n_0\,
- I2 => aresetn_d,
+ I0 => aresetn_d,
+ I1 => m_ready_d0(2),
+ I2 => m_ready_d0(1),
+ I3 => m_ready_d0(0),
O => \m_ready_d[2]_i_1_n_0\
);
-\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
+\m_ready_d[2]_i_10\: unisim.vcomponents.LUT5
generic map(
- INIT => X"4445444444454445"
+ INIT => X"0C0000A0"
)
port map (
- I0 => \^m_ready_d\(2),
- I1 => \m_ready_d_reg[2]_1\,
- I2 => \m_ready_d[2]_i_4_n_0\,
- I3 => \m_ready_d_reg[2]_2\,
- I4 => \m_ready_d[2]_i_6_n_0\,
- I5 => m_axi_awready(1),
- O => \^m_ready_d_reg[2]_0\
+ I0 => m_axi_bvalid(3),
+ I1 => m_axi_bvalid(2),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => \m_axi_bvalid[4]\
);
-\m_ready_d[2]_i_3\: unisim.vcomponents.LUT5
+\m_ready_d[2]_i_5\: unisim.vcomponents.LUT5
generic map(
- INIT => X"FF45FFFF"
+ INIT => X"0C0000A0"
)
port map (
- I0 => \^m_ready_d\(1),
- I1 => \m_ready_d_reg[1]_0\,
- I2 => \m_ready_d_reg[1]_1\,
- I3 => \^m_ready_d_reg[2]_0\,
- I4 => m_ready_d0(0),
- O => \m_ready_d[2]_i_3_n_0\
+ I0 => m_axi_awready(3),
+ I1 => m_axi_awready(2),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => \m_axi_awready[4]\
);
-\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
+\m_ready_d[2]_i_7\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00CA000F00CA0000"
+ INIT => X"000C0A00"
)
port map (
- I0 => m_axi_awready(2),
- I1 => m_axi_awready(3),
- I2 => m_atarget_enc(0),
- I3 => m_atarget_enc(2),
- I4 => m_atarget_enc(1),
- I5 => m_axi_awready(0),
- O => \m_ready_d[2]_i_4_n_0\
+ I0 => m_axi_awready(1),
+ I1 => m_axi_awready(0),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => m_axi_awready_2_sn_1
);
-\m_ready_d[2]_i_6\: unisim.vcomponents.LUT3
+\m_ready_d[2]_i_8\: unisim.vcomponents.LUT5
generic map(
- INIT => X"EF"
+ INIT => X"0C0000A0"
)
port map (
- I0 => m_atarget_enc(1),
- I1 => m_atarget_enc(2),
- I2 => m_atarget_enc(0),
- O => \m_ready_d[2]_i_6_n_0\
+ I0 => m_axi_wready(3),
+ I1 => m_axi_wready(2),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => \m_axi_wready[4]\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
@@ -1893,7 +2130,7 @@ begin
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
- Q => \^m_ready_d\(0),
+ Q => m_ready_d(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
@@ -1904,7 +2141,7 @@ begin
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
- Q => \^m_ready_d\(1),
+ Q => m_ready_d(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
@@ -1915,21 +2152,32 @@ begin
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
- Q => \^m_ready_d\(2),
+ Q => m_ready_d(2),
R => '0'
);
-\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
+\s_axi_bvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00F000CA000000CA"
+ INIT => X"000C0A00"
)
port map (
- I0 => m_axi_bvalid(0),
- I1 => m_axi_bvalid(1),
- I2 => m_atarget_enc(0),
- I3 => m_atarget_enc(2),
- I4 => m_atarget_enc(1),
- I5 => m_axi_bvalid(2),
- O => m_axi_bvalid_0_sn_1
+ I0 => m_axi_bvalid(1),
+ I1 => m_axi_bvalid(0),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => m_axi_bvalid_2_sn_1
+ );
+\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"000C0A00"
+ )
+ port map (
+ I0 => m_axi_wready(1),
+ I1 => m_axi_wready(0),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => m_axi_wready_2_sn_1
);
end STRUCTURE;
library IEEE;
@@ -1938,18 +2186,13 @@ library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0\ is
port (
- m_axi_arready_1_sp_1 : out STD_LOGIC;
+ m_axi_arready_2_sp_1 : out STD_LOGIC;
+ \m_axi_arready[4]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
- m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn_d : in STD_LOGIC;
- m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
- \m_ready_d_reg[1]_0\ : in STD_LOGIC;
- sr_rvalid : in STD_LOGIC;
- Q : in STD_LOGIC_VECTOR ( 0 to 0 );
- s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- \m_ready_d_reg[0]_0\ : in STD_LOGIC;
- \m_ready_d_reg[0]_1\ : in STD_LOGIC;
+ m_ready_d0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
@@ -1957,48 +2200,57 @@ entity \mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0\ is
end \mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0\;
architecture STRUCTURE of \mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0\ is
- signal m_axi_arready_1_sn_1 : STD_LOGIC;
- signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m_axi_arready_2_sn_1 : STD_LOGIC;
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \m_ready_d[0]_i_1\ : label is "soft_lutpair21";
+ attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair21";
begin
- m_axi_arready_1_sp_1 <= m_axi_arready_1_sn_1;
- m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
-\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
+ m_axi_arready_2_sp_1 <= m_axi_arready_2_sn_1;
+\m_ready_d[0]_i_1\: unisim.vcomponents.LUT3
generic map(
- INIT => X"00000000FFFF0080"
+ INIT => X"20"
)
port map (
- I0 => sr_rvalid,
- I1 => Q(0),
- I2 => s_axi_rready(0),
- I3 => \m_ready_d_reg[0]_0\,
- I4 => \^m_ready_d\(0),
- I5 => \m_ready_d_reg[0]_1\,
+ I0 => aresetn_d,
+ I1 => m_ready_d0(1),
+ I2 => m_ready_d0(0),
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
- INIT => X"80"
+ INIT => X"08"
)
port map (
I0 => aresetn_d,
- I1 => m_ready_d0(0),
- I2 => \m_ready_d_reg[1]_0\,
+ I1 => m_ready_d0(1),
+ I2 => m_ready_d0(0),
O => \m_ready_d[1]_i_1_n_0\
);
-\m_ready_d[1]_i_5\: unisim.vcomponents.LUT6
+\m_ready_d[1]_i_4\: unisim.vcomponents.LUT5
+ generic map(
+ INIT => X"0C0000A0"
+ )
+ port map (
+ I0 => m_axi_arready(3),
+ I1 => m_axi_arready(2),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => \m_axi_arready[4]\
+ );
+\m_ready_d[1]_i_6\: unisim.vcomponents.LUT5
generic map(
- INIT => X"00C000AF00C000A0"
+ INIT => X"000C0A00"
)
port map (
I0 => m_axi_arready(1),
- I1 => m_axi_arready(2),
- I2 => m_atarget_enc(0),
- I3 => m_atarget_enc(2),
- I4 => m_atarget_enc(1),
- I5 => m_axi_arready(0),
- O => m_axi_arready_1_sn_1
+ I1 => m_axi_arready(0),
+ I2 => Q(2),
+ I3 => Q(1),
+ I4 => Q(0),
+ O => m_axi_arready_2_sn_1
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
@@ -2008,7 +2260,7 @@ begin
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
- Q => \^m_ready_d\(0),
+ Q => m_ready_d(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
@@ -2019,7 +2271,7 @@ begin
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
- Q => \^m_ready_d\(1),
+ Q => m_ready_d(1),
R => '0'
);
end STRUCTURE;
@@ -2031,60 +2283,85 @@ entity mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
- m_valid_i_reg_0 : out STD_LOGIC;
+ \m_ready_d_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
m_axi_rvalid_2_sp_1 : out STD_LOGIC;
- s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ \m_axi_rvalid[4]\ : out STD_LOGIC;
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 );
\aresetn_d_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
- m_valid_i_reg_1 : in STD_LOGIC;
+ m_valid_i_reg_0 : in STD_LOGIC;
aclk : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
- m_atarget_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ : in STD_LOGIC;
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ : in STD_LOGIC;
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\ : in STD_LOGIC;
+ mi_arvalid_en : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
- m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
- p_0_in1_in : in STD_LOGIC;
- \m_axi_rready[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ aa_grant_rnw : in STD_LOGIC;
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ \m_payload_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ \m_axi_rready[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice : entity is "axi_register_slice_v2_1_32_axic_register_slice";
end mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice;
architecture STRUCTURE of mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^aa_rready\ : STD_LOGIC;
signal \^aresetn_d_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5_n_0\ : STD_LOGIC;
signal m_axi_rvalid_2_sn_1 : STD_LOGIC;
signal \m_payload_i[10]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[10]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[11]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[12]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[13]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[14]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[15]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[16]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[17]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[18]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[19]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[20]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[21]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[22]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[23]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[24]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[25]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[26]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[27]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[28]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[29]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[30]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_2_n_0\ : STD_LOGIC;
@@ -2094,13 +2371,21 @@ architecture STRUCTURE of mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_reg
signal \m_payload_i[34]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_5_n_0\ : STD_LOGIC;
+ signal \m_payload_i[34]_i_6_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[3]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[4]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[5]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[6]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[7]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[8]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_2_n_0\ : STD_LOGIC;
+ signal \m_payload_i[9]_i_3_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
@@ -2139,10 +2424,12 @@ architecture STRUCTURE of mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_reg
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
- attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair17";
- attribute SOFT_HLUTNM of \m_payload_i[34]_i_3\ : label is "soft_lutpair16";
- attribute SOFT_HLUTNM of \skid_buffer[0]_i_1\ : label is "soft_lutpair16";
+ attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair20";
+ attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair19";
+ attribute SOFT_HLUTNM of \m_payload_i[34]_i_5\ : label is "soft_lutpair18";
+ attribute SOFT_HLUTNM of \skid_buffer[0]_i_1\ : label is "soft_lutpair18";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
aa_rready <= \^aa_rready\;
@@ -2171,13 +2458,39 @@ begin
Q => \^aresetn_d_reg[1]_0\(1),
R => SR(0)
);
+\gen_no_arbiter.m_grant_hot_i[0]_inv_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"AAAAAAA888888888"
+ )
+ port map (
+ I0 => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5_n_0\,
+ I1 => m_ready_d(1),
+ I2 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\,
+ I3 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\,
+ I4 => \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\,
+ I5 => mi_arvalid_en,
+ O => \m_ready_d_reg[1]\
+ );
+\gen_no_arbiter.m_grant_hot_i[0]_inv_i_5\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"EAAAAAAA00000000"
+ )
+ port map (
+ I0 => m_ready_d(0),
+ I1 => \^q\(0),
+ I2 => \^sr_rvalid\,
+ I3 => s_axi_rready(0),
+ I4 => m_valid_i,
+ I5 => aa_grant_rnw,
+ O => \gen_no_arbiter.m_grant_hot_i[0]_inv_i_5_n_0\
+ );
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
- I0 => \^aa_rready\,
- I1 => \m_axi_rready[2]\(0),
+ I0 => \m_axi_rready[4]\(0),
+ I1 => \^aa_rready\,
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
@@ -2185,8 +2498,8 @@ begin
INIT => X"8"
)
port map (
- I0 => \^aa_rready\,
- I1 => \m_axi_rready[2]\(1),
+ I0 => \m_axi_rready[4]\(1),
+ I1 => \^aa_rready\,
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
@@ -2194,933 +2507,1376 @@ begin
INIT => X"8"
)
port map (
- I0 => \^aa_rready\,
- I1 => \m_axi_rready[2]\(2),
+ I0 => \m_axi_rready[4]\(2),
+ I1 => \^aa_rready\,
O => m_axi_rready(2)
);
-\m_payload_i[10]_i_1\: unisim.vcomponents.LUT5
+\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"8"
)
port map (
- I0 => m_axi_rdata(7),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_axi_rready[4]\(3),
+ I1 => \^aa_rready\,
+ O => m_axi_rready(3)
+ );
+\m_axi_rready[4]_INST_0\: unisim.vcomponents.LUT2
+ generic map(
+ INIT => X"8"
+ )
+ port map (
+ I0 => \m_axi_rready[4]\(4),
+ I1 => \^aa_rready\,
+ O => m_axi_rready(4)
+ );
+\m_payload_i[10]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFBABABA"
+ )
+ port map (
+ I0 => \m_payload_i[10]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[10]_i_2_n_0\,
+ I3 => m_axi_rdata(7),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[10]_i_3_n_0\,
O => skid_buffer(10)
);
\m_payload_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => m_axi_rdata(71),
- I1 => \m_payload_i[32]_i_2_n_0\,
- I2 => m_axi_rdata(103),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => m_axi_rdata(39),
+ I0 => m_axi_rdata(135),
+ I1 => m_axi_rdata(103),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[10]_i_2_n_0\
);
-\m_payload_i[11]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[10]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(71),
+ I1 => m_axi_rdata(39),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[10]_i_3_n_0\
+ );
+\m_payload_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF222"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => \skid_buffer_reg_n_0_[11]\,
+ I0 => \m_payload_i[11]_i_2_n_0\,
I1 => \^aa_rready\,
- I2 => m_axi_rdata(72),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => \m_payload_i[11]_i_2_n_0\,
+ I2 => \skid_buffer_reg_n_0_[11]\,
+ I3 => m_axi_rdata(8),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[11]_i_3_n_0\,
O => skid_buffer(11)
);
\m_payload_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(40),
- I2 => m_axi_rdata(8),
- I3 => \m_payload_i[31]_i_2_n_0\,
- I4 => m_axi_rdata(104),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(136),
+ I1 => m_axi_rdata(104),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[11]_i_2_n_0\
);
+\m_payload_i[11]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(72),
+ I1 => m_axi_rdata(40),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[11]_i_3_n_0\
+ );
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[12]\,
- I3 => m_axi_rdata(105),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[12]_i_2_n_0\,
+ I0 => \m_payload_i[12]_i_2_n_0\,
+ I1 => m_axi_rdata(9),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(137),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[12]_i_3_n_0\,
O => skid_buffer(12)
);
\m_payload_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[31]_i_2_n_0\,
- I1 => m_axi_rdata(9),
- I2 => m_axi_rdata(41),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(73),
- I5 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(105),
+ I1 => m_axi_rdata(73),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[12]_i_2_n_0\
);
+\m_payload_i[12]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[12]\,
+ I1 => m_axi_rdata(41),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[12]_i_3_n_0\
+ );
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[13]\,
- I3 => m_axi_rdata(106),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[13]_i_2_n_0\,
+ I0 => \m_payload_i[13]_i_2_n_0\,
+ I1 => m_axi_rdata(10),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(138),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[13]_i_3_n_0\,
O => skid_buffer(13)
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(106),
I1 => m_axi_rdata(74),
- I2 => m_axi_rdata(42),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(10),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[13]_i_2_n_0\
);
+\m_payload_i[13]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[13]\,
+ I1 => m_axi_rdata(42),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[13]_i_3_n_0\
+ );
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[14]\,
- I3 => m_axi_rdata(75),
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => \m_payload_i[14]_i_2_n_0\,
+ I0 => \m_payload_i[14]_i_2_n_0\,
+ I1 => m_axi_rdata(11),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(139),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[14]_i_3_n_0\,
O => skid_buffer(14)
);
\m_payload_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[34]_i_4_n_0\,
- I1 => m_axi_rdata(107),
- I2 => m_axi_rdata(43),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(11),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(107),
+ I1 => m_axi_rdata(75),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[14]_i_2_n_0\
);
+\m_payload_i[14]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[14]\,
+ I1 => m_axi_rdata(43),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[14]_i_3_n_0\
+ );
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[15]\,
- I3 => m_axi_rdata(44),
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => \m_payload_i[15]_i_2_n_0\,
+ I0 => \m_payload_i[15]_i_2_n_0\,
+ I1 => m_axi_rdata(12),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(140),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[15]_i_3_n_0\,
O => skid_buffer(15)
);
\m_payload_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(108),
I1 => m_axi_rdata(76),
- I2 => m_axi_rdata(108),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => m_axi_rdata(12),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[15]_i_2_n_0\
);
-\m_payload_i[16]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[15]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[15]\,
+ I1 => m_axi_rdata(44),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[15]_i_3_n_0\
+ );
+\m_payload_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(13),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[16]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[16]_i_2_n_0\,
+ I3 => m_axi_rdata(13),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[16]_i_3_n_0\,
O => skid_buffer(16)
);
\m_payload_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => m_axi_rdata(45),
- I1 => \m_payload_i[33]_i_2_n_0\,
- I2 => m_axi_rdata(109),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => m_axi_rdata(77),
+ I0 => m_axi_rdata(141),
+ I1 => m_axi_rdata(109),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[16]_i_2_n_0\
);
+\m_payload_i[16]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(77),
+ I1 => m_axi_rdata(45),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[16]_i_3_n_0\
+ );
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[17]\,
- I3 => m_axi_rdata(46),
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => \m_payload_i[17]_i_2_n_0\,
+ I0 => \m_payload_i[17]_i_2_n_0\,
+ I1 => m_axi_rdata(14),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(142),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[17]_i_3_n_0\,
O => skid_buffer(17)
);
\m_payload_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(110),
I1 => m_axi_rdata(78),
- I2 => m_axi_rdata(110),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => m_axi_rdata(14),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[17]_i_2_n_0\
);
+\m_payload_i[17]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[17]\,
+ I1 => m_axi_rdata(46),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[17]_i_3_n_0\
+ );
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[18]\,
- I3 => m_axi_rdata(111),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[18]_i_2_n_0\,
+ I0 => \m_payload_i[18]_i_2_n_0\,
+ I1 => m_axi_rdata(15),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(143),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[18]_i_3_n_0\,
O => skid_buffer(18)
);
\m_payload_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(47),
- I2 => m_axi_rdata(79),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(15),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(111),
+ I1 => m_axi_rdata(79),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[18]_i_2_n_0\
);
-\m_payload_i[19]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[18]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[18]\,
+ I1 => m_axi_rdata(47),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[18]_i_3_n_0\
+ );
+\m_payload_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(16),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[19]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[19]_i_2_n_0\,
+ I3 => m_axi_rdata(16),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[19]_i_3_n_0\,
O => skid_buffer(19)
);
\m_payload_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => m_axi_rdata(48),
- I1 => \m_payload_i[33]_i_2_n_0\,
- I2 => m_axi_rdata(112),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => m_axi_rdata(80),
+ I0 => m_axi_rdata(144),
+ I1 => m_axi_rdata(112),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[19]_i_2_n_0\
);
+\m_payload_i[19]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(80),
+ I1 => m_axi_rdata(48),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[19]_i_3_n_0\
+ );
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[1]\,
- I3 => m_axi_rresp(4),
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => \m_payload_i[1]_i_2_n_0\,
+ I0 => \m_payload_i[1]_i_2_n_0\,
+ I1 => m_axi_rresp(0),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rresp(8),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[1]_i_3_n_0\,
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[31]_i_2_n_0\,
- I1 => m_axi_rresp(0),
- I2 => m_axi_rresp(2),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rresp(6),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rresp(6),
+ I1 => m_axi_rresp(4),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[1]_i_2_n_0\
);
-\m_payload_i[20]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[1]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"00F000C0AAAAAAAA"
)
port map (
- I0 => m_axi_rdata(17),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \skid_buffer_reg_n_0_[1]\,
+ I1 => m_axi_rresp(2),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[1]_i_3_n_0\
+ );
+\m_payload_i[20]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFBABABA"
+ )
+ port map (
+ I0 => \m_payload_i[20]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[20]_i_2_n_0\,
+ I3 => m_axi_rdata(17),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[20]_i_3_n_0\,
O => skid_buffer(20)
);
\m_payload_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => m_axi_rdata(49),
- I1 => \m_payload_i[33]_i_2_n_0\,
- I2 => m_axi_rdata(113),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => m_axi_rdata(81),
+ I0 => m_axi_rdata(145),
+ I1 => m_axi_rdata(113),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[20]_i_2_n_0\
);
-\m_payload_i[21]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[20]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(81),
+ I1 => m_axi_rdata(49),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[20]_i_3_n_0\
+ );
+\m_payload_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF222"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => \skid_buffer_reg_n_0_[21]\,
+ I0 => \m_payload_i[21]_i_2_n_0\,
I1 => \^aa_rready\,
- I2 => m_axi_rdata(50),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => \m_payload_i[21]_i_2_n_0\,
+ I2 => \skid_buffer_reg_n_0_[21]\,
+ I3 => m_axi_rdata(18),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[21]_i_3_n_0\,
O => skid_buffer(21)
);
\m_payload_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
- I1 => m_axi_rdata(82),
- I2 => m_axi_rdata(18),
- I3 => \m_payload_i[31]_i_2_n_0\,
- I4 => m_axi_rdata(114),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(146),
+ I1 => m_axi_rdata(114),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[21]_i_2_n_0\
);
-\m_payload_i[22]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[21]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(82),
+ I1 => m_axi_rdata(50),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[21]_i_3_n_0\
+ );
+\m_payload_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(19),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[22]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[22]_i_2_n_0\,
+ I3 => m_axi_rdata(19),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[22]_i_3_n_0\,
O => skid_buffer(22)
);
\m_payload_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(51),
- I2 => m_axi_rdata(83),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(115),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(147),
+ I1 => m_axi_rdata(115),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[22]_i_2_n_0\
);
-\m_payload_i[23]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[22]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(83),
+ I1 => m_axi_rdata(51),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[22]_i_3_n_0\
+ );
+\m_payload_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF222"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => \skid_buffer_reg_n_0_[23]\,
+ I0 => \m_payload_i[23]_i_2_n_0\,
I1 => \^aa_rready\,
- I2 => m_axi_rdata(84),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => \m_payload_i[23]_i_2_n_0\,
+ I2 => \skid_buffer_reg_n_0_[23]\,
+ I3 => m_axi_rdata(20),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[23]_i_3_n_0\,
O => skid_buffer(23)
);
\m_payload_i[23]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(52),
- I2 => m_axi_rdata(20),
- I3 => \m_payload_i[31]_i_2_n_0\,
- I4 => m_axi_rdata(116),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(148),
+ I1 => m_axi_rdata(116),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[23]_i_2_n_0\
);
-\m_payload_i[24]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[23]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"00000AC000000000"
)
port map (
- I0 => m_axi_rdata(21),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(84),
+ I1 => m_axi_rdata(52),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[23]_i_3_n_0\
+ );
+\m_payload_i[24]_i_1\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"FFFFFFFFFFBABABA"
+ )
+ port map (
+ I0 => \m_payload_i[24]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[24]_i_2_n_0\,
+ I3 => m_axi_rdata(21),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[24]_i_3_n_0\,
O => skid_buffer(24)
);
-\m_payload_i[24]_i_2\: unisim.vcomponents.LUT6
+\m_payload_i[24]_i_2\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"000AC00000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(149),
+ I1 => m_axi_rdata(117),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[24]_i_2_n_0\
+ );
+\m_payload_i[24]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"00000AC000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
+ I0 => m_axi_rdata(85),
I1 => m_axi_rdata(53),
- I2 => m_axi_rdata(85),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(117),
- I5 => \m_payload_i[34]_i_4_n_0\,
- O => \m_payload_i[24]_i_2_n_0\
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[24]_i_3_n_0\
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[25]\,
- I3 => m_axi_rdata(86),
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => \m_payload_i[25]_i_2_n_0\,
+ I0 => \m_payload_i[25]_i_2_n_0\,
+ I1 => m_axi_rdata(22),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(150),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[25]_i_3_n_0\,
O => skid_buffer(25)
);
\m_payload_i[25]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[34]_i_4_n_0\,
- I1 => m_axi_rdata(118),
- I2 => m_axi_rdata(54),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(22),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(118),
+ I1 => m_axi_rdata(86),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[25]_i_2_n_0\
);
+\m_payload_i[25]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[25]\,
+ I1 => m_axi_rdata(54),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[25]_i_3_n_0\
+ );
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[26]\,
- I3 => m_axi_rdata(55),
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => \m_payload_i[26]_i_2_n_0\,
+ I0 => \m_payload_i[26]_i_2_n_0\,
+ I1 => m_axi_rdata(23),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(151),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[26]_i_3_n_0\,
O => skid_buffer(26)
);
\m_payload_i[26]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[34]_i_4_n_0\,
- I1 => m_axi_rdata(119),
- I2 => m_axi_rdata(87),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(23),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(119),
+ I1 => m_axi_rdata(87),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[26]_i_2_n_0\
);
-\m_payload_i[27]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[26]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[26]\,
+ I1 => m_axi_rdata(55),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[26]_i_3_n_0\
+ );
+\m_payload_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(24),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[27]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[27]_i_2_n_0\,
+ I3 => m_axi_rdata(24),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[27]_i_3_n_0\,
O => skid_buffer(27)
);
\m_payload_i[27]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(56),
- I2 => m_axi_rdata(88),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(120),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(152),
+ I1 => m_axi_rdata(120),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[27]_i_2_n_0\
);
+\m_payload_i[27]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(88),
+ I1 => m_axi_rdata(56),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[27]_i_3_n_0\
+ );
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[28]\,
- I3 => m_axi_rdata(121),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[28]_i_2_n_0\,
+ I0 => \m_payload_i[28]_i_2_n_0\,
+ I1 => m_axi_rdata(25),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(153),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[28]_i_3_n_0\,
O => skid_buffer(28)
);
\m_payload_i[28]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(121),
I1 => m_axi_rdata(89),
- I2 => m_axi_rdata(57),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(25),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[28]_i_2_n_0\
);
+\m_payload_i[28]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[28]\,
+ I1 => m_axi_rdata(57),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[28]_i_3_n_0\
+ );
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[29]\,
- I3 => m_axi_rdata(58),
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => \m_payload_i[29]_i_2_n_0\,
+ I0 => \m_payload_i[29]_i_2_n_0\,
+ I1 => m_axi_rdata(26),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(154),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[29]_i_3_n_0\,
O => skid_buffer(29)
);
\m_payload_i[29]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(122),
I1 => m_axi_rdata(90),
- I2 => m_axi_rdata(122),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => m_axi_rdata(26),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[29]_i_2_n_0\
);
+\m_payload_i[29]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[29]\,
+ I1 => m_axi_rdata(58),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[29]_i_3_n_0\
+ );
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[2]\,
- I3 => m_axi_rresp(3),
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => \m_payload_i[2]_i_2_n_0\,
+ I0 => \m_payload_i[2]_i_2_n_0\,
+ I1 => m_axi_rresp(1),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rresp(9),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[2]_i_3_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[31]_i_2_n_0\,
- I1 => m_axi_rresp(1),
- I2 => m_axi_rresp(5),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rresp(7),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rresp(7),
+ I1 => m_axi_rresp(5),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[2]_i_2_n_0\
);
+\m_payload_i[2]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[2]\,
+ I1 => m_axi_rresp(3),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[2]_i_3_n_0\
+ );
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[30]\,
- I3 => m_axi_rdata(123),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[30]_i_2_n_0\,
+ I0 => \m_payload_i[30]_i_2_n_0\,
+ I1 => m_axi_rdata(27),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(155),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[30]_i_3_n_0\,
O => skid_buffer(30)
);
\m_payload_i[30]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(59),
- I2 => m_axi_rdata(91),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(27),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(123),
+ I1 => m_axi_rdata(91),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[30]_i_2_n_0\
);
+\m_payload_i[30]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[30]\,
+ I1 => m_axi_rdata(59),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[30]_i_3_n_0\
+ );
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFF8FFF888"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => m_axi_rdata(28),
- I1 => \m_payload_i[31]_i_2_n_0\,
- I2 => \m_payload_i[34]_i_3_n_0\,
- I3 => \^aa_rready\,
- I4 => \skid_buffer_reg_n_0_[31]\,
+ I0 => \m_payload_i[31]_i_2_n_0\,
+ I1 => m_axi_rdata(28),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(156),
+ I4 => \m_payload_i[34]_i_5_n_0\,
I5 => \m_payload_i[31]_i_3_n_0\,
O => skid_buffer(31)
);
-\m_payload_i[31]_i_2\: unisim.vcomponents.LUT4
+\m_payload_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"0002"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \^aa_rready\,
- I1 => m_atarget_enc(2),
- I2 => m_atarget_enc(1),
- I3 => m_atarget_enc(0),
+ I0 => m_axi_rdata(124),
+ I1 => m_axi_rdata(92),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[31]_i_2_n_0\
);
\m_payload_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"00F000C0AAAAAAAA"
)
port map (
- I0 => \m_payload_i[34]_i_4_n_0\,
- I1 => m_axi_rdata(124),
- I2 => m_axi_rdata(60),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(92),
- I5 => \m_payload_i[32]_i_2_n_0\,
+ I0 => \skid_buffer_reg_n_0_[31]\,
+ I1 => m_axi_rdata(60),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[31]_i_3_n_0\
);
-\m_payload_i[32]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[32]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF222"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => \skid_buffer_reg_n_0_[32]\,
+ I0 => \m_payload_i[32]_i_2_n_0\,
I1 => \^aa_rready\,
- I2 => m_axi_rdata(93),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => \m_payload_i[32]_i_3_n_0\,
+ I2 => \skid_buffer_reg_n_0_[32]\,
+ I3 => m_axi_rdata(29),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[32]_i_3_n_0\,
O => skid_buffer(32)
);
-\m_payload_i[32]_i_2\: unisim.vcomponents.LUT4
+\m_payload_i[32]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"0020"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \^aa_rready\,
- I1 => m_atarget_enc(2),
- I2 => m_atarget_enc(1),
- I3 => m_atarget_enc(0),
+ I0 => m_axi_rdata(157),
+ I1 => m_axi_rdata(125),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[32]_i_2_n_0\
);
\m_payload_i[32]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"00000AC000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
+ I0 => m_axi_rdata(93),
I1 => m_axi_rdata(61),
- I2 => m_axi_rdata(29),
- I3 => \m_payload_i[31]_i_2_n_0\,
- I4 => m_axi_rdata(125),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[32]_i_3_n_0\
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[33]\,
- I3 => m_axi_rdata(62),
- I4 => \m_payload_i[33]_i_2_n_0\,
+ I0 => \m_payload_i[33]_i_2_n_0\,
+ I1 => m_axi_rdata(30),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(158),
+ I4 => \m_payload_i[34]_i_5_n_0\,
I5 => \m_payload_i[33]_i_3_n_0\,
O => skid_buffer(33)
);
-\m_payload_i[33]_i_2\: unisim.vcomponents.LUT4
+\m_payload_i[33]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"0008"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \^aa_rready\,
- I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(1),
+ I0 => m_axi_rdata(126),
+ I1 => m_axi_rdata(94),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[33]_i_2_n_0\
);
\m_payload_i[33]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"00F000C0AAAAAAAA"
)
port map (
- I0 => \m_payload_i[32]_i_2_n_0\,
- I1 => m_axi_rdata(94),
- I2 => m_axi_rdata(126),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => m_axi_rdata(30),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \skid_buffer_reg_n_0_[33]\,
+ I1 => m_axi_rdata(62),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[33]_i_3_n_0\
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[34]\,
- I3 => m_axi_rdata(127),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[34]_i_5_n_0\,
+ I1 => m_axi_rdata(31),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(159),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[34]_i_6_n_0\,
O => skid_buffer(34)
);
-\m_payload_i[34]_i_3\: unisim.vcomponents.LUT3
+\m_payload_i[34]_i_3\: unisim.vcomponents.LUT6
generic map(
- INIT => X"04"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => m_atarget_enc(0),
- I1 => m_atarget_enc(2),
- I2 => m_atarget_enc(1),
+ I0 => m_axi_rdata(127),
+ I1 => m_axi_rdata(95),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[34]_i_3_n_0\
);
\m_payload_i[34]_i_4\: unisim.vcomponents.LUT4
generic map(
- INIT => X"0800"
+ INIT => X"0100"
)
port map (
- I0 => \^aa_rready\,
- I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(1),
+ I0 => \m_payload_i_reg[0]_0\(0),
+ I1 => \m_payload_i_reg[0]_0\(1),
+ I2 => \m_payload_i_reg[0]_0\(2),
+ I3 => \^aa_rready\,
O => \m_payload_i[34]_i_4_n_0\
);
-\m_payload_i[34]_i_5\: unisim.vcomponents.LUT6
+\m_payload_i[34]_i_5\: unisim.vcomponents.LUT4
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0400"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(63),
- I2 => m_axi_rdata(95),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(31),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i_reg[0]_0\(0),
+ I1 => \m_payload_i_reg[0]_0\(2),
+ I2 => \m_payload_i_reg[0]_0\(1),
+ I3 => \^aa_rready\,
O => \m_payload_i[34]_i_5_n_0\
);
-\m_payload_i[3]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[34]_i_6\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[34]\,
+ I1 => m_axi_rdata(63),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[34]_i_6_n_0\
+ );
+\m_payload_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(0),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[3]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[3]_i_2_n_0\,
+ I3 => m_axi_rdata(0),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[3]_i_3_n_0\,
O => skid_buffer(3)
);
\m_payload_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => m_axi_rdata(32),
- I1 => \m_payload_i[33]_i_2_n_0\,
- I2 => m_axi_rdata(96),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => m_axi_rdata(64),
+ I0 => m_axi_rdata(128),
+ I1 => m_axi_rdata(96),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[3]_i_2_n_0\
);
-\m_payload_i[4]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[3]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(64),
+ I1 => m_axi_rdata(32),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[3]_i_3_n_0\
+ );
+\m_payload_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(1),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[4]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[4]_i_2_n_0\,
+ I3 => m_axi_rdata(1),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[4]_i_3_n_0\,
O => skid_buffer(4)
);
\m_payload_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => m_axi_rdata(65),
- I1 => \m_payload_i[32]_i_2_n_0\,
- I2 => m_axi_rdata(97),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => \m_payload_i[33]_i_2_n_0\,
- I5 => m_axi_rdata(33),
+ I0 => m_axi_rdata(129),
+ I1 => m_axi_rdata(97),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[4]_i_2_n_0\
);
+\m_payload_i[4]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(65),
+ I1 => m_axi_rdata(33),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[4]_i_3_n_0\
+ );
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[5]\,
- I3 => m_axi_rdata(66),
- I4 => \m_payload_i[32]_i_2_n_0\,
- I5 => \m_payload_i[5]_i_2_n_0\,
+ I0 => \m_payload_i[5]_i_2_n_0\,
+ I1 => m_axi_rdata(2),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(130),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[5]_i_3_n_0\,
O => skid_buffer(5)
);
\m_payload_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[31]_i_2_n_0\,
- I1 => m_axi_rdata(2),
- I2 => m_axi_rdata(98),
- I3 => \m_payload_i[34]_i_4_n_0\,
- I4 => m_axi_rdata(34),
- I5 => \m_payload_i[33]_i_2_n_0\,
+ I0 => m_axi_rdata(98),
+ I1 => m_axi_rdata(66),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[5]_i_2_n_0\
);
+\m_payload_i[5]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[5]\,
+ I1 => m_axi_rdata(34),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[5]_i_3_n_0\
+ );
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFFFB8B8B8"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => \m_payload_i[34]_i_3_n_0\,
- I1 => \^aa_rready\,
- I2 => \skid_buffer_reg_n_0_[6]\,
- I3 => m_axi_rdata(99),
- I4 => \m_payload_i[34]_i_4_n_0\,
- I5 => \m_payload_i[6]_i_2_n_0\,
+ I0 => \m_payload_i[6]_i_2_n_0\,
+ I1 => m_axi_rdata(3),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(131),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[6]_i_3_n_0\,
O => skid_buffer(6)
);
\m_payload_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(35),
- I2 => m_axi_rdata(67),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(3),
- I5 => \m_payload_i[31]_i_2_n_0\,
+ I0 => m_axi_rdata(99),
+ I1 => m_axi_rdata(67),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[6]_i_2_n_0\
);
+\m_payload_i[6]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[6]\,
+ I1 => m_axi_rdata(35),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[6]_i_3_n_0\
+ );
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFFFFFF8FFF888"
+ INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
- I0 => m_axi_rdata(4),
- I1 => \m_payload_i[31]_i_2_n_0\,
- I2 => \m_payload_i[34]_i_3_n_0\,
- I3 => \^aa_rready\,
- I4 => \skid_buffer_reg_n_0_[7]\,
- I5 => \m_payload_i[7]_i_2_n_0\,
+ I0 => \m_payload_i[7]_i_2_n_0\,
+ I1 => m_axi_rdata(4),
+ I2 => \m_payload_i[34]_i_4_n_0\,
+ I3 => m_axi_rdata(132),
+ I4 => \m_payload_i[34]_i_5_n_0\,
+ I5 => \m_payload_i[7]_i_3_n_0\,
O => skid_buffer(7)
);
\m_payload_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"0000AC0000000000"
)
port map (
- I0 => \m_payload_i[34]_i_4_n_0\,
- I1 => m_axi_rdata(100),
- I2 => m_axi_rdata(36),
- I3 => \m_payload_i[33]_i_2_n_0\,
- I4 => m_axi_rdata(68),
- I5 => \m_payload_i[32]_i_2_n_0\,
+ I0 => m_axi_rdata(100),
+ I1 => m_axi_rdata(68),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[7]_i_2_n_0\
);
-\m_payload_i[8]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[7]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00F000C0AAAAAAAA"
+ )
+ port map (
+ I0 => \skid_buffer_reg_n_0_[7]\,
+ I1 => m_axi_rdata(36),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[7]_i_3_n_0\
+ );
+\m_payload_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF88F8"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => m_axi_rdata(5),
- I1 => \m_payload_i[31]_i_2_n_0\,
+ I0 => \m_payload_i[8]_i_2_n_0\,
+ I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
- I3 => \^aa_rready\,
- I4 => \m_payload_i[8]_i_2_n_0\,
+ I3 => m_axi_rdata(5),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[8]_i_3_n_0\,
O => skid_buffer(8)
);
\m_payload_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(37),
- I2 => m_axi_rdata(69),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => m_axi_rdata(101),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(133),
+ I1 => m_axi_rdata(101),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[8]_i_2_n_0\
);
-\m_payload_i[9]_i_1\: unisim.vcomponents.LUT5
+\m_payload_i[8]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(69),
+ I1 => m_axi_rdata(37),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[8]_i_3_n_0\
+ );
+\m_payload_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF222"
+ INIT => X"FFFFFFFFFFBABABA"
)
port map (
- I0 => \skid_buffer_reg_n_0_[9]\,
+ I0 => \m_payload_i[9]_i_2_n_0\,
I1 => \^aa_rready\,
- I2 => m_axi_rdata(70),
- I3 => \m_payload_i[32]_i_2_n_0\,
- I4 => \m_payload_i[9]_i_2_n_0\,
+ I2 => \skid_buffer_reg_n_0_[9]\,
+ I3 => m_axi_rdata(6),
+ I4 => \m_payload_i[34]_i_4_n_0\,
+ I5 => \m_payload_i[9]_i_3_n_0\,
O => skid_buffer(9)
);
\m_payload_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFFF888F888F888"
+ INIT => X"000AC00000000000"
)
port map (
- I0 => \m_payload_i[33]_i_2_n_0\,
- I1 => m_axi_rdata(38),
- I2 => m_axi_rdata(6),
- I3 => \m_payload_i[31]_i_2_n_0\,
- I4 => m_axi_rdata(102),
- I5 => \m_payload_i[34]_i_4_n_0\,
+ I0 => m_axi_rdata(134),
+ I1 => m_axi_rdata(102),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
O => \m_payload_i[9]_i_2_n_0\
);
+\m_payload_i[9]_i_3\: unisim.vcomponents.LUT6
+ generic map(
+ INIT => X"00000AC000000000"
+ )
+ port map (
+ I0 => m_axi_rdata(70),
+ I1 => m_axi_rdata(38),
+ I2 => \m_payload_i_reg[0]_0\(0),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(2),
+ I5 => \^aa_rready\,
+ O => \m_payload_i[9]_i_3_n_0\
+ );
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
@@ -3401,30 +4157,28 @@ begin
Q => \^q\(9),
R => '0'
);
-\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
+m_valid_i_i_4: unisim.vcomponents.LUT5
generic map(
- INIT => X"000000007FFFFFFF"
+ INIT => X"0C0000A0"
)
port map (
- I0 => \^sr_rvalid\,
- I1 => \^q\(0),
- I2 => s_axi_rready(0),
- I3 => aa_grant_rnw,
- I4 => m_valid_i,
- I5 => m_ready_d(0),
- O => m_valid_i_reg_0
+ I0 => m_axi_rvalid(3),
+ I1 => m_axi_rvalid(2),
+ I2 => \m_payload_i_reg[0]_0\(2),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(0),
+ O => \m_axi_rvalid[4]\
);
-m_valid_i_i_4: unisim.vcomponents.LUT6
+m_valid_i_i_6: unisim.vcomponents.LUT5
generic map(
- INIT => X"00CA000F00CA0000"
+ INIT => X"000C0A00"
)
port map (
I0 => m_axi_rvalid(1),
- I1 => m_axi_rvalid(2),
- I2 => m_atarget_enc(0),
- I3 => m_atarget_enc(2),
- I4 => m_atarget_enc(1),
- I5 => m_axi_rvalid(0),
+ I1 => m_axi_rvalid(0),
+ I2 => \m_payload_i_reg[0]_0\(2),
+ I3 => \m_payload_i_reg[0]_0\(1),
+ I4 => \m_payload_i_reg[0]_0\(0),
O => m_axi_rvalid_2_sn_1
);
m_valid_i_reg: unisim.vcomponents.FDRE
@@ -3434,19 +4188,10 @@ m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
- D => m_valid_i_reg_1,
+ D => m_valid_i_reg_0,
Q => \^sr_rvalid\,
R => '0'
);
-\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
- generic map(
- INIT => X"2"
- )
- port map (
- I0 => \^sr_rvalid\,
- I1 => p_0_in1_in,
- O => s_axi_rvalid(0)
- );
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
@@ -3458,16 +4203,15 @@ s_ready_i_reg: unisim.vcomponents.FDRE
Q => \^aa_rready\,
R => '0'
);
-\skid_buffer[0]_i_1\: unisim.vcomponents.LUT5
+\skid_buffer[0]_i_1\: unisim.vcomponents.LUT4
generic map(
- INIT => X"03FFAAAA"
+ INIT => X"2EEE"
)
port map (
I0 => \skid_buffer_reg_n_0_[0]\,
- I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(1),
- I3 => m_atarget_enc(2),
- I4 => \^aa_rready\,
+ I1 => \^aa_rready\,
+ I2 => \m_payload_i_reg[0]_0\(2),
+ I3 => \m_payload_i_reg[0]_0\(1),
O => skid_buffer(0)
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
@@ -3759,140 +4503,139 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
- s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 );
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
- s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
+ s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd : entity is "axi_crossbar_v2_1_33_crossbar_sasd";
end mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd;
architecture STRUCTURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd is
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
- signal addr_arbiter_inst_n_10 : STD_LOGIC;
- signal addr_arbiter_inst_n_4 : STD_LOGIC;
- signal addr_arbiter_inst_n_5 : STD_LOGIC;
- signal addr_arbiter_inst_n_52 : STD_LOGIC;
- signal addr_arbiter_inst_n_60 : STD_LOGIC;
- signal addr_arbiter_inst_n_61 : STD_LOGIC;
- signal addr_arbiter_inst_n_62 : STD_LOGIC;
- signal addr_arbiter_inst_n_63 : STD_LOGIC;
- signal addr_arbiter_inst_n_69 : STD_LOGIC;
- signal addr_arbiter_inst_n_70 : STD_LOGIC;
- signal addr_arbiter_inst_n_73 : STD_LOGIC;
- signal addr_arbiter_inst_n_74 : STD_LOGIC;
- signal addr_arbiter_inst_n_9 : STD_LOGIC;
- signal any_error : STD_LOGIC;
+ signal addr_arbiter_inst_n_21 : STD_LOGIC;
+ signal addr_arbiter_inst_n_22 : STD_LOGIC;
+ signal addr_arbiter_inst_n_24 : STD_LOGIC;
+ signal addr_arbiter_inst_n_36 : STD_LOGIC;
+ signal addr_arbiter_inst_n_37 : STD_LOGIC;
+ signal addr_arbiter_inst_n_38 : STD_LOGIC;
+ signal addr_arbiter_inst_n_80 : STD_LOGIC;
+ signal addr_arbiter_inst_n_81 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
- signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
- signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
+ signal f_mux_return2 : STD_LOGIC;
+ signal f_mux_return3 : STD_LOGIC;
+ signal \f_mux_return__1\ : STD_LOGIC;
+ signal \f_mux_return__3\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
- signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
- signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal m_atarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
- signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal m_atarget_hot : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 );
- signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 0 to 0 );
+ signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m_ready_d0_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_ready_d_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
- signal mi_bvalid : STD_LOGIC_VECTOR ( 4 to 4 );
- signal mi_wready : STD_LOGIC_VECTOR ( 4 to 4 );
- signal p_0_in1_in : STD_LOGIC;
+ signal mi_arvalid_en : STD_LOGIC;
+ signal mi_bvalid : STD_LOGIC_VECTOR ( 5 to 5 );
+ signal mi_wready : STD_LOGIC_VECTOR ( 5 to 5 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_2 : STD_LOGIC;
signal reg_slice_r_n_37 : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
- signal reg_slice_r_n_43 : STD_LOGIC;
- signal reg_slice_r_n_44 : STD_LOGIC;
+ signal reg_slice_r_n_39 : STD_LOGIC;
+ signal reg_slice_r_n_45 : STD_LOGIC;
+ signal reg_slice_r_n_46 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal splitter_ar_n_0 : STD_LOGIC;
+ signal splitter_ar_n_1 : STD_LOGIC;
+ signal splitter_aw_n_0 : STD_LOGIC;
+ signal splitter_aw_n_1 : STD_LOGIC;
+ signal splitter_aw_n_2 : STD_LOGIC;
signal splitter_aw_n_3 : STD_LOGIC;
signal splitter_aw_n_4 : STD_LOGIC;
+ signal splitter_aw_n_5 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
+ attribute SOFT_HLUTNM : string;
+ attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_2\ : label is "soft_lutpair23";
+ attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_3\ : label is "soft_lutpair23";
begin
addr_arbiter_inst: entity work.mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbiter_sasd
port map (
- D(3) => addr_arbiter_inst_n_5,
- D(2 downto 0) => m_atarget_hot0(2 downto 0),
+ D(2) => addr_arbiter_inst_n_36,
+ D(1) => addr_arbiter_inst_n_37,
+ D(0) => addr_arbiter_inst_n_38,
E(0) => p_1_in,
- Q(34 downto 0) => Q(34 downto 0),
+ Q(5 downto 0) => m_atarget_hot(5 downto 0),
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
- aresetn_d_reg => addr_arbiter_inst_n_4,
- \aresetn_d_reg[0]\ => addr_arbiter_inst_n_62,
- \aresetn_d_reg[1]\ => addr_arbiter_inst_n_63,
- aresetn_d_reg_0 => addr_arbiter_inst_n_9,
- aresetn_d_reg_1 => addr_arbiter_inst_n_10,
- \gen_axilite.s_axi_awready_i_reg\ => addr_arbiter_inst_n_73,
- \gen_axilite.s_axi_bvalid_i_reg\(3) => m_atarget_hot(4),
- \gen_axilite.s_axi_bvalid_i_reg\(2 downto 0) => m_atarget_hot(2 downto 0),
- \gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_61,
- \gen_no_arbiter.grant_rnw_reg_1\ => addr_arbiter_inst_n_70,
- \gen_no_arbiter.m_amesg_i_reg[19]_0\(0) => any_error,
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_0\ => \gen_decerr.decerr_slave_inst_n_8\,
- \gen_no_arbiter.m_grant_hot_i[0]_inv_i_2_1\ => reg_slice_r_n_2,
- \gen_no_arbiter.m_valid_i_reg_0\ => splitter_aw_n_3,
- m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
- m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
- m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
- m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
- m_axi_wready(1 downto 0) => m_axi_wready(3 downto 2),
- m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
+ \aresetn_d_reg[0]\ => addr_arbiter_inst_n_22,
+ \aresetn_d_reg[1]\ => addr_arbiter_inst_n_24,
+ \f_mux_return__1\ => \f_mux_return__1\,
+ \f_mux_return__3\ => \f_mux_return__3\,
+ \gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_81,
+ \gen_no_arbiter.grant_rnw_reg_0\(0) => m_ready_d0_0(2),
+ \gen_no_arbiter.m_amesg_i_reg[48]_0\(34 downto 0) => Q(34 downto 0),
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\(5 downto 0) => m_atarget_hot0(5 downto 0),
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\ => reg_slice_r_n_2,
+ \gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_inst_n_21,
+ \gen_no_arbiter.m_valid_i_reg_1\ => splitter_aw_n_2,
+ \gen_no_arbiter.m_valid_i_reg_2\ => \gen_decerr.decerr_slave_inst_n_8\,
+ \gen_no_arbiter.m_valid_i_reg_3\ => splitter_aw_n_5,
+ \m_atarget_hot_reg[5]\ => addr_arbiter_inst_n_80,
+ m_axi_arvalid(4 downto 0) => m_axi_arvalid(4 downto 0),
+ m_axi_awvalid(4 downto 0) => m_axi_awvalid(4 downto 0),
+ m_axi_bready(4 downto 0) => m_axi_bready(4 downto 0),
+ m_axi_wvalid(4 downto 0) => m_axi_wvalid(4 downto 0),
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
- m_ready_d0(0) => m_ready_d0_0(0),
- m_ready_d0_0(0) => m_ready_d0(1),
- \m_ready_d[2]_i_3\ => \gen_decerr.decerr_slave_inst_n_4\,
- \m_ready_d[2]_i_3_0\ => splitter_aw_n_4,
+ m_ready_d0(1 downto 0) => m_ready_d0(1 downto 0),
+ m_ready_d0_0(1 downto 0) => m_ready_d0_0(1 downto 0),
m_ready_d_1(1 downto 0) => m_ready_d(1 downto 0),
- \m_ready_d_reg[1]\ => addr_arbiter_inst_n_69,
- \m_ready_d_reg[1]_0\ => splitter_ar_n_0,
+ \m_ready_d_reg[1]\(0) => reg_slice_r_n_37,
+ \m_ready_d_reg[1]_0\ => splitter_ar_n_1,
\m_ready_d_reg[1]_1\ => \gen_decerr.decerr_slave_inst_n_5\,
- \m_ready_d_reg[2]\ => addr_arbiter_inst_n_74,
+ \m_ready_d_reg[1]_2\ => splitter_ar_n_0,
m_valid_i => m_valid_i,
- m_valid_i_reg(1) => reg_slice_r_n_43,
- m_valid_i_reg(0) => reg_slice_r_n_44,
- m_valid_i_reg_0 => reg_slice_r_n_38,
- m_valid_i_reg_1 => \gen_decerr.decerr_slave_inst_n_6\,
- mi_bvalid(0) => mi_bvalid(4),
- mi_wready(0) => mi_wready(4),
- p_0_in1_in => p_0_in1_in,
+ m_valid_i_reg(1) => reg_slice_r_n_45,
+ m_valid_i_reg(0) => reg_slice_r_n_46,
+ m_valid_i_reg_0 => reg_slice_r_n_39,
+ m_valid_i_reg_1 => \gen_decerr.decerr_slave_inst_n_4\,
+ m_valid_i_reg_2 => reg_slice_r_n_38,
+ mi_arvalid_en => mi_arvalid_en,
+ mi_bvalid(0) => mi_bvalid(5),
+ mi_wready(0) => mi_wready(5),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
@@ -3902,14 +4645,11 @@ addr_arbiter_inst: entity work.mb_design_1_xbar_0_axi_crossbar_v2_1_33_addr_arbi
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
- s_axi_bready_0_sp_1 => addr_arbiter_inst_n_60,
s_axi_bvalid(0) => s_axi_bvalid(0),
- s_axi_bvalid_0_sp_1 => \gen_decerr.decerr_slave_inst_n_3\,
s_axi_rready(0) => s_axi_rready(0),
+ s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
- s_axi_wready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_7\,
s_axi_wvalid(0) => s_axi_wvalid(0),
- s_axi_wvalid_0_sp_1 => addr_arbiter_inst_n_52,
sr_rvalid => sr_rvalid
);
aresetn_d_reg: unisim.vcomponents.FDRE
@@ -3925,29 +4665,40 @@ aresetn_d_reg: unisim.vcomponents.FDRE
);
\gen_decerr.decerr_slave_inst\: entity work.mb_design_1_xbar_0_axi_crossbar_v2_1_33_decerr_slave
port map (
- Q(0) => m_atarget_hot(4),
+ Q(0) => m_atarget_hot(5),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
- \gen_axilite.s_axi_arready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_5\,
- \gen_axilite.s_axi_awready_i_reg_0\ => addr_arbiter_inst_n_74,
- \gen_axilite.s_axi_bvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_3\,
- \gen_axilite.s_axi_bvalid_i_reg_1\ => addr_arbiter_inst_n_73,
- \gen_axilite.s_axi_rvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_6\,
- \gen_axilite.s_axi_rvalid_i_reg_1\ => addr_arbiter_inst_n_69,
- m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
- \m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_2\,
- m_axi_arready(0) => m_axi_arready(2),
- m_axi_bvalid(0) => m_axi_bvalid(2),
- \m_axi_bvalid[2]\ => \gen_decerr.decerr_slave_inst_n_4\,
- m_axi_rvalid(0) => m_axi_rvalid(1),
- m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
- m_axi_wready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_8\,
- m_axi_wready_3_sp_1 => \gen_decerr.decerr_slave_inst_n_7\,
- \m_ready_d_reg[0]\ => splitter_aw_n_4,
- mi_bvalid(0) => mi_bvalid(4),
- mi_wready(0) => mi_wready(4)
+ f_mux_return2 => f_mux_return2,
+ f_mux_return3 => f_mux_return3,
+ \f_mux_return__1\ => \f_mux_return__1\,
+ \f_mux_return__3\ => \f_mux_return__3\,
+ \gen_axilite.s_axi_awready_i_reg_0\ => addr_arbiter_inst_n_81,
+ \gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_80,
+ m_axi_arready(0) => m_axi_arready(0),
+ m_axi_arready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_5\,
+ m_axi_awready(0) => m_axi_awready(0),
+ m_axi_awready_0_sp_1 => \gen_decerr.decerr_slave_inst_n_8\,
+ m_axi_bvalid(2 downto 1) => m_axi_bvalid(4 downto 3),
+ m_axi_bvalid(0) => m_axi_bvalid(0),
+ m_axi_rvalid(0) => m_axi_rvalid(0),
+ m_axi_rvalid_0_sp_1 => \gen_decerr.decerr_slave_inst_n_4\,
+ m_axi_wready(2 downto 1) => m_axi_wready(4 downto 3),
+ m_axi_wready(0) => m_axi_wready(0),
+ m_ready_d(1 downto 0) => m_ready_d_1(1 downto 0),
+ m_ready_d0(1 downto 0) => m_ready_d0_0(1 downto 0),
+ \m_ready_d[2]_i_2\(2 downto 0) => m_atarget_enc(2 downto 0),
+ \m_ready_d_reg[2]\ => splitter_aw_n_3,
+ \m_ready_d_reg[2]_0\ => splitter_aw_n_0,
+ \m_ready_d_reg[2]_1\ => addr_arbiter_inst_n_21,
+ \m_ready_d_reg[2]_2\ => splitter_aw_n_4,
+ \m_ready_d_reg[2]_3\ => splitter_aw_n_1,
+ mi_arvalid_en => mi_arvalid_en,
+ mi_bvalid(0) => mi_bvalid(5),
+ mi_wready(0) => mi_wready(5),
+ s_axi_bready(0) => s_axi_bready(0),
+ s_axi_wvalid(0) => s_axi_wvalid(0)
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
@@ -3956,7 +4707,7 @@ aresetn_d_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
- D => addr_arbiter_inst_n_9,
+ D => addr_arbiter_inst_n_38,
Q => m_atarget_enc(0),
R => '0'
);
@@ -3967,7 +4718,7 @@ aresetn_d_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
- D => addr_arbiter_inst_n_10,
+ D => addr_arbiter_inst_n_37,
Q => m_atarget_enc(1),
R => '0'
);
@@ -3978,9 +4729,9 @@ aresetn_d_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
- D => any_error,
+ D => addr_arbiter_inst_n_36,
Q => m_atarget_enc(2),
- R => reset
+ R => '0'
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
@@ -4015,6 +4766,17 @@ aresetn_d_reg: unisim.vcomponents.FDRE
Q => m_atarget_hot(2),
R => reset
);
+\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => m_atarget_hot0(3),
+ Q => m_atarget_hot(3),
+ R => reset
+ );
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
@@ -4022,10 +4784,21 @@ aresetn_d_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
- D => addr_arbiter_inst_n_5,
+ D => m_atarget_hot0(4),
Q => m_atarget_hot(4),
R => reset
);
+\m_atarget_hot_reg[5]\: unisim.vcomponents.FDRE
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => aclk,
+ CE => '1',
+ D => m_atarget_hot0(5),
+ Q => m_atarget_hot(5),
+ R => reset
+ );
reg_slice_r: entity work.mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_register_slice
port map (
E(0) => p_1_in,
@@ -4035,111 +4808,127 @@ reg_slice_r: entity work.mb_design_1_xbar_0_axi_register_slice_v2_1_32_axic_regi
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
- \aresetn_d_reg[1]_0\(1) => reg_slice_r_n_43,
- \aresetn_d_reg[1]_0\(0) => reg_slice_r_n_44,
- m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
- m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
- m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
- \m_axi_rready[2]\(2 downto 0) => m_atarget_hot(2 downto 0),
- m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
- m_axi_rvalid(2 downto 1) => m_axi_rvalid(3 downto 2),
- m_axi_rvalid(0) => m_axi_rvalid(0),
+ \aresetn_d_reg[1]_0\(1) => reg_slice_r_n_45,
+ \aresetn_d_reg[1]_0\(0) => reg_slice_r_n_46,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv\ => splitter_ar_n_0,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_0\ => \gen_decerr.decerr_slave_inst_n_5\,
+ \gen_no_arbiter.m_grant_hot_i_reg[0]_inv_1\ => splitter_ar_n_1,
+ m_axi_rdata(159 downto 0) => m_axi_rdata(159 downto 0),
+ m_axi_rready(4 downto 0) => m_axi_rready(4 downto 0),
+ \m_axi_rready[4]\(4 downto 0) => m_atarget_hot(4 downto 0),
+ m_axi_rresp(9 downto 0) => m_axi_rresp(9 downto 0),
+ m_axi_rvalid(3 downto 0) => m_axi_rvalid(4 downto 1),
+ \m_axi_rvalid[4]\ => reg_slice_r_n_39,
m_axi_rvalid_2_sp_1 => reg_slice_r_n_38,
- m_ready_d(0) => m_ready_d(0),
+ \m_payload_i_reg[0]_0\(2 downto 0) => m_atarget_enc(2 downto 0),
+ m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
+ \m_ready_d_reg[1]\ => reg_slice_r_n_2,
m_valid_i => m_valid_i,
- m_valid_i_reg_0 => reg_slice_r_n_2,
- m_valid_i_reg_1 => addr_arbiter_inst_n_63,
- p_0_in1_in => p_0_in1_in,
+ m_valid_i_reg_0 => addr_arbiter_inst_n_24,
+ mi_arvalid_en => mi_arvalid_en,
s_axi_rready(0) => s_axi_rready(0),
- s_axi_rvalid(0) => s_axi_rvalid(0),
- s_ready_i_reg_0 => addr_arbiter_inst_n_62,
+ s_ready_i_reg_0 => addr_arbiter_inst_n_22,
sr_rvalid => sr_rvalid
);
-\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT5
+\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF0038"
+ INIT => X"AABEAABAAAAEAAAA"
)
port map (
- I0 => m_axi_bresp(2),
+ I0 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
I1 => m_atarget_enc(0),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(1),
- I4 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
+ I2 => m_atarget_enc(1),
+ I3 => m_atarget_enc(2),
+ I4 => m_axi_bresp(2),
+ I5 => m_axi_bresp(4),
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"00CA000F00CA0000"
+ INIT => X"0FF00A0C0F000A0C"
)
port map (
- I0 => m_axi_bresp(4),
- I1 => m_axi_bresp(6),
- I2 => m_atarget_enc(0),
+ I0 => m_axi_bresp(8),
+ I1 => m_axi_bresp(0),
+ I2 => m_atarget_enc(1),
I3 => m_atarget_enc(2),
- I4 => m_atarget_enc(1),
- I5 => m_axi_bresp(0),
+ I4 => m_atarget_enc(0),
+ I5 => m_axi_bresp(6),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
-\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT5
+\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
- INIT => X"FFFF000E"
+ INIT => X"AABEAABAAAAEAAAA"
)
port map (
- I0 => m_axi_bresp(1),
- I1 => m_atarget_enc(2),
+ I0 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
+ I1 => m_atarget_enc(0),
I2 => m_atarget_enc(1),
- I3 => m_atarget_enc(0),
- I4 => \s_axi_bresp[1]_INST_0_i_1_n_0\,
+ I3 => m_atarget_enc(2),
+ I4 => m_axi_bresp(3),
+ I5 => m_axi_bresp(5),
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
- INIT => X"0A0F0C000A000C00"
+ INIT => X"0FF00A0C0F000A0C"
)
port map (
- I0 => m_axi_bresp(7),
- I1 => m_axi_bresp(5),
- I2 => m_atarget_enc(2),
- I3 => m_atarget_enc(1),
+ I0 => m_axi_bresp(9),
+ I1 => m_axi_bresp(1),
+ I2 => m_atarget_enc(1),
+ I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
- I5 => m_axi_bresp(3),
+ I5 => m_axi_bresp(7),
O => \s_axi_bresp[1]_INST_0_i_1_n_0\
);
+\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"04"
+ )
+ port map (
+ I0 => m_atarget_enc(1),
+ I1 => m_atarget_enc(2),
+ I2 => m_atarget_enc(0),
+ O => f_mux_return2
+ );
+\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT3
+ generic map(
+ INIT => X"40"
+ )
+ port map (
+ I0 => m_atarget_enc(2),
+ I1 => m_atarget_enc(1),
+ I2 => m_atarget_enc(0),
+ O => f_mux_return3
+ );
splitter_ar: entity work.\mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter__parameterized0\
port map (
- Q(0) => reg_slice_r_n_37,
+ Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
- m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
- m_axi_arready(2) => m_axi_arready(3),
- m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
- m_axi_arready_1_sp_1 => splitter_ar_n_0,
+ m_axi_arready(3 downto 0) => m_axi_arready(4 downto 1),
+ \m_axi_arready[4]\ => splitter_ar_n_1,
+ m_axi_arready_2_sp_1 => splitter_ar_n_0,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
- m_ready_d0(0) => m_ready_d0(1),
- \m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_70,
- \m_ready_d_reg[0]_1\ => addr_arbiter_inst_n_4,
- \m_ready_d_reg[1]_0\ => reg_slice_r_n_2,
- s_axi_rready(0) => s_axi_rready(0),
- sr_rvalid => sr_rvalid
+ m_ready_d0(1 downto 0) => m_ready_d0(1 downto 0)
);
splitter_aw: entity work.mb_design_1_xbar_0_axi_crossbar_v2_1_33_splitter
port map (
+ Q(2 downto 0) => m_atarget_enc(2 downto 0),
aclk => aclk,
aresetn_d => aresetn_d,
- m_atarget_enc(2 downto 0) => m_atarget_enc(2 downto 0),
- m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
- m_axi_bvalid(2) => m_axi_bvalid(3),
- m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
- m_axi_bvalid_0_sp_1 => splitter_aw_n_4,
+ m_axi_awready(3 downto 0) => m_axi_awready(4 downto 1),
+ \m_axi_awready[4]\ => splitter_aw_n_5,
+ m_axi_awready_2_sp_1 => splitter_aw_n_2,
+ m_axi_bvalid(3 downto 0) => m_axi_bvalid(4 downto 1),
+ \m_axi_bvalid[4]\ => splitter_aw_n_3,
+ m_axi_bvalid_2_sp_1 => splitter_aw_n_0,
+ m_axi_wready(3 downto 0) => m_axi_wready(4 downto 1),
+ \m_axi_wready[4]\ => splitter_aw_n_4,
+ m_axi_wready_2_sp_1 => splitter_aw_n_1,
m_ready_d(2 downto 0) => m_ready_d_1(2 downto 0),
- m_ready_d0(0) => m_ready_d0_0(0),
- \m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_60,
- \m_ready_d_reg[0]_1\ => \gen_decerr.decerr_slave_inst_n_3\,
- \m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_7\,
- \m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_52,
- \m_ready_d_reg[2]_0\ => splitter_aw_n_3,
- \m_ready_d_reg[2]_1\ => addr_arbiter_inst_n_61,
- \m_ready_d_reg[2]_2\ => \gen_decerr.decerr_slave_inst_n_2\
+ m_ready_d0(2 downto 0) => m_ready_d0_0(2 downto 0)
);
end STRUCTURE;
library IEEE;
@@ -4193,51 +4982,51 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar is
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
- m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
- m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ m_axi_awid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_awlen : out STD_LOGIC_VECTOR ( 39 downto 0 );
+ m_axi_awsize : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_awburst : out STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_awlock : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awcache : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_awregion : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_awqos : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_awuser : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_wlast : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wuser : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_buser : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_arlen : out STD_LOGIC_VECTOR ( 39 downto 0 );
+ m_axi_arsize : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_arburst : out STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_arlock : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arcache : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_arregion : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_arqos : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_aruser : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rlast : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_ruser : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 32;
@@ -4266,23 +5055,23 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar is
attribute C_FAMILY : string;
attribute C_FAMILY of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "artix7";
attribute C_M_AXI_ADDR_WIDTH : string;
- attribute C_M_AXI_ADDR_WIDTH of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100";
+ attribute C_M_AXI_ADDR_WIDTH of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000011100000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
- attribute C_M_AXI_BASE_ADDR of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "256'b1111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000";
+ attribute C_M_AXI_BASE_ADDR of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "320'b00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
- attribute C_M_AXI_READ_CONNECTIVITY of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_READ_CONNECTIVITY of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
- attribute C_M_AXI_READ_ISSUING of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_READ_ISSUING of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
- attribute C_M_AXI_SECURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_M_AXI_SECURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
- attribute C_M_AXI_WRITE_CONNECTIVITY of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_WRITE_CONNECTIVITY of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
- attribute C_M_AXI_WRITE_ISSUING of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_WRITE_ISSUING of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
- attribute C_NUM_MASTER_SLOTS of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 4;
+ attribute C_NUM_MASTER_SLOTS of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 5;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
@@ -4301,8 +5090,6 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar is
attribute C_S_AXI_WRITE_ACCEPTANCE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "yes";
- attribute ORIG_REF_NAME : string;
- attribute ORIG_REF_NAME of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "axi_crossbar_v2_1_33_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
@@ -4322,11 +5109,11 @@ entity mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar is
attribute P_LOCK : integer;
attribute P_LOCK of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
- attribute P_M_AXI_ERR_MODE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute P_M_AXI_ERR_MODE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
- attribute P_M_AXI_SUPPORTS_READ of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "4'b1111";
+ attribute P_M_AXI_SUPPORTS_READ of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "5'b11111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
- attribute P_M_AXI_SUPPORTS_WRITE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "4'b1111";
+ attribute P_M_AXI_SUPPORTS_WRITE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "5'b11111";
attribute P_ONES : string;
attribute P_ONES of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
@@ -4343,27 +5130,26 @@ end mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar;
architecture STRUCTURE of mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
- signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 11 downto 0 );
+ signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_arvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 108 );
- signal \^m_axi_awvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_rready\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_wvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 159 downto 135 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
- m_axi_araddr(127 downto 108) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_araddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
- m_axi_araddr(95 downto 76) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_araddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
- m_axi_araddr(63 downto 44) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_araddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
- m_axi_araddr(31 downto 12) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_araddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
+ m_axi_araddr(159 downto 135) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_araddr(134 downto 128) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_araddr(127 downto 103) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_araddr(102 downto 96) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_araddr(95 downto 71) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_araddr(70 downto 64) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_araddr(63 downto 39) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_araddr(38 downto 32) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_araddr(31 downto 7) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_araddr(6 downto 0) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_arburst(9) <= \<const0>\;
+ m_axi_arburst(8) <= \<const0>\;
m_axi_arburst(7) <= \<const0>\;
m_axi_arburst(6) <= \<const0>\;
m_axi_arburst(5) <= \<const0>\;
@@ -4372,6 +5158,10 @@ begin
m_axi_arburst(2) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
+ m_axi_arcache(19) <= \<const0>\;
+ m_axi_arcache(18) <= \<const0>\;
+ m_axi_arcache(17) <= \<const0>\;
+ m_axi_arcache(16) <= \<const0>\;
m_axi_arcache(15) <= \<const0>\;
m_axi_arcache(14) <= \<const0>\;
m_axi_arcache(13) <= \<const0>\;
@@ -4388,10 +5178,19 @@ begin
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
+ m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
+ m_axi_arlen(39) <= \<const0>\;
+ m_axi_arlen(38) <= \<const0>\;
+ m_axi_arlen(37) <= \<const0>\;
+ m_axi_arlen(36) <= \<const0>\;
+ m_axi_arlen(35) <= \<const0>\;
+ m_axi_arlen(34) <= \<const0>\;
+ m_axi_arlen(33) <= \<const0>\;
+ m_axi_arlen(32) <= \<const0>\;
m_axi_arlen(31) <= \<const0>\;
m_axi_arlen(30) <= \<const0>\;
m_axi_arlen(29) <= \<const0>\;
@@ -4424,14 +5223,20 @@ begin
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
+ m_axi_arlock(4) <= \<const0>\;
m_axi_arlock(3) <= \<const0>\;
m_axi_arlock(2) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
+ m_axi_arprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
+ m_axi_arqos(19) <= \<const0>\;
+ m_axi_arqos(18) <= \<const0>\;
+ m_axi_arqos(17) <= \<const0>\;
+ m_axi_arqos(16) <= \<const0>\;
m_axi_arqos(15) <= \<const0>\;
m_axi_arqos(14) <= \<const0>\;
m_axi_arqos(13) <= \<const0>\;
@@ -4448,6 +5253,10 @@ begin
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
+ m_axi_arregion(19) <= \<const0>\;
+ m_axi_arregion(18) <= \<const0>\;
+ m_axi_arregion(17) <= \<const0>\;
+ m_axi_arregion(16) <= \<const0>\;
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
@@ -4464,6 +5273,9 @@ begin
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
+ m_axi_arsize(14) <= \<const0>\;
+ m_axi_arsize(13) <= \<const0>\;
+ m_axi_arsize(12) <= \<const0>\;
m_axi_arsize(11) <= \<const0>\;
m_axi_arsize(10) <= \<const0>\;
m_axi_arsize(9) <= \<const0>\;
@@ -4476,20 +5288,23 @@ begin
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
+ m_axi_aruser(4) <= \<const0>\;
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
- m_axi_arvalid(3) <= \<const0>\;
- m_axi_arvalid(2 downto 0) <= \^m_axi_arvalid\(2 downto 0);
- m_axi_awaddr(127 downto 108) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_awaddr(107 downto 96) <= \^m_axi_araddr\(11 downto 0);
- m_axi_awaddr(95 downto 76) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_awaddr(75 downto 64) <= \^m_axi_araddr\(11 downto 0);
- m_axi_awaddr(63 downto 44) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_awaddr(43 downto 32) <= \^m_axi_araddr\(11 downto 0);
- m_axi_awaddr(31 downto 12) <= \^m_axi_awaddr\(127 downto 108);
- m_axi_awaddr(11 downto 0) <= \^m_axi_araddr\(11 downto 0);
+ m_axi_awaddr(159 downto 135) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_awaddr(134 downto 128) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_awaddr(127 downto 103) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_awaddr(102 downto 96) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_awaddr(95 downto 71) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_awaddr(70 downto 64) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_awaddr(63 downto 39) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_awaddr(38 downto 32) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_awaddr(31 downto 7) <= \^m_axi_awaddr\(159 downto 135);
+ m_axi_awaddr(6 downto 0) <= \^m_axi_araddr\(6 downto 0);
+ m_axi_awburst(9) <= \<const0>\;
+ m_axi_awburst(8) <= \<const0>\;
m_axi_awburst(7) <= \<const0>\;
m_axi_awburst(6) <= \<const0>\;
m_axi_awburst(5) <= \<const0>\;
@@ -4498,6 +5313,10 @@ begin
m_axi_awburst(2) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
+ m_axi_awcache(19) <= \<const0>\;
+ m_axi_awcache(18) <= \<const0>\;
+ m_axi_awcache(17) <= \<const0>\;
+ m_axi_awcache(16) <= \<const0>\;
m_axi_awcache(15) <= \<const0>\;
m_axi_awcache(14) <= \<const0>\;
m_axi_awcache(13) <= \<const0>\;
@@ -4514,10 +5333,19 @@ begin
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
+ m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
+ m_axi_awlen(39) <= \<const0>\;
+ m_axi_awlen(38) <= \<const0>\;
+ m_axi_awlen(37) <= \<const0>\;
+ m_axi_awlen(36) <= \<const0>\;
+ m_axi_awlen(35) <= \<const0>\;
+ m_axi_awlen(34) <= \<const0>\;
+ m_axi_awlen(33) <= \<const0>\;
+ m_axi_awlen(32) <= \<const0>\;
m_axi_awlen(31) <= \<const0>\;
m_axi_awlen(30) <= \<const0>\;
m_axi_awlen(29) <= \<const0>\;
@@ -4550,14 +5378,20 @@ begin
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
+ m_axi_awlock(4) <= \<const0>\;
m_axi_awlock(3) <= \<const0>\;
m_axi_awlock(2) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
+ m_axi_awprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
+ m_axi_awqos(19) <= \<const0>\;
+ m_axi_awqos(18) <= \<const0>\;
+ m_axi_awqos(17) <= \<const0>\;
+ m_axi_awqos(16) <= \<const0>\;
m_axi_awqos(15) <= \<const0>\;
m_axi_awqos(14) <= \<const0>\;
m_axi_awqos(13) <= \<const0>\;
@@ -4574,6 +5408,10 @@ begin
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
+ m_axi_awregion(19) <= \<const0>\;
+ m_axi_awregion(18) <= \<const0>\;
+ m_axi_awregion(17) <= \<const0>\;
+ m_axi_awregion(16) <= \<const0>\;
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
@@ -4590,6 +5428,9 @@ begin
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
+ m_axi_awsize(14) <= \<const0>\;
+ m_axi_awsize(13) <= \<const0>\;
+ m_axi_awsize(12) <= \<const0>\;
m_axi_awsize(11) <= \<const0>\;
m_axi_awsize(10) <= \<const0>\;
m_axi_awsize(9) <= \<const0>\;
@@ -4602,38 +5443,36 @@ begin
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
+ m_axi_awuser(4) <= \<const0>\;
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
- m_axi_awvalid(3) <= \<const0>\;
- m_axi_awvalid(2 downto 0) <= \^m_axi_awvalid\(2 downto 0);
- m_axi_bready(3) <= \<const0>\;
- m_axi_bready(2 downto 0) <= \^m_axi_bready\(2 downto 0);
- m_axi_rready(3) <= \<const0>\;
- m_axi_rready(2 downto 0) <= \^m_axi_rready\(2 downto 0);
+ m_axi_wdata(159 downto 128) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
+ m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
+ m_axi_wlast(4) <= \<const0>\;
m_axi_wlast(3) <= \<const0>\;
m_axi_wlast(2) <= \<const0>\;
m_axi_wlast(1) <= \<const0>\;
m_axi_wlast(0) <= \<const0>\;
+ m_axi_wstrb(19 downto 16) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
+ m_axi_wuser(4) <= \<const0>\;
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
- m_axi_wvalid(3) <= \<const0>\;
- m_axi_wvalid(2 downto 0) <= \^m_axi_wvalid\(2 downto 0);
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
@@ -4646,23 +5485,23 @@ GND: unisim.vcomponents.GND
\gen_sasd.crossbar_sasd_0\: entity work.mb_design_1_xbar_0_axi_crossbar_v2_1_33_crossbar_sasd
port map (
Q(34 downto 32) => \^m_axi_arprot\(2 downto 0),
- Q(31 downto 12) => \^m_axi_awaddr\(127 downto 108),
- Q(11 downto 0) => \^m_axi_araddr\(11 downto 0),
+ Q(31 downto 7) => \^m_axi_awaddr\(159 downto 135),
+ Q(6 downto 0) => \^m_axi_araddr\(6 downto 0),
aclk => aclk,
aresetn => aresetn,
- m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
- m_axi_arvalid(2 downto 0) => \^m_axi_arvalid\(2 downto 0),
- m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
- m_axi_awvalid(2 downto 0) => \^m_axi_awvalid\(2 downto 0),
- m_axi_bready(2 downto 0) => \^m_axi_bready\(2 downto 0),
- m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
- m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
- m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
- m_axi_rready(2 downto 0) => \^m_axi_rready\(2 downto 0),
- m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
- m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
- m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
- m_axi_wvalid(2 downto 0) => \^m_axi_wvalid\(2 downto 0),
+ m_axi_arready(4 downto 0) => m_axi_arready(4 downto 0),
+ m_axi_arvalid(4 downto 0) => m_axi_arvalid(4 downto 0),
+ m_axi_awready(4 downto 0) => m_axi_awready(4 downto 0),
+ m_axi_awvalid(4 downto 0) => m_axi_awvalid(4 downto 0),
+ m_axi_bready(4 downto 0) => m_axi_bready(4 downto 0),
+ m_axi_bresp(9 downto 0) => m_axi_bresp(9 downto 0),
+ m_axi_bvalid(4 downto 0) => m_axi_bvalid(4 downto 0),
+ m_axi_rdata(159 downto 0) => m_axi_rdata(159 downto 0),
+ m_axi_rready(4 downto 0) => m_axi_rready(4 downto 0),
+ m_axi_rresp(9 downto 0) => m_axi_rresp(9 downto 0),
+ m_axi_rvalid(4 downto 0) => m_axi_rvalid(4 downto 0),
+ m_axi_wready(4 downto 0) => m_axi_wready(4 downto 0),
+ m_axi_wvalid(4 downto 0) => m_axi_wvalid(4 downto 0),
\m_payload_i_reg[34]\(33 downto 2) => s_axi_rdata(31 downto 0),
\m_payload_i_reg[34]\(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
@@ -4709,25 +5548,25 @@ entity mb_design_1_xbar_0 is
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mb_design_1_xbar_0 : entity is true;
@@ -4740,38 +5579,27 @@ entity mb_design_1_xbar_0 is
end mb_design_1_xbar_0;
architecture STRUCTURE of mb_design_1_xbar_0 is
- signal \<const0>\ : STD_LOGIC;
- signal \^m_axi_arvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_awvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_rready\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal \^m_axi_wvalid\ : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
- signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
- signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_inst_m_axi_rready_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
+ signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 39 downto 0 );
+ signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+ signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
+ signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 39 downto 0 );
+ signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
+ signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+ signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
+ signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
@@ -4804,23 +5632,23 @@ architecture STRUCTURE of mb_design_1_xbar_0 is
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_M_AXI_ADDR_WIDTH : string;
- attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100";
+ attribute C_M_AXI_ADDR_WIDTH of inst : label is "160'b0000000000000000000000000000011100000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100";
attribute C_M_AXI_BASE_ADDR : string;
- attribute C_M_AXI_BASE_ADDR of inst : label is "256'b1111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000";
+ attribute C_M_AXI_BASE_ADDR of inst : label is "320'b00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
- attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
- attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_READ_ISSUING of inst : label is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
- attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute C_M_AXI_SECURE of inst : label is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
- attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
- attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
+ attribute C_M_AXI_WRITE_ISSUING of inst : label is "160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
- attribute C_NUM_MASTER_SLOTS of inst : label is 4;
+ attribute C_NUM_MASTER_SLOTS of inst : label is 5;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
@@ -4857,11 +5685,11 @@ architecture STRUCTURE of mb_design_1_xbar_0 is
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
- attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute P_M_AXI_ERR_MODE of inst : label is "160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
- attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
+ attribute P_M_AXI_SUPPORTS_READ of inst : label is "5'b11111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
- attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
+ attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "5'b11111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
@@ -4880,26 +5708,26 @@ architecture STRUCTURE of mb_design_1_xbar_0 is
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
- attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]";
- attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]";
- attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]";
- attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]";
- attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]";
- attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]";
- attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]";
- attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
- attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]";
- attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]";
- attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]";
- attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]";
- attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]";
+ attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128]";
+ attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12]";
+ attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128]";
+ attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12]";
+ attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8]";
+ attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128]";
+ attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4]";
+ attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+ attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8]";
+ attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128]";
+ attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4]";
+ attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16]";
+ attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4]";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
@@ -4921,74 +5749,55 @@ architecture STRUCTURE of mb_design_1_xbar_0 is
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
begin
- m_axi_arvalid(3) <= \<const0>\;
- m_axi_arvalid(2 downto 0) <= \^m_axi_arvalid\(2 downto 0);
- m_axi_awvalid(3) <= \<const0>\;
- m_axi_awvalid(2 downto 0) <= \^m_axi_awvalid\(2 downto 0);
- m_axi_bready(3) <= \<const0>\;
- m_axi_bready(2 downto 0) <= \^m_axi_bready\(2 downto 0);
- m_axi_rready(3) <= \<const0>\;
- m_axi_rready(2 downto 0) <= \^m_axi_rready\(2 downto 0);
- m_axi_wvalid(3) <= \<const0>\;
- m_axi_wvalid(2 downto 0) <= \^m_axi_wvalid\(2 downto 0);
-GND: unisim.vcomponents.GND
- port map (
- G => \<const0>\
- );
inst: entity work.mb_design_1_xbar_0_axi_crossbar_v2_1_33_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
- m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
- m_axi_arburst(7 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(7 downto 0),
- m_axi_arcache(15 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(15 downto 0),
- m_axi_arid(3 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(3 downto 0),
- m_axi_arlen(31 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(31 downto 0),
- m_axi_arlock(3 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(3 downto 0),
- m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
- m_axi_arqos(15 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(15 downto 0),
- m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
- m_axi_arregion(15 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(15 downto 0),
- m_axi_arsize(11 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(11 downto 0),
- m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
- m_axi_arvalid(3) => NLW_inst_m_axi_arvalid_UNCONNECTED(3),
- m_axi_arvalid(2 downto 0) => \^m_axi_arvalid\(2 downto 0),
- m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
- m_axi_awburst(7 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(7 downto 0),
- m_axi_awcache(15 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(15 downto 0),
- m_axi_awid(3 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(3 downto 0),
- m_axi_awlen(31 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(31 downto 0),
- m_axi_awlock(3 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(3 downto 0),
- m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
- m_axi_awqos(15 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(15 downto 0),
- m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
- m_axi_awregion(15 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(15 downto 0),
- m_axi_awsize(11 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(11 downto 0),
- m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
- m_axi_awvalid(3) => NLW_inst_m_axi_awvalid_UNCONNECTED(3),
- m_axi_awvalid(2 downto 0) => \^m_axi_awvalid\(2 downto 0),
- m_axi_bid(3 downto 0) => B"0000",
- m_axi_bready(3) => NLW_inst_m_axi_bready_UNCONNECTED(3),
- m_axi_bready(2 downto 0) => \^m_axi_bready\(2 downto 0),
- m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
- m_axi_buser(3 downto 0) => B"0000",
- m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
- m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
- m_axi_rid(3 downto 0) => B"0000",
- m_axi_rlast(3 downto 0) => B"1111",
- m_axi_rready(3) => NLW_inst_m_axi_rready_UNCONNECTED(3),
- m_axi_rready(2 downto 0) => \^m_axi_rready\(2 downto 0),
- m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
- m_axi_ruser(3 downto 0) => B"0000",
- m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
- m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
- m_axi_wid(3 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(3 downto 0),
- m_axi_wlast(3 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(3 downto 0),
- m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
- m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
- m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
- m_axi_wvalid(3) => NLW_inst_m_axi_wvalid_UNCONNECTED(3),
- m_axi_wvalid(2 downto 0) => \^m_axi_wvalid\(2 downto 0),
+ m_axi_araddr(159 downto 0) => m_axi_araddr(159 downto 0),
+ m_axi_arburst(9 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(9 downto 0),
+ m_axi_arcache(19 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(19 downto 0),
+ m_axi_arid(4 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(4 downto 0),
+ m_axi_arlen(39 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(39 downto 0),
+ m_axi_arlock(4 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(4 downto 0),
+ m_axi_arprot(14 downto 0) => m_axi_arprot(14 downto 0),
+ m_axi_arqos(19 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(19 downto 0),
+ m_axi_arready(4 downto 0) => m_axi_arready(4 downto 0),
+ m_axi_arregion(19 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(19 downto 0),
+ m_axi_arsize(14 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(14 downto 0),
+ m_axi_aruser(4 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(4 downto 0),
+ m_axi_arvalid(4 downto 0) => m_axi_arvalid(4 downto 0),
+ m_axi_awaddr(159 downto 0) => m_axi_awaddr(159 downto 0),
+ m_axi_awburst(9 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(9 downto 0),
+ m_axi_awcache(19 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(19 downto 0),
+ m_axi_awid(4 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(4 downto 0),
+ m_axi_awlen(39 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(39 downto 0),
+ m_axi_awlock(4 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(4 downto 0),
+ m_axi_awprot(14 downto 0) => m_axi_awprot(14 downto 0),
+ m_axi_awqos(19 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(19 downto 0),
+ m_axi_awready(4 downto 0) => m_axi_awready(4 downto 0),
+ m_axi_awregion(19 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(19 downto 0),
+ m_axi_awsize(14 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(14 downto 0),
+ m_axi_awuser(4 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(4 downto 0),
+ m_axi_awvalid(4 downto 0) => m_axi_awvalid(4 downto 0),
+ m_axi_bid(4 downto 0) => B"00000",
+ m_axi_bready(4 downto 0) => m_axi_bready(4 downto 0),
+ m_axi_bresp(9 downto 0) => m_axi_bresp(9 downto 0),
+ m_axi_buser(4 downto 0) => B"00000",
+ m_axi_bvalid(4 downto 0) => m_axi_bvalid(4 downto 0),
+ m_axi_rdata(159 downto 0) => m_axi_rdata(159 downto 0),
+ m_axi_rid(4 downto 0) => B"00000",
+ m_axi_rlast(4 downto 0) => B"11111",
+ m_axi_rready(4 downto 0) => m_axi_rready(4 downto 0),
+ m_axi_rresp(9 downto 0) => m_axi_rresp(9 downto 0),
+ m_axi_ruser(4 downto 0) => B"00000",
+ m_axi_rvalid(4 downto 0) => m_axi_rvalid(4 downto 0),
+ m_axi_wdata(159 downto 0) => m_axi_wdata(159 downto 0),
+ m_axi_wid(4 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(4 downto 0),
+ m_axi_wlast(4 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(4 downto 0),
+ m_axi_wready(4 downto 0) => m_axi_wready(4 downto 0),
+ m_axi_wstrb(19 downto 0) => m_axi_wstrb(19 downto 0),
+ m_axi_wuser(4 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(4 downto 0),
+ m_axi_wvalid(4 downto 0) => m_axi_wvalid(4 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.v
index 50c7a62520809a4c0f014e9cb206d62eaaf249ef..83b96cfda7a2721ab5dbc3727dc8da0df9b00e4d 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.v
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.v
@@ -2,10 +2,10 @@
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-// Date : Tue Mar 4 22:38:42 2025
+// Date : Thu Mar 20 17:31:25 2025
// Host : hogtest running 64-bit unknown
-// Command : write_verilog -force -mode synth_stub
-// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.v
+// Command : write_verilog -force -mode synth_stub -rename_top mb_design_1_xbar_0 -prefix
+// mb_design_1_xbar_0_ mb_design_1_xbar_0_stub.v
// Design : mb_design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
@@ -22,7 +22,7 @@ module mb_design_1_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
-/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[127:0],m_axi_awprot[11:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_araddr[127:0],m_axi_arprot[11:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */
+/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[159:0],m_axi_awprot[14:0],m_axi_awvalid[4:0],m_axi_awready[4:0],m_axi_wdata[159:0],m_axi_wstrb[19:0],m_axi_wvalid[4:0],m_axi_wready[4:0],m_axi_bresp[9:0],m_axi_bvalid[4:0],m_axi_bready[4:0],m_axi_araddr[159:0],m_axi_arprot[14:0],m_axi_arvalid[4:0],m_axi_arready[4:0],m_axi_rdata[159:0],m_axi_rresp[9:0],m_axi_rvalid[4:0],m_axi_rready[4:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
@@ -45,23 +45,23 @@ module mb_design_1_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
- output [127:0]m_axi_awaddr;
- output [11:0]m_axi_awprot;
- output [3:0]m_axi_awvalid;
- input [3:0]m_axi_awready;
- output [127:0]m_axi_wdata;
- output [15:0]m_axi_wstrb;
- output [3:0]m_axi_wvalid;
- input [3:0]m_axi_wready;
- input [7:0]m_axi_bresp;
- input [3:0]m_axi_bvalid;
- output [3:0]m_axi_bready;
- output [127:0]m_axi_araddr;
- output [11:0]m_axi_arprot;
- output [3:0]m_axi_arvalid;
- input [3:0]m_axi_arready;
- input [127:0]m_axi_rdata;
- input [7:0]m_axi_rresp;
- input [3:0]m_axi_rvalid;
- output [3:0]m_axi_rready;
+ output [159:0]m_axi_awaddr;
+ output [14:0]m_axi_awprot;
+ output [4:0]m_axi_awvalid;
+ input [4:0]m_axi_awready;
+ output [159:0]m_axi_wdata;
+ output [19:0]m_axi_wstrb;
+ output [4:0]m_axi_wvalid;
+ input [4:0]m_axi_wready;
+ input [9:0]m_axi_bresp;
+ input [4:0]m_axi_bvalid;
+ output [4:0]m_axi_bready;
+ output [159:0]m_axi_araddr;
+ output [14:0]m_axi_arprot;
+ output [4:0]m_axi_arvalid;
+ input [4:0]m_axi_arready;
+ input [159:0]m_axi_rdata;
+ input [9:0]m_axi_rresp;
+ input [4:0]m_axi_rvalid;
+ output [4:0]m_axi_rready;
endmodule
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.vhdl b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.vhdl
index 568ff301ca868a1b758080bc174aec6176866ee9..40748a7732afaf4666c446bdb40e45f491a48c5f 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.vhdl
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.vhdl
@@ -2,10 +2,10 @@
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--- Date : Tue Mar 4 22:38:42 2025
+-- Date : Thu Mar 20 17:31:25 2025
-- Host : hogtest running 64-bit unknown
--- Command : write_vhdl -force -mode synth_stub
--- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0_stub.vhdl
+-- Command : write_vhdl -force -mode synth_stub -rename_top mb_design_1_xbar_0 -prefix
+-- mb_design_1_xbar_0_ mb_design_1_xbar_0_stub.vhdl
-- Design : mb_design_1_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
@@ -36,25 +36,25 @@ entity mb_design_1_xbar_0 is
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end mb_design_1_xbar_0;
@@ -63,7 +63,7 @@ architecture stub of mb_design_1_xbar_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[127:0],m_axi_awprot[11:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_araddr[127:0],m_axi_arprot[11:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rvalid[3:0],m_axi_rready[3:0]";
+attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[159:0],m_axi_awprot[14:0],m_axi_awvalid[4:0],m_axi_awready[4:0],m_axi_wdata[159:0],m_axi_wstrb[19:0],m_axi_wvalid[4:0],m_axi_wready[4:0],m_axi_bresp[9:0],m_axi_bvalid[4:0],m_axi_bready[4:0],m_axi_araddr[159:0],m_axi_arprot[14:0],m_axi_arvalid[4:0],m_axi_arready[4:0],m_axi_rdata[159:0],m_axi_rresp[9:0],m_axi_rvalid[4:0],m_axi_rready[4:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_33_axi_crossbar,Vivado 2024.1.2";
begin
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.cpp b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.cpp
index 423306fd922eb2db5e6cfc55f286800aae349bc7..f97e99085b5cf6ce92129db8ac3701343dd018ef 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.cpp
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.cpp
@@ -160,6 +160,26 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_rresp_converter_3 = NULL;
mp_m_axi_rvalid_converter_3 = NULL;
mp_m_axi_rready_converter_3 = NULL;
+ mp_M04_AXI_transactor = NULL;
+ mp_m_axi_awaddr_converter_4 = NULL;
+ mp_m_axi_awprot_converter_4 = NULL;
+ mp_m_axi_awvalid_converter_4 = NULL;
+ mp_m_axi_awready_converter_4 = NULL;
+ mp_m_axi_wdata_converter_4 = NULL;
+ mp_m_axi_wstrb_converter_4 = NULL;
+ mp_m_axi_wvalid_converter_4 = NULL;
+ mp_m_axi_wready_converter_4 = NULL;
+ mp_m_axi_bresp_converter_4 = NULL;
+ mp_m_axi_bvalid_converter_4 = NULL;
+ mp_m_axi_bready_converter_4 = NULL;
+ mp_m_axi_araddr_converter_4 = NULL;
+ mp_m_axi_arprot_converter_4 = NULL;
+ mp_m_axi_arvalid_converter_4 = NULL;
+ mp_m_axi_arready_converter_4 = NULL;
+ mp_m_axi_rdata_converter_4 = NULL;
+ mp_m_axi_rresp_converter_4 = NULL;
+ mp_m_axi_rvalid_converter_4 = NULL;
+ mp_m_axi_rready_converter_4 = NULL;
// initialize junctures
mp_m_axi_concat_araddr = NULL;
@@ -181,79 +201,79 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_split_rresp = NULL;
mp_m_axi_split_rvalid = NULL;
mp_m_axi_split_wready = NULL;
- mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_awaddr");
+ mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_awaddr");
mp_m_axi_concat_awaddr->in_port[0](m_axi_concat_awaddr_out_0);
mp_m_axi_concat_awaddr->out_port(m_axi_awaddr);
mp_m_axi_concat_awaddr->offset_port(0, 0);
- mp_m_axi_concat_awprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_awprot");
+ mp_m_axi_concat_awprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_awprot");
mp_m_axi_concat_awprot->in_port[0](m_axi_concat_awprot_out_0);
mp_m_axi_concat_awprot->out_port(m_axi_awprot);
mp_m_axi_concat_awprot->offset_port(0, 0);
- mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_awvalid");
+ mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_awvalid");
mp_m_axi_concat_awvalid->in_port[0](m_axi_concat_awvalid_out_0);
mp_m_axi_concat_awvalid->out_port(m_axi_awvalid);
mp_m_axi_concat_awvalid->offset_port(0, 0);
- mp_m_axi_split_awready = new xsc::xsc_split<4, 4>("m_axi_split_awready");
+ mp_m_axi_split_awready = new xsc::xsc_split<5, 5>("m_axi_split_awready");
mp_m_axi_split_awready->in_port(m_axi_awready);
mp_m_axi_split_awready->out_port[0](m_axi_split_awready_out_0);
mp_m_axi_split_awready->add_mask(0,1,0);
- mp_m_axi_concat_wdata = new xsc::xsc_concatenator<128, 4>("m_axi_concat_wdata");
+ mp_m_axi_concat_wdata = new xsc::xsc_concatenator<160, 5>("m_axi_concat_wdata");
mp_m_axi_concat_wdata->in_port[0](m_axi_concat_wdata_out_0);
mp_m_axi_concat_wdata->out_port(m_axi_wdata);
mp_m_axi_concat_wdata->offset_port(0, 0);
- mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<16, 4>("m_axi_concat_wstrb");
+ mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<20, 5>("m_axi_concat_wstrb");
mp_m_axi_concat_wstrb->in_port[0](m_axi_concat_wstrb_out_0);
mp_m_axi_concat_wstrb->out_port(m_axi_wstrb);
mp_m_axi_concat_wstrb->offset_port(0, 0);
- mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_wvalid");
+ mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_wvalid");
mp_m_axi_concat_wvalid->in_port[0](m_axi_concat_wvalid_out_0);
mp_m_axi_concat_wvalid->out_port(m_axi_wvalid);
mp_m_axi_concat_wvalid->offset_port(0, 0);
- mp_m_axi_split_wready = new xsc::xsc_split<4, 4>("m_axi_split_wready");
+ mp_m_axi_split_wready = new xsc::xsc_split<5, 5>("m_axi_split_wready");
mp_m_axi_split_wready->in_port(m_axi_wready);
mp_m_axi_split_wready->out_port[0](m_axi_split_wready_out_0);
mp_m_axi_split_wready->add_mask(0,1,0);
- mp_m_axi_split_bresp = new xsc::xsc_split<8, 4>("m_axi_split_bresp");
+ mp_m_axi_split_bresp = new xsc::xsc_split<10, 5>("m_axi_split_bresp");
mp_m_axi_split_bresp->in_port(m_axi_bresp);
mp_m_axi_split_bresp->out_port[0](m_axi_split_bresp_out_0);
mp_m_axi_split_bresp->add_mask(0,2,0);
- mp_m_axi_split_bvalid = new xsc::xsc_split<4, 4>("m_axi_split_bvalid");
+ mp_m_axi_split_bvalid = new xsc::xsc_split<5, 5>("m_axi_split_bvalid");
mp_m_axi_split_bvalid->in_port(m_axi_bvalid);
mp_m_axi_split_bvalid->out_port[0](m_axi_split_bvalid_out_0);
mp_m_axi_split_bvalid->add_mask(0,1,0);
- mp_m_axi_concat_bready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_bready");
+ mp_m_axi_concat_bready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_bready");
mp_m_axi_concat_bready->in_port[0](m_axi_concat_bready_out_0);
mp_m_axi_concat_bready->out_port(m_axi_bready);
mp_m_axi_concat_bready->offset_port(0, 0);
- mp_m_axi_concat_araddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_araddr");
+ mp_m_axi_concat_araddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_araddr");
mp_m_axi_concat_araddr->in_port[0](m_axi_concat_araddr_out_0);
mp_m_axi_concat_araddr->out_port(m_axi_araddr);
mp_m_axi_concat_araddr->offset_port(0, 0);
- mp_m_axi_concat_arprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_arprot");
+ mp_m_axi_concat_arprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_arprot");
mp_m_axi_concat_arprot->in_port[0](m_axi_concat_arprot_out_0);
mp_m_axi_concat_arprot->out_port(m_axi_arprot);
mp_m_axi_concat_arprot->offset_port(0, 0);
- mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_arvalid");
+ mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_arvalid");
mp_m_axi_concat_arvalid->in_port[0](m_axi_concat_arvalid_out_0);
mp_m_axi_concat_arvalid->out_port(m_axi_arvalid);
mp_m_axi_concat_arvalid->offset_port(0, 0);
- mp_m_axi_split_arready = new xsc::xsc_split<4, 4>("m_axi_split_arready");
+ mp_m_axi_split_arready = new xsc::xsc_split<5, 5>("m_axi_split_arready");
mp_m_axi_split_arready->in_port(m_axi_arready);
mp_m_axi_split_arready->out_port[0](m_axi_split_arready_out_0);
mp_m_axi_split_arready->add_mask(0,1,0);
- mp_m_axi_split_rdata = new xsc::xsc_split<128, 4>("m_axi_split_rdata");
+ mp_m_axi_split_rdata = new xsc::xsc_split<160, 5>("m_axi_split_rdata");
mp_m_axi_split_rdata->in_port(m_axi_rdata);
mp_m_axi_split_rdata->out_port[0](m_axi_split_rdata_out_0);
mp_m_axi_split_rdata->add_mask(0,32,0);
- mp_m_axi_split_rresp = new xsc::xsc_split<8, 4>("m_axi_split_rresp");
+ mp_m_axi_split_rresp = new xsc::xsc_split<10, 5>("m_axi_split_rresp");
mp_m_axi_split_rresp->in_port(m_axi_rresp);
mp_m_axi_split_rresp->out_port[0](m_axi_split_rresp_out_0);
mp_m_axi_split_rresp->add_mask(0,2,0);
- mp_m_axi_split_rvalid = new xsc::xsc_split<4, 4>("m_axi_split_rvalid");
+ mp_m_axi_split_rvalid = new xsc::xsc_split<5, 5>("m_axi_split_rvalid");
mp_m_axi_split_rvalid->in_port(m_axi_rvalid);
mp_m_axi_split_rvalid->out_port[0](m_axi_split_rvalid_out_0);
mp_m_axi_split_rvalid->add_mask(0,1,0);
- mp_m_axi_concat_rready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_rready");
+ mp_m_axi_concat_rready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_rready");
mp_m_axi_concat_rready->in_port[0](m_axi_concat_rready_out_0);
mp_m_axi_concat_rready->out_port(m_axi_rready);
mp_m_axi_concat_rready->offset_port(0, 0);
@@ -395,6 +415,52 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_split_rvalid->add_mask(3,4,3);
mp_m_axi_concat_rready->in_port[3](m_axi_concat_rready_out_3);
mp_m_axi_concat_rready->offset_port(3, 3);
+ mp_m_axi_concat_awaddr->in_port[4](m_axi_concat_awaddr_out_4);
+ mp_m_axi_concat_awaddr->offset_port(4, 128);
+ mp_m_axi_concat_awprot->in_port[4](m_axi_concat_awprot_out_4);
+ mp_m_axi_concat_awprot->offset_port(4, 12);
+ mp_m_axi_concat_awvalid->in_port[4](m_axi_concat_awvalid_out_4);
+ mp_m_axi_concat_awvalid->offset_port(4, 4);
+
+ mp_m_axi_split_awready->out_port[4](m_axi_split_awready_out_4);
+ mp_m_axi_split_awready->add_mask(4,5,4);
+ mp_m_axi_concat_wdata->in_port[4](m_axi_concat_wdata_out_4);
+ mp_m_axi_concat_wdata->offset_port(4, 128);
+ mp_m_axi_concat_wstrb->in_port[4](m_axi_concat_wstrb_out_4);
+ mp_m_axi_concat_wstrb->offset_port(4, 16);
+ mp_m_axi_concat_wvalid->in_port[4](m_axi_concat_wvalid_out_4);
+ mp_m_axi_concat_wvalid->offset_port(4, 4);
+
+ mp_m_axi_split_wready->out_port[4](m_axi_split_wready_out_4);
+ mp_m_axi_split_wready->add_mask(4,5,4);
+
+ mp_m_axi_split_bresp->out_port[4](m_axi_split_bresp_out_4);
+ mp_m_axi_split_bresp->add_mask(4,10,8);
+
+ mp_m_axi_split_bvalid->out_port[4](m_axi_split_bvalid_out_4);
+ mp_m_axi_split_bvalid->add_mask(4,5,4);
+ mp_m_axi_concat_bready->in_port[4](m_axi_concat_bready_out_4);
+ mp_m_axi_concat_bready->offset_port(4, 4);
+ mp_m_axi_concat_araddr->in_port[4](m_axi_concat_araddr_out_4);
+ mp_m_axi_concat_araddr->offset_port(4, 128);
+ mp_m_axi_concat_arprot->in_port[4](m_axi_concat_arprot_out_4);
+ mp_m_axi_concat_arprot->offset_port(4, 12);
+ mp_m_axi_concat_arvalid->in_port[4](m_axi_concat_arvalid_out_4);
+ mp_m_axi_concat_arvalid->offset_port(4, 4);
+
+ mp_m_axi_split_arready->out_port[4](m_axi_split_arready_out_4);
+ mp_m_axi_split_arready->add_mask(4,5,4);
+
+ mp_m_axi_split_rdata->out_port[4](m_axi_split_rdata_out_4);
+ mp_m_axi_split_rdata->add_mask(4,160,128);
+
+ mp_m_axi_split_rresp->out_port[4](m_axi_split_rresp_out_4);
+ mp_m_axi_split_rresp->add_mask(4,10,8);
+
+ mp_m_axi_split_rvalid->out_port[4](m_axi_split_rvalid_out_4);
+ mp_m_axi_split_rvalid->add_mask(4,5,4);
+ mp_m_axi_concat_rready->in_port[4](m_axi_concat_rready_out_4);
+ mp_m_axi_concat_rready->offset_port(4, 4);
// initialize socket stubs
@@ -553,79 +619,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M00_AXI' transactor ports
- mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_0");
+ mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_0");
mp_m_axi_awaddr_converter_0->vector_in(m_m_axi_awaddr_converter_0_signal);
mp_m_axi_awaddr_converter_0->vector_out(m_axi_concat_awaddr_out_0);
mp_M00_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_0_signal);
- mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_0");
+ mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_0");
mp_m_axi_awprot_converter_0->vector_in(m_m_axi_awprot_converter_0_signal);
mp_m_axi_awprot_converter_0->vector_out(m_axi_concat_awprot_out_0);
mp_M00_AXI_transactor->AWPROT(m_m_axi_awprot_converter_0_signal);
- mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_0");
+ mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_0");
mp_m_axi_awvalid_converter_0->scalar_in(m_m_axi_awvalid_converter_0_signal);
mp_m_axi_awvalid_converter_0->vector_out(m_axi_concat_awvalid_out_0);
mp_M00_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_0_signal);
- mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_0");
+ mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_0");
mp_m_axi_awready_converter_0->vector_in(m_axi_split_awready_out_0);
mp_m_axi_awready_converter_0->scalar_out(m_m_axi_awready_converter_0_signal);
mp_M00_AXI_transactor->AWREADY(m_m_axi_awready_converter_0_signal);
- mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_0");
+ mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_0");
mp_m_axi_wdata_converter_0->vector_in(m_m_axi_wdata_converter_0_signal);
mp_m_axi_wdata_converter_0->vector_out(m_axi_concat_wdata_out_0);
mp_M00_AXI_transactor->WDATA(m_m_axi_wdata_converter_0_signal);
- mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_0");
+ mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_0");
mp_m_axi_wstrb_converter_0->vector_in(m_m_axi_wstrb_converter_0_signal);
mp_m_axi_wstrb_converter_0->vector_out(m_axi_concat_wstrb_out_0);
mp_M00_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_0_signal);
- mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_0");
+ mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_0");
mp_m_axi_wvalid_converter_0->scalar_in(m_m_axi_wvalid_converter_0_signal);
mp_m_axi_wvalid_converter_0->vector_out(m_axi_concat_wvalid_out_0);
mp_M00_AXI_transactor->WVALID(m_m_axi_wvalid_converter_0_signal);
- mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_0");
+ mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_0");
mp_m_axi_wready_converter_0->vector_in(m_axi_split_wready_out_0);
mp_m_axi_wready_converter_0->scalar_out(m_m_axi_wready_converter_0_signal);
mp_M00_AXI_transactor->WREADY(m_m_axi_wready_converter_0_signal);
- mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_0");
+ mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_0");
mp_m_axi_bresp_converter_0->vector_in(m_axi_split_bresp_out_0);
mp_m_axi_bresp_converter_0->vector_out(m_m_axi_bresp_converter_0_signal);
mp_M00_AXI_transactor->BRESP(m_m_axi_bresp_converter_0_signal);
- mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_0");
+ mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_0");
mp_m_axi_bvalid_converter_0->vector_in(m_axi_split_bvalid_out_0);
mp_m_axi_bvalid_converter_0->scalar_out(m_m_axi_bvalid_converter_0_signal);
mp_M00_AXI_transactor->BVALID(m_m_axi_bvalid_converter_0_signal);
- mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_0");
+ mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_0");
mp_m_axi_bready_converter_0->scalar_in(m_m_axi_bready_converter_0_signal);
mp_m_axi_bready_converter_0->vector_out(m_axi_concat_bready_out_0);
mp_M00_AXI_transactor->BREADY(m_m_axi_bready_converter_0_signal);
- mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_0");
+ mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_0");
mp_m_axi_araddr_converter_0->vector_in(m_m_axi_araddr_converter_0_signal);
mp_m_axi_araddr_converter_0->vector_out(m_axi_concat_araddr_out_0);
mp_M00_AXI_transactor->ARADDR(m_m_axi_araddr_converter_0_signal);
- mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_0");
+ mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_0");
mp_m_axi_arprot_converter_0->vector_in(m_m_axi_arprot_converter_0_signal);
mp_m_axi_arprot_converter_0->vector_out(m_axi_concat_arprot_out_0);
mp_M00_AXI_transactor->ARPROT(m_m_axi_arprot_converter_0_signal);
- mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_0");
+ mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_0");
mp_m_axi_arvalid_converter_0->scalar_in(m_m_axi_arvalid_converter_0_signal);
mp_m_axi_arvalid_converter_0->vector_out(m_axi_concat_arvalid_out_0);
mp_M00_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_0_signal);
- mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_0");
+ mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_0");
mp_m_axi_arready_converter_0->vector_in(m_axi_split_arready_out_0);
mp_m_axi_arready_converter_0->scalar_out(m_m_axi_arready_converter_0_signal);
mp_M00_AXI_transactor->ARREADY(m_m_axi_arready_converter_0_signal);
- mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_0");
+ mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_0");
mp_m_axi_rdata_converter_0->vector_in(m_axi_split_rdata_out_0);
mp_m_axi_rdata_converter_0->vector_out(m_m_axi_rdata_converter_0_signal);
mp_M00_AXI_transactor->RDATA(m_m_axi_rdata_converter_0_signal);
- mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_0");
+ mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_0");
mp_m_axi_rresp_converter_0->vector_in(m_axi_split_rresp_out_0);
mp_m_axi_rresp_converter_0->vector_out(m_m_axi_rresp_converter_0_signal);
mp_M00_AXI_transactor->RRESP(m_m_axi_rresp_converter_0_signal);
- mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_0");
+ mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_0");
mp_m_axi_rvalid_converter_0->vector_in(m_axi_split_rvalid_out_0);
mp_m_axi_rvalid_converter_0->scalar_out(m_m_axi_rvalid_converter_0_signal);
mp_M00_AXI_transactor->RVALID(m_m_axi_rvalid_converter_0_signal);
- mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_0");
+ mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_0");
mp_m_axi_rready_converter_0->scalar_in(m_m_axi_rready_converter_0_signal);
mp_m_axi_rready_converter_0->vector_out(m_axi_concat_rready_out_0);
mp_M00_AXI_transactor->RREADY(m_m_axi_rready_converter_0_signal);
@@ -686,79 +752,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M01_AXI' transactor ports
- mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_1");
+ mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_1");
mp_m_axi_awaddr_converter_1->vector_in(m_m_axi_awaddr_converter_1_signal);
mp_m_axi_awaddr_converter_1->vector_out(m_axi_concat_awaddr_out_1);
mp_M01_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_1_signal);
- mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_1");
+ mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_1");
mp_m_axi_awprot_converter_1->vector_in(m_m_axi_awprot_converter_1_signal);
mp_m_axi_awprot_converter_1->vector_out(m_axi_concat_awprot_out_1);
mp_M01_AXI_transactor->AWPROT(m_m_axi_awprot_converter_1_signal);
- mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_1");
+ mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_1");
mp_m_axi_awvalid_converter_1->scalar_in(m_m_axi_awvalid_converter_1_signal);
mp_m_axi_awvalid_converter_1->vector_out(m_axi_concat_awvalid_out_1);
mp_M01_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_1_signal);
- mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_1");
+ mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_1");
mp_m_axi_awready_converter_1->vector_in(m_axi_split_awready_out_1);
mp_m_axi_awready_converter_1->scalar_out(m_m_axi_awready_converter_1_signal);
mp_M01_AXI_transactor->AWREADY(m_m_axi_awready_converter_1_signal);
- mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_1");
+ mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_1");
mp_m_axi_wdata_converter_1->vector_in(m_m_axi_wdata_converter_1_signal);
mp_m_axi_wdata_converter_1->vector_out(m_axi_concat_wdata_out_1);
mp_M01_AXI_transactor->WDATA(m_m_axi_wdata_converter_1_signal);
- mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_1");
+ mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_1");
mp_m_axi_wstrb_converter_1->vector_in(m_m_axi_wstrb_converter_1_signal);
mp_m_axi_wstrb_converter_1->vector_out(m_axi_concat_wstrb_out_1);
mp_M01_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_1_signal);
- mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_1");
+ mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_1");
mp_m_axi_wvalid_converter_1->scalar_in(m_m_axi_wvalid_converter_1_signal);
mp_m_axi_wvalid_converter_1->vector_out(m_axi_concat_wvalid_out_1);
mp_M01_AXI_transactor->WVALID(m_m_axi_wvalid_converter_1_signal);
- mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_1");
+ mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_1");
mp_m_axi_wready_converter_1->vector_in(m_axi_split_wready_out_1);
mp_m_axi_wready_converter_1->scalar_out(m_m_axi_wready_converter_1_signal);
mp_M01_AXI_transactor->WREADY(m_m_axi_wready_converter_1_signal);
- mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_1");
+ mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_1");
mp_m_axi_bresp_converter_1->vector_in(m_axi_split_bresp_out_1);
mp_m_axi_bresp_converter_1->vector_out(m_m_axi_bresp_converter_1_signal);
mp_M01_AXI_transactor->BRESP(m_m_axi_bresp_converter_1_signal);
- mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_1");
+ mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_1");
mp_m_axi_bvalid_converter_1->vector_in(m_axi_split_bvalid_out_1);
mp_m_axi_bvalid_converter_1->scalar_out(m_m_axi_bvalid_converter_1_signal);
mp_M01_AXI_transactor->BVALID(m_m_axi_bvalid_converter_1_signal);
- mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_1");
+ mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_1");
mp_m_axi_bready_converter_1->scalar_in(m_m_axi_bready_converter_1_signal);
mp_m_axi_bready_converter_1->vector_out(m_axi_concat_bready_out_1);
mp_M01_AXI_transactor->BREADY(m_m_axi_bready_converter_1_signal);
- mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_1");
+ mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_1");
mp_m_axi_araddr_converter_1->vector_in(m_m_axi_araddr_converter_1_signal);
mp_m_axi_araddr_converter_1->vector_out(m_axi_concat_araddr_out_1);
mp_M01_AXI_transactor->ARADDR(m_m_axi_araddr_converter_1_signal);
- mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_1");
+ mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_1");
mp_m_axi_arprot_converter_1->vector_in(m_m_axi_arprot_converter_1_signal);
mp_m_axi_arprot_converter_1->vector_out(m_axi_concat_arprot_out_1);
mp_M01_AXI_transactor->ARPROT(m_m_axi_arprot_converter_1_signal);
- mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_1");
+ mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_1");
mp_m_axi_arvalid_converter_1->scalar_in(m_m_axi_arvalid_converter_1_signal);
mp_m_axi_arvalid_converter_1->vector_out(m_axi_concat_arvalid_out_1);
mp_M01_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_1_signal);
- mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_1");
+ mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_1");
mp_m_axi_arready_converter_1->vector_in(m_axi_split_arready_out_1);
mp_m_axi_arready_converter_1->scalar_out(m_m_axi_arready_converter_1_signal);
mp_M01_AXI_transactor->ARREADY(m_m_axi_arready_converter_1_signal);
- mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_1");
+ mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_1");
mp_m_axi_rdata_converter_1->vector_in(m_axi_split_rdata_out_1);
mp_m_axi_rdata_converter_1->vector_out(m_m_axi_rdata_converter_1_signal);
mp_M01_AXI_transactor->RDATA(m_m_axi_rdata_converter_1_signal);
- mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_1");
+ mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_1");
mp_m_axi_rresp_converter_1->vector_in(m_axi_split_rresp_out_1);
mp_m_axi_rresp_converter_1->vector_out(m_m_axi_rresp_converter_1_signal);
mp_M01_AXI_transactor->RRESP(m_m_axi_rresp_converter_1_signal);
- mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_1");
+ mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_1");
mp_m_axi_rvalid_converter_1->vector_in(m_axi_split_rvalid_out_1);
mp_m_axi_rvalid_converter_1->scalar_out(m_m_axi_rvalid_converter_1_signal);
mp_M01_AXI_transactor->RVALID(m_m_axi_rvalid_converter_1_signal);
- mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_1");
+ mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_1");
mp_m_axi_rready_converter_1->scalar_in(m_m_axi_rready_converter_1_signal);
mp_m_axi_rready_converter_1->vector_out(m_axi_concat_rready_out_1);
mp_M01_AXI_transactor->RREADY(m_m_axi_rready_converter_1_signal);
@@ -819,79 +885,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M02_AXI' transactor ports
- mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_2");
+ mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_2");
mp_m_axi_awaddr_converter_2->vector_in(m_m_axi_awaddr_converter_2_signal);
mp_m_axi_awaddr_converter_2->vector_out(m_axi_concat_awaddr_out_2);
mp_M02_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_2_signal);
- mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_2");
+ mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_2");
mp_m_axi_awprot_converter_2->vector_in(m_m_axi_awprot_converter_2_signal);
mp_m_axi_awprot_converter_2->vector_out(m_axi_concat_awprot_out_2);
mp_M02_AXI_transactor->AWPROT(m_m_axi_awprot_converter_2_signal);
- mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_2");
+ mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_2");
mp_m_axi_awvalid_converter_2->scalar_in(m_m_axi_awvalid_converter_2_signal);
mp_m_axi_awvalid_converter_2->vector_out(m_axi_concat_awvalid_out_2);
mp_M02_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_2_signal);
- mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_2");
+ mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_2");
mp_m_axi_awready_converter_2->vector_in(m_axi_split_awready_out_2);
mp_m_axi_awready_converter_2->scalar_out(m_m_axi_awready_converter_2_signal);
mp_M02_AXI_transactor->AWREADY(m_m_axi_awready_converter_2_signal);
- mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_2");
+ mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_2");
mp_m_axi_wdata_converter_2->vector_in(m_m_axi_wdata_converter_2_signal);
mp_m_axi_wdata_converter_2->vector_out(m_axi_concat_wdata_out_2);
mp_M02_AXI_transactor->WDATA(m_m_axi_wdata_converter_2_signal);
- mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_2");
+ mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_2");
mp_m_axi_wstrb_converter_2->vector_in(m_m_axi_wstrb_converter_2_signal);
mp_m_axi_wstrb_converter_2->vector_out(m_axi_concat_wstrb_out_2);
mp_M02_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_2_signal);
- mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_2");
+ mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_2");
mp_m_axi_wvalid_converter_2->scalar_in(m_m_axi_wvalid_converter_2_signal);
mp_m_axi_wvalid_converter_2->vector_out(m_axi_concat_wvalid_out_2);
mp_M02_AXI_transactor->WVALID(m_m_axi_wvalid_converter_2_signal);
- mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_2");
+ mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_2");
mp_m_axi_wready_converter_2->vector_in(m_axi_split_wready_out_2);
mp_m_axi_wready_converter_2->scalar_out(m_m_axi_wready_converter_2_signal);
mp_M02_AXI_transactor->WREADY(m_m_axi_wready_converter_2_signal);
- mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_2");
+ mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_2");
mp_m_axi_bresp_converter_2->vector_in(m_axi_split_bresp_out_2);
mp_m_axi_bresp_converter_2->vector_out(m_m_axi_bresp_converter_2_signal);
mp_M02_AXI_transactor->BRESP(m_m_axi_bresp_converter_2_signal);
- mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_2");
+ mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_2");
mp_m_axi_bvalid_converter_2->vector_in(m_axi_split_bvalid_out_2);
mp_m_axi_bvalid_converter_2->scalar_out(m_m_axi_bvalid_converter_2_signal);
mp_M02_AXI_transactor->BVALID(m_m_axi_bvalid_converter_2_signal);
- mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_2");
+ mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_2");
mp_m_axi_bready_converter_2->scalar_in(m_m_axi_bready_converter_2_signal);
mp_m_axi_bready_converter_2->vector_out(m_axi_concat_bready_out_2);
mp_M02_AXI_transactor->BREADY(m_m_axi_bready_converter_2_signal);
- mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_2");
+ mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_2");
mp_m_axi_araddr_converter_2->vector_in(m_m_axi_araddr_converter_2_signal);
mp_m_axi_araddr_converter_2->vector_out(m_axi_concat_araddr_out_2);
mp_M02_AXI_transactor->ARADDR(m_m_axi_araddr_converter_2_signal);
- mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_2");
+ mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_2");
mp_m_axi_arprot_converter_2->vector_in(m_m_axi_arprot_converter_2_signal);
mp_m_axi_arprot_converter_2->vector_out(m_axi_concat_arprot_out_2);
mp_M02_AXI_transactor->ARPROT(m_m_axi_arprot_converter_2_signal);
- mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_2");
+ mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_2");
mp_m_axi_arvalid_converter_2->scalar_in(m_m_axi_arvalid_converter_2_signal);
mp_m_axi_arvalid_converter_2->vector_out(m_axi_concat_arvalid_out_2);
mp_M02_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_2_signal);
- mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_2");
+ mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_2");
mp_m_axi_arready_converter_2->vector_in(m_axi_split_arready_out_2);
mp_m_axi_arready_converter_2->scalar_out(m_m_axi_arready_converter_2_signal);
mp_M02_AXI_transactor->ARREADY(m_m_axi_arready_converter_2_signal);
- mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_2");
+ mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_2");
mp_m_axi_rdata_converter_2->vector_in(m_axi_split_rdata_out_2);
mp_m_axi_rdata_converter_2->vector_out(m_m_axi_rdata_converter_2_signal);
mp_M02_AXI_transactor->RDATA(m_m_axi_rdata_converter_2_signal);
- mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_2");
+ mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_2");
mp_m_axi_rresp_converter_2->vector_in(m_axi_split_rresp_out_2);
mp_m_axi_rresp_converter_2->vector_out(m_m_axi_rresp_converter_2_signal);
mp_M02_AXI_transactor->RRESP(m_m_axi_rresp_converter_2_signal);
- mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_2");
+ mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_2");
mp_m_axi_rvalid_converter_2->vector_in(m_axi_split_rvalid_out_2);
mp_m_axi_rvalid_converter_2->scalar_out(m_m_axi_rvalid_converter_2_signal);
mp_M02_AXI_transactor->RVALID(m_m_axi_rvalid_converter_2_signal);
- mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_2");
+ mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_2");
mp_m_axi_rready_converter_2->scalar_in(m_m_axi_rready_converter_2_signal);
mp_m_axi_rready_converter_2->vector_out(m_axi_concat_rready_out_2);
mp_M02_AXI_transactor->RREADY(m_m_axi_rready_converter_2_signal);
@@ -934,8 +1000,8 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
M03_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
M03_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
M03_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
- M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
- M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+ M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
M03_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
M03_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
M03_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
@@ -952,79 +1018,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M03_AXI' transactor ports
- mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_3");
+ mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_3");
mp_m_axi_awaddr_converter_3->vector_in(m_m_axi_awaddr_converter_3_signal);
mp_m_axi_awaddr_converter_3->vector_out(m_axi_concat_awaddr_out_3);
mp_M03_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_3_signal);
- mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_3");
+ mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_3");
mp_m_axi_awprot_converter_3->vector_in(m_m_axi_awprot_converter_3_signal);
mp_m_axi_awprot_converter_3->vector_out(m_axi_concat_awprot_out_3);
mp_M03_AXI_transactor->AWPROT(m_m_axi_awprot_converter_3_signal);
- mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_3");
+ mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_3");
mp_m_axi_awvalid_converter_3->scalar_in(m_m_axi_awvalid_converter_3_signal);
mp_m_axi_awvalid_converter_3->vector_out(m_axi_concat_awvalid_out_3);
mp_M03_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_3_signal);
- mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_3");
+ mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_3");
mp_m_axi_awready_converter_3->vector_in(m_axi_split_awready_out_3);
mp_m_axi_awready_converter_3->scalar_out(m_m_axi_awready_converter_3_signal);
mp_M03_AXI_transactor->AWREADY(m_m_axi_awready_converter_3_signal);
- mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_3");
+ mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_3");
mp_m_axi_wdata_converter_3->vector_in(m_m_axi_wdata_converter_3_signal);
mp_m_axi_wdata_converter_3->vector_out(m_axi_concat_wdata_out_3);
mp_M03_AXI_transactor->WDATA(m_m_axi_wdata_converter_3_signal);
- mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_3");
+ mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_3");
mp_m_axi_wstrb_converter_3->vector_in(m_m_axi_wstrb_converter_3_signal);
mp_m_axi_wstrb_converter_3->vector_out(m_axi_concat_wstrb_out_3);
mp_M03_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_3_signal);
- mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_3");
+ mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_3");
mp_m_axi_wvalid_converter_3->scalar_in(m_m_axi_wvalid_converter_3_signal);
mp_m_axi_wvalid_converter_3->vector_out(m_axi_concat_wvalid_out_3);
mp_M03_AXI_transactor->WVALID(m_m_axi_wvalid_converter_3_signal);
- mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_3");
+ mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_3");
mp_m_axi_wready_converter_3->vector_in(m_axi_split_wready_out_3);
mp_m_axi_wready_converter_3->scalar_out(m_m_axi_wready_converter_3_signal);
mp_M03_AXI_transactor->WREADY(m_m_axi_wready_converter_3_signal);
- mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_3");
+ mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_3");
mp_m_axi_bresp_converter_3->vector_in(m_axi_split_bresp_out_3);
mp_m_axi_bresp_converter_3->vector_out(m_m_axi_bresp_converter_3_signal);
mp_M03_AXI_transactor->BRESP(m_m_axi_bresp_converter_3_signal);
- mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_3");
+ mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_3");
mp_m_axi_bvalid_converter_3->vector_in(m_axi_split_bvalid_out_3);
mp_m_axi_bvalid_converter_3->scalar_out(m_m_axi_bvalid_converter_3_signal);
mp_M03_AXI_transactor->BVALID(m_m_axi_bvalid_converter_3_signal);
- mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_3");
+ mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_3");
mp_m_axi_bready_converter_3->scalar_in(m_m_axi_bready_converter_3_signal);
mp_m_axi_bready_converter_3->vector_out(m_axi_concat_bready_out_3);
mp_M03_AXI_transactor->BREADY(m_m_axi_bready_converter_3_signal);
- mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_3");
+ mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_3");
mp_m_axi_araddr_converter_3->vector_in(m_m_axi_araddr_converter_3_signal);
mp_m_axi_araddr_converter_3->vector_out(m_axi_concat_araddr_out_3);
mp_M03_AXI_transactor->ARADDR(m_m_axi_araddr_converter_3_signal);
- mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_3");
+ mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_3");
mp_m_axi_arprot_converter_3->vector_in(m_m_axi_arprot_converter_3_signal);
mp_m_axi_arprot_converter_3->vector_out(m_axi_concat_arprot_out_3);
mp_M03_AXI_transactor->ARPROT(m_m_axi_arprot_converter_3_signal);
- mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_3");
+ mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_3");
mp_m_axi_arvalid_converter_3->scalar_in(m_m_axi_arvalid_converter_3_signal);
mp_m_axi_arvalid_converter_3->vector_out(m_axi_concat_arvalid_out_3);
mp_M03_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_3_signal);
- mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_3");
+ mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_3");
mp_m_axi_arready_converter_3->vector_in(m_axi_split_arready_out_3);
mp_m_axi_arready_converter_3->scalar_out(m_m_axi_arready_converter_3_signal);
mp_M03_AXI_transactor->ARREADY(m_m_axi_arready_converter_3_signal);
- mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_3");
+ mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_3");
mp_m_axi_rdata_converter_3->vector_in(m_axi_split_rdata_out_3);
mp_m_axi_rdata_converter_3->vector_out(m_m_axi_rdata_converter_3_signal);
mp_M03_AXI_transactor->RDATA(m_m_axi_rdata_converter_3_signal);
- mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_3");
+ mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_3");
mp_m_axi_rresp_converter_3->vector_in(m_axi_split_rresp_out_3);
mp_m_axi_rresp_converter_3->vector_out(m_m_axi_rresp_converter_3_signal);
mp_M03_AXI_transactor->RRESP(m_m_axi_rresp_converter_3_signal);
- mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_3");
+ mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_3");
mp_m_axi_rvalid_converter_3->vector_in(m_axi_split_rvalid_out_3);
mp_m_axi_rvalid_converter_3->scalar_out(m_m_axi_rvalid_converter_3_signal);
mp_M03_AXI_transactor->RVALID(m_m_axi_rvalid_converter_3_signal);
- mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_3");
+ mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_3");
mp_m_axi_rready_converter_3->scalar_in(m_m_axi_rready_converter_3_signal);
mp_m_axi_rready_converter_3->vector_out(m_axi_concat_rready_out_3);
mp_M03_AXI_transactor->RREADY(m_m_axi_rready_converter_3_signal);
@@ -1040,6 +1106,139 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
{
}
+ // configure 'M04_AXI' transactor
+
+ if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("mb_design_1_xbar_0", "M04_AXI_TLM_MODE") != 1)
+ {
+ // Instantiate Socket Stubs
+
+ // 'M04_AXI' transactor parameters
+ xsc::common_cpp::properties M04_AXI_transactor_param_props;
+ M04_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000");
+ M04_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+ M04_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+ M04_AXI_transactor_param_props.addFloat("PHASE", "0.0");
+ M04_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+ M04_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+ M04_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
+
+ mp_M04_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M04_AXI_transactor", M04_AXI_transactor_param_props);
+
+ // M04_AXI' transactor ports
+
+ mp_m_axi_awaddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_4");
+ mp_m_axi_awaddr_converter_4->vector_in(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awaddr_converter_4->vector_out(m_axi_concat_awaddr_out_4);
+ mp_M04_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_4");
+ mp_m_axi_awprot_converter_4->vector_in(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awprot_converter_4->vector_out(m_axi_concat_awprot_out_4);
+ mp_M04_AXI_transactor->AWPROT(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_4");
+ mp_m_axi_awvalid_converter_4->scalar_in(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awvalid_converter_4->vector_out(m_axi_concat_awvalid_out_4);
+ mp_M04_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_4");
+ mp_m_axi_awready_converter_4->vector_in(m_axi_split_awready_out_4);
+ mp_m_axi_awready_converter_4->scalar_out(m_m_axi_awready_converter_4_signal);
+ mp_M04_AXI_transactor->AWREADY(m_m_axi_awready_converter_4_signal);
+ mp_m_axi_wdata_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_4");
+ mp_m_axi_wdata_converter_4->vector_in(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wdata_converter_4->vector_out(m_axi_concat_wdata_out_4);
+ mp_M04_AXI_transactor->WDATA(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wstrb_converter_4 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_4");
+ mp_m_axi_wstrb_converter_4->vector_in(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wstrb_converter_4->vector_out(m_axi_concat_wstrb_out_4);
+ mp_M04_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_4");
+ mp_m_axi_wvalid_converter_4->scalar_in(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wvalid_converter_4->vector_out(m_axi_concat_wvalid_out_4);
+ mp_M04_AXI_transactor->WVALID(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_4");
+ mp_m_axi_wready_converter_4->vector_in(m_axi_split_wready_out_4);
+ mp_m_axi_wready_converter_4->scalar_out(m_m_axi_wready_converter_4_signal);
+ mp_M04_AXI_transactor->WREADY(m_m_axi_wready_converter_4_signal);
+ mp_m_axi_bresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_4");
+ mp_m_axi_bresp_converter_4->vector_in(m_axi_split_bresp_out_4);
+ mp_m_axi_bresp_converter_4->vector_out(m_m_axi_bresp_converter_4_signal);
+ mp_M04_AXI_transactor->BRESP(m_m_axi_bresp_converter_4_signal);
+ mp_m_axi_bvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_4");
+ mp_m_axi_bvalid_converter_4->vector_in(m_axi_split_bvalid_out_4);
+ mp_m_axi_bvalid_converter_4->scalar_out(m_m_axi_bvalid_converter_4_signal);
+ mp_M04_AXI_transactor->BVALID(m_m_axi_bvalid_converter_4_signal);
+ mp_m_axi_bready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_4");
+ mp_m_axi_bready_converter_4->scalar_in(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_bready_converter_4->vector_out(m_axi_concat_bready_out_4);
+ mp_M04_AXI_transactor->BREADY(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_araddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_4");
+ mp_m_axi_araddr_converter_4->vector_in(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_araddr_converter_4->vector_out(m_axi_concat_araddr_out_4);
+ mp_M04_AXI_transactor->ARADDR(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_arprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_4");
+ mp_m_axi_arprot_converter_4->vector_in(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arprot_converter_4->vector_out(m_axi_concat_arprot_out_4);
+ mp_M04_AXI_transactor->ARPROT(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_4");
+ mp_m_axi_arvalid_converter_4->scalar_in(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arvalid_converter_4->vector_out(m_axi_concat_arvalid_out_4);
+ mp_M04_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_4");
+ mp_m_axi_arready_converter_4->vector_in(m_axi_split_arready_out_4);
+ mp_m_axi_arready_converter_4->scalar_out(m_m_axi_arready_converter_4_signal);
+ mp_M04_AXI_transactor->ARREADY(m_m_axi_arready_converter_4_signal);
+ mp_m_axi_rdata_converter_4 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_4");
+ mp_m_axi_rdata_converter_4->vector_in(m_axi_split_rdata_out_4);
+ mp_m_axi_rdata_converter_4->vector_out(m_m_axi_rdata_converter_4_signal);
+ mp_M04_AXI_transactor->RDATA(m_m_axi_rdata_converter_4_signal);
+ mp_m_axi_rresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_4");
+ mp_m_axi_rresp_converter_4->vector_in(m_axi_split_rresp_out_4);
+ mp_m_axi_rresp_converter_4->vector_out(m_m_axi_rresp_converter_4_signal);
+ mp_M04_AXI_transactor->RRESP(m_m_axi_rresp_converter_4_signal);
+ mp_m_axi_rvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_4");
+ mp_m_axi_rvalid_converter_4->vector_in(m_axi_split_rvalid_out_4);
+ mp_m_axi_rvalid_converter_4->scalar_out(m_m_axi_rvalid_converter_4_signal);
+ mp_M04_AXI_transactor->RVALID(m_m_axi_rvalid_converter_4_signal);
+ mp_m_axi_rready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_4");
+ mp_m_axi_rready_converter_4->scalar_in(m_m_axi_rready_converter_4_signal);
+ mp_m_axi_rready_converter_4->vector_out(m_axi_concat_rready_out_4);
+ mp_M04_AXI_transactor->RREADY(m_m_axi_rready_converter_4_signal);
+ mp_M04_AXI_transactor->CLK(aclk);
+ mp_M04_AXI_transactor->RST(aresetn);
+
+ // M04_AXI' transactor sockets
+
+ mp_impl->initiator_4_rd_socket->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_impl->initiator_4_wr_socket->bind(*(mp_M04_AXI_transactor->wr_socket));
+ }
+ else
+ {
+ }
+
}
#endif // XILINX_SIMULATOR
@@ -1147,6 +1346,26 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_rresp_converter_3 = NULL;
mp_m_axi_rvalid_converter_3 = NULL;
mp_m_axi_rready_converter_3 = NULL;
+ mp_M04_AXI_transactor = NULL;
+ mp_m_axi_awaddr_converter_4 = NULL;
+ mp_m_axi_awprot_converter_4 = NULL;
+ mp_m_axi_awvalid_converter_4 = NULL;
+ mp_m_axi_awready_converter_4 = NULL;
+ mp_m_axi_wdata_converter_4 = NULL;
+ mp_m_axi_wstrb_converter_4 = NULL;
+ mp_m_axi_wvalid_converter_4 = NULL;
+ mp_m_axi_wready_converter_4 = NULL;
+ mp_m_axi_bresp_converter_4 = NULL;
+ mp_m_axi_bvalid_converter_4 = NULL;
+ mp_m_axi_bready_converter_4 = NULL;
+ mp_m_axi_araddr_converter_4 = NULL;
+ mp_m_axi_arprot_converter_4 = NULL;
+ mp_m_axi_arvalid_converter_4 = NULL;
+ mp_m_axi_arready_converter_4 = NULL;
+ mp_m_axi_rdata_converter_4 = NULL;
+ mp_m_axi_rresp_converter_4 = NULL;
+ mp_m_axi_rvalid_converter_4 = NULL;
+ mp_m_axi_rready_converter_4 = NULL;
// initialize junctures
mp_m_axi_concat_araddr = NULL;
@@ -1168,79 +1387,79 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_split_rresp = NULL;
mp_m_axi_split_rvalid = NULL;
mp_m_axi_split_wready = NULL;
- mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_awaddr");
+ mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_awaddr");
mp_m_axi_concat_awaddr->in_port[0](m_axi_concat_awaddr_out_0);
mp_m_axi_concat_awaddr->out_port(m_axi_awaddr);
mp_m_axi_concat_awaddr->offset_port(0, 0);
- mp_m_axi_concat_awprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_awprot");
+ mp_m_axi_concat_awprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_awprot");
mp_m_axi_concat_awprot->in_port[0](m_axi_concat_awprot_out_0);
mp_m_axi_concat_awprot->out_port(m_axi_awprot);
mp_m_axi_concat_awprot->offset_port(0, 0);
- mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_awvalid");
+ mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_awvalid");
mp_m_axi_concat_awvalid->in_port[0](m_axi_concat_awvalid_out_0);
mp_m_axi_concat_awvalid->out_port(m_axi_awvalid);
mp_m_axi_concat_awvalid->offset_port(0, 0);
- mp_m_axi_split_awready = new xsc::xsc_split<4, 4>("m_axi_split_awready");
+ mp_m_axi_split_awready = new xsc::xsc_split<5, 5>("m_axi_split_awready");
mp_m_axi_split_awready->in_port(m_axi_awready);
mp_m_axi_split_awready->out_port[0](m_axi_split_awready_out_0);
mp_m_axi_split_awready->add_mask(0,1,0);
- mp_m_axi_concat_wdata = new xsc::xsc_concatenator<128, 4>("m_axi_concat_wdata");
+ mp_m_axi_concat_wdata = new xsc::xsc_concatenator<160, 5>("m_axi_concat_wdata");
mp_m_axi_concat_wdata->in_port[0](m_axi_concat_wdata_out_0);
mp_m_axi_concat_wdata->out_port(m_axi_wdata);
mp_m_axi_concat_wdata->offset_port(0, 0);
- mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<16, 4>("m_axi_concat_wstrb");
+ mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<20, 5>("m_axi_concat_wstrb");
mp_m_axi_concat_wstrb->in_port[0](m_axi_concat_wstrb_out_0);
mp_m_axi_concat_wstrb->out_port(m_axi_wstrb);
mp_m_axi_concat_wstrb->offset_port(0, 0);
- mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_wvalid");
+ mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_wvalid");
mp_m_axi_concat_wvalid->in_port[0](m_axi_concat_wvalid_out_0);
mp_m_axi_concat_wvalid->out_port(m_axi_wvalid);
mp_m_axi_concat_wvalid->offset_port(0, 0);
- mp_m_axi_split_wready = new xsc::xsc_split<4, 4>("m_axi_split_wready");
+ mp_m_axi_split_wready = new xsc::xsc_split<5, 5>("m_axi_split_wready");
mp_m_axi_split_wready->in_port(m_axi_wready);
mp_m_axi_split_wready->out_port[0](m_axi_split_wready_out_0);
mp_m_axi_split_wready->add_mask(0,1,0);
- mp_m_axi_split_bresp = new xsc::xsc_split<8, 4>("m_axi_split_bresp");
+ mp_m_axi_split_bresp = new xsc::xsc_split<10, 5>("m_axi_split_bresp");
mp_m_axi_split_bresp->in_port(m_axi_bresp);
mp_m_axi_split_bresp->out_port[0](m_axi_split_bresp_out_0);
mp_m_axi_split_bresp->add_mask(0,2,0);
- mp_m_axi_split_bvalid = new xsc::xsc_split<4, 4>("m_axi_split_bvalid");
+ mp_m_axi_split_bvalid = new xsc::xsc_split<5, 5>("m_axi_split_bvalid");
mp_m_axi_split_bvalid->in_port(m_axi_bvalid);
mp_m_axi_split_bvalid->out_port[0](m_axi_split_bvalid_out_0);
mp_m_axi_split_bvalid->add_mask(0,1,0);
- mp_m_axi_concat_bready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_bready");
+ mp_m_axi_concat_bready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_bready");
mp_m_axi_concat_bready->in_port[0](m_axi_concat_bready_out_0);
mp_m_axi_concat_bready->out_port(m_axi_bready);
mp_m_axi_concat_bready->offset_port(0, 0);
- mp_m_axi_concat_araddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_araddr");
+ mp_m_axi_concat_araddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_araddr");
mp_m_axi_concat_araddr->in_port[0](m_axi_concat_araddr_out_0);
mp_m_axi_concat_araddr->out_port(m_axi_araddr);
mp_m_axi_concat_araddr->offset_port(0, 0);
- mp_m_axi_concat_arprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_arprot");
+ mp_m_axi_concat_arprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_arprot");
mp_m_axi_concat_arprot->in_port[0](m_axi_concat_arprot_out_0);
mp_m_axi_concat_arprot->out_port(m_axi_arprot);
mp_m_axi_concat_arprot->offset_port(0, 0);
- mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_arvalid");
+ mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_arvalid");
mp_m_axi_concat_arvalid->in_port[0](m_axi_concat_arvalid_out_0);
mp_m_axi_concat_arvalid->out_port(m_axi_arvalid);
mp_m_axi_concat_arvalid->offset_port(0, 0);
- mp_m_axi_split_arready = new xsc::xsc_split<4, 4>("m_axi_split_arready");
+ mp_m_axi_split_arready = new xsc::xsc_split<5, 5>("m_axi_split_arready");
mp_m_axi_split_arready->in_port(m_axi_arready);
mp_m_axi_split_arready->out_port[0](m_axi_split_arready_out_0);
mp_m_axi_split_arready->add_mask(0,1,0);
- mp_m_axi_split_rdata = new xsc::xsc_split<128, 4>("m_axi_split_rdata");
+ mp_m_axi_split_rdata = new xsc::xsc_split<160, 5>("m_axi_split_rdata");
mp_m_axi_split_rdata->in_port(m_axi_rdata);
mp_m_axi_split_rdata->out_port[0](m_axi_split_rdata_out_0);
mp_m_axi_split_rdata->add_mask(0,32,0);
- mp_m_axi_split_rresp = new xsc::xsc_split<8, 4>("m_axi_split_rresp");
+ mp_m_axi_split_rresp = new xsc::xsc_split<10, 5>("m_axi_split_rresp");
mp_m_axi_split_rresp->in_port(m_axi_rresp);
mp_m_axi_split_rresp->out_port[0](m_axi_split_rresp_out_0);
mp_m_axi_split_rresp->add_mask(0,2,0);
- mp_m_axi_split_rvalid = new xsc::xsc_split<4, 4>("m_axi_split_rvalid");
+ mp_m_axi_split_rvalid = new xsc::xsc_split<5, 5>("m_axi_split_rvalid");
mp_m_axi_split_rvalid->in_port(m_axi_rvalid);
mp_m_axi_split_rvalid->out_port[0](m_axi_split_rvalid_out_0);
mp_m_axi_split_rvalid->add_mask(0,1,0);
- mp_m_axi_concat_rready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_rready");
+ mp_m_axi_concat_rready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_rready");
mp_m_axi_concat_rready->in_port[0](m_axi_concat_rready_out_0);
mp_m_axi_concat_rready->out_port(m_axi_rready);
mp_m_axi_concat_rready->offset_port(0, 0);
@@ -1382,6 +1601,52 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_split_rvalid->add_mask(3,4,3);
mp_m_axi_concat_rready->in_port[3](m_axi_concat_rready_out_3);
mp_m_axi_concat_rready->offset_port(3, 3);
+ mp_m_axi_concat_awaddr->in_port[4](m_axi_concat_awaddr_out_4);
+ mp_m_axi_concat_awaddr->offset_port(4, 128);
+ mp_m_axi_concat_awprot->in_port[4](m_axi_concat_awprot_out_4);
+ mp_m_axi_concat_awprot->offset_port(4, 12);
+ mp_m_axi_concat_awvalid->in_port[4](m_axi_concat_awvalid_out_4);
+ mp_m_axi_concat_awvalid->offset_port(4, 4);
+
+ mp_m_axi_split_awready->out_port[4](m_axi_split_awready_out_4);
+ mp_m_axi_split_awready->add_mask(4,5,4);
+ mp_m_axi_concat_wdata->in_port[4](m_axi_concat_wdata_out_4);
+ mp_m_axi_concat_wdata->offset_port(4, 128);
+ mp_m_axi_concat_wstrb->in_port[4](m_axi_concat_wstrb_out_4);
+ mp_m_axi_concat_wstrb->offset_port(4, 16);
+ mp_m_axi_concat_wvalid->in_port[4](m_axi_concat_wvalid_out_4);
+ mp_m_axi_concat_wvalid->offset_port(4, 4);
+
+ mp_m_axi_split_wready->out_port[4](m_axi_split_wready_out_4);
+ mp_m_axi_split_wready->add_mask(4,5,4);
+
+ mp_m_axi_split_bresp->out_port[4](m_axi_split_bresp_out_4);
+ mp_m_axi_split_bresp->add_mask(4,10,8);
+
+ mp_m_axi_split_bvalid->out_port[4](m_axi_split_bvalid_out_4);
+ mp_m_axi_split_bvalid->add_mask(4,5,4);
+ mp_m_axi_concat_bready->in_port[4](m_axi_concat_bready_out_4);
+ mp_m_axi_concat_bready->offset_port(4, 4);
+ mp_m_axi_concat_araddr->in_port[4](m_axi_concat_araddr_out_4);
+ mp_m_axi_concat_araddr->offset_port(4, 128);
+ mp_m_axi_concat_arprot->in_port[4](m_axi_concat_arprot_out_4);
+ mp_m_axi_concat_arprot->offset_port(4, 12);
+ mp_m_axi_concat_arvalid->in_port[4](m_axi_concat_arvalid_out_4);
+ mp_m_axi_concat_arvalid->offset_port(4, 4);
+
+ mp_m_axi_split_arready->out_port[4](m_axi_split_arready_out_4);
+ mp_m_axi_split_arready->add_mask(4,5,4);
+
+ mp_m_axi_split_rdata->out_port[4](m_axi_split_rdata_out_4);
+ mp_m_axi_split_rdata->add_mask(4,160,128);
+
+ mp_m_axi_split_rresp->out_port[4](m_axi_split_rresp_out_4);
+ mp_m_axi_split_rresp->add_mask(4,10,8);
+
+ mp_m_axi_split_rvalid->out_port[4](m_axi_split_rvalid_out_4);
+ mp_m_axi_split_rvalid->add_mask(4,5,4);
+ mp_m_axi_concat_rready->in_port[4](m_axi_concat_rready_out_4);
+ mp_m_axi_concat_rready->offset_port(4, 4);
// initialize socket stubs
@@ -1540,79 +1805,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M00_AXI' transactor ports
- mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_0");
+ mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_0");
mp_m_axi_awaddr_converter_0->vector_in(m_m_axi_awaddr_converter_0_signal);
mp_m_axi_awaddr_converter_0->vector_out(m_axi_concat_awaddr_out_0);
mp_M00_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_0_signal);
- mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_0");
+ mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_0");
mp_m_axi_awprot_converter_0->vector_in(m_m_axi_awprot_converter_0_signal);
mp_m_axi_awprot_converter_0->vector_out(m_axi_concat_awprot_out_0);
mp_M00_AXI_transactor->AWPROT(m_m_axi_awprot_converter_0_signal);
- mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_0");
+ mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_0");
mp_m_axi_awvalid_converter_0->scalar_in(m_m_axi_awvalid_converter_0_signal);
mp_m_axi_awvalid_converter_0->vector_out(m_axi_concat_awvalid_out_0);
mp_M00_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_0_signal);
- mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_0");
+ mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_0");
mp_m_axi_awready_converter_0->vector_in(m_axi_split_awready_out_0);
mp_m_axi_awready_converter_0->scalar_out(m_m_axi_awready_converter_0_signal);
mp_M00_AXI_transactor->AWREADY(m_m_axi_awready_converter_0_signal);
- mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_0");
+ mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_0");
mp_m_axi_wdata_converter_0->vector_in(m_m_axi_wdata_converter_0_signal);
mp_m_axi_wdata_converter_0->vector_out(m_axi_concat_wdata_out_0);
mp_M00_AXI_transactor->WDATA(m_m_axi_wdata_converter_0_signal);
- mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_0");
+ mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_0");
mp_m_axi_wstrb_converter_0->vector_in(m_m_axi_wstrb_converter_0_signal);
mp_m_axi_wstrb_converter_0->vector_out(m_axi_concat_wstrb_out_0);
mp_M00_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_0_signal);
- mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_0");
+ mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_0");
mp_m_axi_wvalid_converter_0->scalar_in(m_m_axi_wvalid_converter_0_signal);
mp_m_axi_wvalid_converter_0->vector_out(m_axi_concat_wvalid_out_0);
mp_M00_AXI_transactor->WVALID(m_m_axi_wvalid_converter_0_signal);
- mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_0");
+ mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_0");
mp_m_axi_wready_converter_0->vector_in(m_axi_split_wready_out_0);
mp_m_axi_wready_converter_0->scalar_out(m_m_axi_wready_converter_0_signal);
mp_M00_AXI_transactor->WREADY(m_m_axi_wready_converter_0_signal);
- mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_0");
+ mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_0");
mp_m_axi_bresp_converter_0->vector_in(m_axi_split_bresp_out_0);
mp_m_axi_bresp_converter_0->vector_out(m_m_axi_bresp_converter_0_signal);
mp_M00_AXI_transactor->BRESP(m_m_axi_bresp_converter_0_signal);
- mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_0");
+ mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_0");
mp_m_axi_bvalid_converter_0->vector_in(m_axi_split_bvalid_out_0);
mp_m_axi_bvalid_converter_0->scalar_out(m_m_axi_bvalid_converter_0_signal);
mp_M00_AXI_transactor->BVALID(m_m_axi_bvalid_converter_0_signal);
- mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_0");
+ mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_0");
mp_m_axi_bready_converter_0->scalar_in(m_m_axi_bready_converter_0_signal);
mp_m_axi_bready_converter_0->vector_out(m_axi_concat_bready_out_0);
mp_M00_AXI_transactor->BREADY(m_m_axi_bready_converter_0_signal);
- mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_0");
+ mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_0");
mp_m_axi_araddr_converter_0->vector_in(m_m_axi_araddr_converter_0_signal);
mp_m_axi_araddr_converter_0->vector_out(m_axi_concat_araddr_out_0);
mp_M00_AXI_transactor->ARADDR(m_m_axi_araddr_converter_0_signal);
- mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_0");
+ mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_0");
mp_m_axi_arprot_converter_0->vector_in(m_m_axi_arprot_converter_0_signal);
mp_m_axi_arprot_converter_0->vector_out(m_axi_concat_arprot_out_0);
mp_M00_AXI_transactor->ARPROT(m_m_axi_arprot_converter_0_signal);
- mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_0");
+ mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_0");
mp_m_axi_arvalid_converter_0->scalar_in(m_m_axi_arvalid_converter_0_signal);
mp_m_axi_arvalid_converter_0->vector_out(m_axi_concat_arvalid_out_0);
mp_M00_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_0_signal);
- mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_0");
+ mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_0");
mp_m_axi_arready_converter_0->vector_in(m_axi_split_arready_out_0);
mp_m_axi_arready_converter_0->scalar_out(m_m_axi_arready_converter_0_signal);
mp_M00_AXI_transactor->ARREADY(m_m_axi_arready_converter_0_signal);
- mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_0");
+ mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_0");
mp_m_axi_rdata_converter_0->vector_in(m_axi_split_rdata_out_0);
mp_m_axi_rdata_converter_0->vector_out(m_m_axi_rdata_converter_0_signal);
mp_M00_AXI_transactor->RDATA(m_m_axi_rdata_converter_0_signal);
- mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_0");
+ mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_0");
mp_m_axi_rresp_converter_0->vector_in(m_axi_split_rresp_out_0);
mp_m_axi_rresp_converter_0->vector_out(m_m_axi_rresp_converter_0_signal);
mp_M00_AXI_transactor->RRESP(m_m_axi_rresp_converter_0_signal);
- mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_0");
+ mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_0");
mp_m_axi_rvalid_converter_0->vector_in(m_axi_split_rvalid_out_0);
mp_m_axi_rvalid_converter_0->scalar_out(m_m_axi_rvalid_converter_0_signal);
mp_M00_AXI_transactor->RVALID(m_m_axi_rvalid_converter_0_signal);
- mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_0");
+ mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_0");
mp_m_axi_rready_converter_0->scalar_in(m_m_axi_rready_converter_0_signal);
mp_m_axi_rready_converter_0->vector_out(m_axi_concat_rready_out_0);
mp_M00_AXI_transactor->RREADY(m_m_axi_rready_converter_0_signal);
@@ -1673,79 +1938,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M01_AXI' transactor ports
- mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_1");
+ mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_1");
mp_m_axi_awaddr_converter_1->vector_in(m_m_axi_awaddr_converter_1_signal);
mp_m_axi_awaddr_converter_1->vector_out(m_axi_concat_awaddr_out_1);
mp_M01_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_1_signal);
- mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_1");
+ mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_1");
mp_m_axi_awprot_converter_1->vector_in(m_m_axi_awprot_converter_1_signal);
mp_m_axi_awprot_converter_1->vector_out(m_axi_concat_awprot_out_1);
mp_M01_AXI_transactor->AWPROT(m_m_axi_awprot_converter_1_signal);
- mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_1");
+ mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_1");
mp_m_axi_awvalid_converter_1->scalar_in(m_m_axi_awvalid_converter_1_signal);
mp_m_axi_awvalid_converter_1->vector_out(m_axi_concat_awvalid_out_1);
mp_M01_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_1_signal);
- mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_1");
+ mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_1");
mp_m_axi_awready_converter_1->vector_in(m_axi_split_awready_out_1);
mp_m_axi_awready_converter_1->scalar_out(m_m_axi_awready_converter_1_signal);
mp_M01_AXI_transactor->AWREADY(m_m_axi_awready_converter_1_signal);
- mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_1");
+ mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_1");
mp_m_axi_wdata_converter_1->vector_in(m_m_axi_wdata_converter_1_signal);
mp_m_axi_wdata_converter_1->vector_out(m_axi_concat_wdata_out_1);
mp_M01_AXI_transactor->WDATA(m_m_axi_wdata_converter_1_signal);
- mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_1");
+ mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_1");
mp_m_axi_wstrb_converter_1->vector_in(m_m_axi_wstrb_converter_1_signal);
mp_m_axi_wstrb_converter_1->vector_out(m_axi_concat_wstrb_out_1);
mp_M01_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_1_signal);
- mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_1");
+ mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_1");
mp_m_axi_wvalid_converter_1->scalar_in(m_m_axi_wvalid_converter_1_signal);
mp_m_axi_wvalid_converter_1->vector_out(m_axi_concat_wvalid_out_1);
mp_M01_AXI_transactor->WVALID(m_m_axi_wvalid_converter_1_signal);
- mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_1");
+ mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_1");
mp_m_axi_wready_converter_1->vector_in(m_axi_split_wready_out_1);
mp_m_axi_wready_converter_1->scalar_out(m_m_axi_wready_converter_1_signal);
mp_M01_AXI_transactor->WREADY(m_m_axi_wready_converter_1_signal);
- mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_1");
+ mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_1");
mp_m_axi_bresp_converter_1->vector_in(m_axi_split_bresp_out_1);
mp_m_axi_bresp_converter_1->vector_out(m_m_axi_bresp_converter_1_signal);
mp_M01_AXI_transactor->BRESP(m_m_axi_bresp_converter_1_signal);
- mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_1");
+ mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_1");
mp_m_axi_bvalid_converter_1->vector_in(m_axi_split_bvalid_out_1);
mp_m_axi_bvalid_converter_1->scalar_out(m_m_axi_bvalid_converter_1_signal);
mp_M01_AXI_transactor->BVALID(m_m_axi_bvalid_converter_1_signal);
- mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_1");
+ mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_1");
mp_m_axi_bready_converter_1->scalar_in(m_m_axi_bready_converter_1_signal);
mp_m_axi_bready_converter_1->vector_out(m_axi_concat_bready_out_1);
mp_M01_AXI_transactor->BREADY(m_m_axi_bready_converter_1_signal);
- mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_1");
+ mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_1");
mp_m_axi_araddr_converter_1->vector_in(m_m_axi_araddr_converter_1_signal);
mp_m_axi_araddr_converter_1->vector_out(m_axi_concat_araddr_out_1);
mp_M01_AXI_transactor->ARADDR(m_m_axi_araddr_converter_1_signal);
- mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_1");
+ mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_1");
mp_m_axi_arprot_converter_1->vector_in(m_m_axi_arprot_converter_1_signal);
mp_m_axi_arprot_converter_1->vector_out(m_axi_concat_arprot_out_1);
mp_M01_AXI_transactor->ARPROT(m_m_axi_arprot_converter_1_signal);
- mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_1");
+ mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_1");
mp_m_axi_arvalid_converter_1->scalar_in(m_m_axi_arvalid_converter_1_signal);
mp_m_axi_arvalid_converter_1->vector_out(m_axi_concat_arvalid_out_1);
mp_M01_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_1_signal);
- mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_1");
+ mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_1");
mp_m_axi_arready_converter_1->vector_in(m_axi_split_arready_out_1);
mp_m_axi_arready_converter_1->scalar_out(m_m_axi_arready_converter_1_signal);
mp_M01_AXI_transactor->ARREADY(m_m_axi_arready_converter_1_signal);
- mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_1");
+ mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_1");
mp_m_axi_rdata_converter_1->vector_in(m_axi_split_rdata_out_1);
mp_m_axi_rdata_converter_1->vector_out(m_m_axi_rdata_converter_1_signal);
mp_M01_AXI_transactor->RDATA(m_m_axi_rdata_converter_1_signal);
- mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_1");
+ mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_1");
mp_m_axi_rresp_converter_1->vector_in(m_axi_split_rresp_out_1);
mp_m_axi_rresp_converter_1->vector_out(m_m_axi_rresp_converter_1_signal);
mp_M01_AXI_transactor->RRESP(m_m_axi_rresp_converter_1_signal);
- mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_1");
+ mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_1");
mp_m_axi_rvalid_converter_1->vector_in(m_axi_split_rvalid_out_1);
mp_m_axi_rvalid_converter_1->scalar_out(m_m_axi_rvalid_converter_1_signal);
mp_M01_AXI_transactor->RVALID(m_m_axi_rvalid_converter_1_signal);
- mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_1");
+ mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_1");
mp_m_axi_rready_converter_1->scalar_in(m_m_axi_rready_converter_1_signal);
mp_m_axi_rready_converter_1->vector_out(m_axi_concat_rready_out_1);
mp_M01_AXI_transactor->RREADY(m_m_axi_rready_converter_1_signal);
@@ -1806,79 +2071,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M02_AXI' transactor ports
- mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_2");
+ mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_2");
mp_m_axi_awaddr_converter_2->vector_in(m_m_axi_awaddr_converter_2_signal);
mp_m_axi_awaddr_converter_2->vector_out(m_axi_concat_awaddr_out_2);
mp_M02_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_2_signal);
- mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_2");
+ mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_2");
mp_m_axi_awprot_converter_2->vector_in(m_m_axi_awprot_converter_2_signal);
mp_m_axi_awprot_converter_2->vector_out(m_axi_concat_awprot_out_2);
mp_M02_AXI_transactor->AWPROT(m_m_axi_awprot_converter_2_signal);
- mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_2");
+ mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_2");
mp_m_axi_awvalid_converter_2->scalar_in(m_m_axi_awvalid_converter_2_signal);
mp_m_axi_awvalid_converter_2->vector_out(m_axi_concat_awvalid_out_2);
mp_M02_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_2_signal);
- mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_2");
+ mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_2");
mp_m_axi_awready_converter_2->vector_in(m_axi_split_awready_out_2);
mp_m_axi_awready_converter_2->scalar_out(m_m_axi_awready_converter_2_signal);
mp_M02_AXI_transactor->AWREADY(m_m_axi_awready_converter_2_signal);
- mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_2");
+ mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_2");
mp_m_axi_wdata_converter_2->vector_in(m_m_axi_wdata_converter_2_signal);
mp_m_axi_wdata_converter_2->vector_out(m_axi_concat_wdata_out_2);
mp_M02_AXI_transactor->WDATA(m_m_axi_wdata_converter_2_signal);
- mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_2");
+ mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_2");
mp_m_axi_wstrb_converter_2->vector_in(m_m_axi_wstrb_converter_2_signal);
mp_m_axi_wstrb_converter_2->vector_out(m_axi_concat_wstrb_out_2);
mp_M02_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_2_signal);
- mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_2");
+ mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_2");
mp_m_axi_wvalid_converter_2->scalar_in(m_m_axi_wvalid_converter_2_signal);
mp_m_axi_wvalid_converter_2->vector_out(m_axi_concat_wvalid_out_2);
mp_M02_AXI_transactor->WVALID(m_m_axi_wvalid_converter_2_signal);
- mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_2");
+ mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_2");
mp_m_axi_wready_converter_2->vector_in(m_axi_split_wready_out_2);
mp_m_axi_wready_converter_2->scalar_out(m_m_axi_wready_converter_2_signal);
mp_M02_AXI_transactor->WREADY(m_m_axi_wready_converter_2_signal);
- mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_2");
+ mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_2");
mp_m_axi_bresp_converter_2->vector_in(m_axi_split_bresp_out_2);
mp_m_axi_bresp_converter_2->vector_out(m_m_axi_bresp_converter_2_signal);
mp_M02_AXI_transactor->BRESP(m_m_axi_bresp_converter_2_signal);
- mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_2");
+ mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_2");
mp_m_axi_bvalid_converter_2->vector_in(m_axi_split_bvalid_out_2);
mp_m_axi_bvalid_converter_2->scalar_out(m_m_axi_bvalid_converter_2_signal);
mp_M02_AXI_transactor->BVALID(m_m_axi_bvalid_converter_2_signal);
- mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_2");
+ mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_2");
mp_m_axi_bready_converter_2->scalar_in(m_m_axi_bready_converter_2_signal);
mp_m_axi_bready_converter_2->vector_out(m_axi_concat_bready_out_2);
mp_M02_AXI_transactor->BREADY(m_m_axi_bready_converter_2_signal);
- mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_2");
+ mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_2");
mp_m_axi_araddr_converter_2->vector_in(m_m_axi_araddr_converter_2_signal);
mp_m_axi_araddr_converter_2->vector_out(m_axi_concat_araddr_out_2);
mp_M02_AXI_transactor->ARADDR(m_m_axi_araddr_converter_2_signal);
- mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_2");
+ mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_2");
mp_m_axi_arprot_converter_2->vector_in(m_m_axi_arprot_converter_2_signal);
mp_m_axi_arprot_converter_2->vector_out(m_axi_concat_arprot_out_2);
mp_M02_AXI_transactor->ARPROT(m_m_axi_arprot_converter_2_signal);
- mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_2");
+ mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_2");
mp_m_axi_arvalid_converter_2->scalar_in(m_m_axi_arvalid_converter_2_signal);
mp_m_axi_arvalid_converter_2->vector_out(m_axi_concat_arvalid_out_2);
mp_M02_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_2_signal);
- mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_2");
+ mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_2");
mp_m_axi_arready_converter_2->vector_in(m_axi_split_arready_out_2);
mp_m_axi_arready_converter_2->scalar_out(m_m_axi_arready_converter_2_signal);
mp_M02_AXI_transactor->ARREADY(m_m_axi_arready_converter_2_signal);
- mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_2");
+ mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_2");
mp_m_axi_rdata_converter_2->vector_in(m_axi_split_rdata_out_2);
mp_m_axi_rdata_converter_2->vector_out(m_m_axi_rdata_converter_2_signal);
mp_M02_AXI_transactor->RDATA(m_m_axi_rdata_converter_2_signal);
- mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_2");
+ mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_2");
mp_m_axi_rresp_converter_2->vector_in(m_axi_split_rresp_out_2);
mp_m_axi_rresp_converter_2->vector_out(m_m_axi_rresp_converter_2_signal);
mp_M02_AXI_transactor->RRESP(m_m_axi_rresp_converter_2_signal);
- mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_2");
+ mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_2");
mp_m_axi_rvalid_converter_2->vector_in(m_axi_split_rvalid_out_2);
mp_m_axi_rvalid_converter_2->scalar_out(m_m_axi_rvalid_converter_2_signal);
mp_M02_AXI_transactor->RVALID(m_m_axi_rvalid_converter_2_signal);
- mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_2");
+ mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_2");
mp_m_axi_rready_converter_2->scalar_in(m_m_axi_rready_converter_2_signal);
mp_m_axi_rready_converter_2->vector_out(m_axi_concat_rready_out_2);
mp_M02_AXI_transactor->RREADY(m_m_axi_rready_converter_2_signal);
@@ -1921,8 +2186,8 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
M03_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
M03_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
M03_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
- M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
- M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+ M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
M03_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
M03_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
M03_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
@@ -1939,79 +2204,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M03_AXI' transactor ports
- mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_3");
+ mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_3");
mp_m_axi_awaddr_converter_3->vector_in(m_m_axi_awaddr_converter_3_signal);
mp_m_axi_awaddr_converter_3->vector_out(m_axi_concat_awaddr_out_3);
mp_M03_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_3_signal);
- mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_3");
+ mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_3");
mp_m_axi_awprot_converter_3->vector_in(m_m_axi_awprot_converter_3_signal);
mp_m_axi_awprot_converter_3->vector_out(m_axi_concat_awprot_out_3);
mp_M03_AXI_transactor->AWPROT(m_m_axi_awprot_converter_3_signal);
- mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_3");
+ mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_3");
mp_m_axi_awvalid_converter_3->scalar_in(m_m_axi_awvalid_converter_3_signal);
mp_m_axi_awvalid_converter_3->vector_out(m_axi_concat_awvalid_out_3);
mp_M03_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_3_signal);
- mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_3");
+ mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_3");
mp_m_axi_awready_converter_3->vector_in(m_axi_split_awready_out_3);
mp_m_axi_awready_converter_3->scalar_out(m_m_axi_awready_converter_3_signal);
mp_M03_AXI_transactor->AWREADY(m_m_axi_awready_converter_3_signal);
- mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_3");
+ mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_3");
mp_m_axi_wdata_converter_3->vector_in(m_m_axi_wdata_converter_3_signal);
mp_m_axi_wdata_converter_3->vector_out(m_axi_concat_wdata_out_3);
mp_M03_AXI_transactor->WDATA(m_m_axi_wdata_converter_3_signal);
- mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_3");
+ mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_3");
mp_m_axi_wstrb_converter_3->vector_in(m_m_axi_wstrb_converter_3_signal);
mp_m_axi_wstrb_converter_3->vector_out(m_axi_concat_wstrb_out_3);
mp_M03_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_3_signal);
- mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_3");
+ mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_3");
mp_m_axi_wvalid_converter_3->scalar_in(m_m_axi_wvalid_converter_3_signal);
mp_m_axi_wvalid_converter_3->vector_out(m_axi_concat_wvalid_out_3);
mp_M03_AXI_transactor->WVALID(m_m_axi_wvalid_converter_3_signal);
- mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_3");
+ mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_3");
mp_m_axi_wready_converter_3->vector_in(m_axi_split_wready_out_3);
mp_m_axi_wready_converter_3->scalar_out(m_m_axi_wready_converter_3_signal);
mp_M03_AXI_transactor->WREADY(m_m_axi_wready_converter_3_signal);
- mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_3");
+ mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_3");
mp_m_axi_bresp_converter_3->vector_in(m_axi_split_bresp_out_3);
mp_m_axi_bresp_converter_3->vector_out(m_m_axi_bresp_converter_3_signal);
mp_M03_AXI_transactor->BRESP(m_m_axi_bresp_converter_3_signal);
- mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_3");
+ mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_3");
mp_m_axi_bvalid_converter_3->vector_in(m_axi_split_bvalid_out_3);
mp_m_axi_bvalid_converter_3->scalar_out(m_m_axi_bvalid_converter_3_signal);
mp_M03_AXI_transactor->BVALID(m_m_axi_bvalid_converter_3_signal);
- mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_3");
+ mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_3");
mp_m_axi_bready_converter_3->scalar_in(m_m_axi_bready_converter_3_signal);
mp_m_axi_bready_converter_3->vector_out(m_axi_concat_bready_out_3);
mp_M03_AXI_transactor->BREADY(m_m_axi_bready_converter_3_signal);
- mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_3");
+ mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_3");
mp_m_axi_araddr_converter_3->vector_in(m_m_axi_araddr_converter_3_signal);
mp_m_axi_araddr_converter_3->vector_out(m_axi_concat_araddr_out_3);
mp_M03_AXI_transactor->ARADDR(m_m_axi_araddr_converter_3_signal);
- mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_3");
+ mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_3");
mp_m_axi_arprot_converter_3->vector_in(m_m_axi_arprot_converter_3_signal);
mp_m_axi_arprot_converter_3->vector_out(m_axi_concat_arprot_out_3);
mp_M03_AXI_transactor->ARPROT(m_m_axi_arprot_converter_3_signal);
- mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_3");
+ mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_3");
mp_m_axi_arvalid_converter_3->scalar_in(m_m_axi_arvalid_converter_3_signal);
mp_m_axi_arvalid_converter_3->vector_out(m_axi_concat_arvalid_out_3);
mp_M03_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_3_signal);
- mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_3");
+ mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_3");
mp_m_axi_arready_converter_3->vector_in(m_axi_split_arready_out_3);
mp_m_axi_arready_converter_3->scalar_out(m_m_axi_arready_converter_3_signal);
mp_M03_AXI_transactor->ARREADY(m_m_axi_arready_converter_3_signal);
- mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_3");
+ mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_3");
mp_m_axi_rdata_converter_3->vector_in(m_axi_split_rdata_out_3);
mp_m_axi_rdata_converter_3->vector_out(m_m_axi_rdata_converter_3_signal);
mp_M03_AXI_transactor->RDATA(m_m_axi_rdata_converter_3_signal);
- mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_3");
+ mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_3");
mp_m_axi_rresp_converter_3->vector_in(m_axi_split_rresp_out_3);
mp_m_axi_rresp_converter_3->vector_out(m_m_axi_rresp_converter_3_signal);
mp_M03_AXI_transactor->RRESP(m_m_axi_rresp_converter_3_signal);
- mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_3");
+ mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_3");
mp_m_axi_rvalid_converter_3->vector_in(m_axi_split_rvalid_out_3);
mp_m_axi_rvalid_converter_3->scalar_out(m_m_axi_rvalid_converter_3_signal);
mp_M03_AXI_transactor->RVALID(m_m_axi_rvalid_converter_3_signal);
- mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_3");
+ mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_3");
mp_m_axi_rready_converter_3->scalar_in(m_m_axi_rready_converter_3_signal);
mp_m_axi_rready_converter_3->vector_out(m_axi_concat_rready_out_3);
mp_M03_AXI_transactor->RREADY(m_m_axi_rready_converter_3_signal);
@@ -2027,6 +2292,139 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
{
}
+ // configure 'M04_AXI' transactor
+
+ if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("mb_design_1_xbar_0", "M04_AXI_TLM_MODE") != 1)
+ {
+ // Instantiate Socket Stubs
+
+ // 'M04_AXI' transactor parameters
+ xsc::common_cpp::properties M04_AXI_transactor_param_props;
+ M04_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000");
+ M04_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+ M04_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+ M04_AXI_transactor_param_props.addFloat("PHASE", "0.0");
+ M04_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+ M04_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+ M04_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
+
+ mp_M04_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M04_AXI_transactor", M04_AXI_transactor_param_props);
+
+ // M04_AXI' transactor ports
+
+ mp_m_axi_awaddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_4");
+ mp_m_axi_awaddr_converter_4->vector_in(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awaddr_converter_4->vector_out(m_axi_concat_awaddr_out_4);
+ mp_M04_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_4");
+ mp_m_axi_awprot_converter_4->vector_in(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awprot_converter_4->vector_out(m_axi_concat_awprot_out_4);
+ mp_M04_AXI_transactor->AWPROT(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_4");
+ mp_m_axi_awvalid_converter_4->scalar_in(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awvalid_converter_4->vector_out(m_axi_concat_awvalid_out_4);
+ mp_M04_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_4");
+ mp_m_axi_awready_converter_4->vector_in(m_axi_split_awready_out_4);
+ mp_m_axi_awready_converter_4->scalar_out(m_m_axi_awready_converter_4_signal);
+ mp_M04_AXI_transactor->AWREADY(m_m_axi_awready_converter_4_signal);
+ mp_m_axi_wdata_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_4");
+ mp_m_axi_wdata_converter_4->vector_in(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wdata_converter_4->vector_out(m_axi_concat_wdata_out_4);
+ mp_M04_AXI_transactor->WDATA(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wstrb_converter_4 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_4");
+ mp_m_axi_wstrb_converter_4->vector_in(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wstrb_converter_4->vector_out(m_axi_concat_wstrb_out_4);
+ mp_M04_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_4");
+ mp_m_axi_wvalid_converter_4->scalar_in(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wvalid_converter_4->vector_out(m_axi_concat_wvalid_out_4);
+ mp_M04_AXI_transactor->WVALID(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_4");
+ mp_m_axi_wready_converter_4->vector_in(m_axi_split_wready_out_4);
+ mp_m_axi_wready_converter_4->scalar_out(m_m_axi_wready_converter_4_signal);
+ mp_M04_AXI_transactor->WREADY(m_m_axi_wready_converter_4_signal);
+ mp_m_axi_bresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_4");
+ mp_m_axi_bresp_converter_4->vector_in(m_axi_split_bresp_out_4);
+ mp_m_axi_bresp_converter_4->vector_out(m_m_axi_bresp_converter_4_signal);
+ mp_M04_AXI_transactor->BRESP(m_m_axi_bresp_converter_4_signal);
+ mp_m_axi_bvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_4");
+ mp_m_axi_bvalid_converter_4->vector_in(m_axi_split_bvalid_out_4);
+ mp_m_axi_bvalid_converter_4->scalar_out(m_m_axi_bvalid_converter_4_signal);
+ mp_M04_AXI_transactor->BVALID(m_m_axi_bvalid_converter_4_signal);
+ mp_m_axi_bready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_4");
+ mp_m_axi_bready_converter_4->scalar_in(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_bready_converter_4->vector_out(m_axi_concat_bready_out_4);
+ mp_M04_AXI_transactor->BREADY(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_araddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_4");
+ mp_m_axi_araddr_converter_4->vector_in(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_araddr_converter_4->vector_out(m_axi_concat_araddr_out_4);
+ mp_M04_AXI_transactor->ARADDR(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_arprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_4");
+ mp_m_axi_arprot_converter_4->vector_in(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arprot_converter_4->vector_out(m_axi_concat_arprot_out_4);
+ mp_M04_AXI_transactor->ARPROT(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_4");
+ mp_m_axi_arvalid_converter_4->scalar_in(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arvalid_converter_4->vector_out(m_axi_concat_arvalid_out_4);
+ mp_M04_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_4");
+ mp_m_axi_arready_converter_4->vector_in(m_axi_split_arready_out_4);
+ mp_m_axi_arready_converter_4->scalar_out(m_m_axi_arready_converter_4_signal);
+ mp_M04_AXI_transactor->ARREADY(m_m_axi_arready_converter_4_signal);
+ mp_m_axi_rdata_converter_4 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_4");
+ mp_m_axi_rdata_converter_4->vector_in(m_axi_split_rdata_out_4);
+ mp_m_axi_rdata_converter_4->vector_out(m_m_axi_rdata_converter_4_signal);
+ mp_M04_AXI_transactor->RDATA(m_m_axi_rdata_converter_4_signal);
+ mp_m_axi_rresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_4");
+ mp_m_axi_rresp_converter_4->vector_in(m_axi_split_rresp_out_4);
+ mp_m_axi_rresp_converter_4->vector_out(m_m_axi_rresp_converter_4_signal);
+ mp_M04_AXI_transactor->RRESP(m_m_axi_rresp_converter_4_signal);
+ mp_m_axi_rvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_4");
+ mp_m_axi_rvalid_converter_4->vector_in(m_axi_split_rvalid_out_4);
+ mp_m_axi_rvalid_converter_4->scalar_out(m_m_axi_rvalid_converter_4_signal);
+ mp_M04_AXI_transactor->RVALID(m_m_axi_rvalid_converter_4_signal);
+ mp_m_axi_rready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_4");
+ mp_m_axi_rready_converter_4->scalar_in(m_m_axi_rready_converter_4_signal);
+ mp_m_axi_rready_converter_4->vector_out(m_axi_concat_rready_out_4);
+ mp_M04_AXI_transactor->RREADY(m_m_axi_rready_converter_4_signal);
+ mp_M04_AXI_transactor->CLK(aclk);
+ mp_M04_AXI_transactor->RST(aresetn);
+
+ // M04_AXI' transactor sockets
+
+ mp_impl->initiator_4_rd_socket->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_impl->initiator_4_wr_socket->bind(*(mp_M04_AXI_transactor->wr_socket));
+ }
+ else
+ {
+ }
+
}
#endif // XM_SYSTEMC
@@ -2134,6 +2532,26 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_rresp_converter_3 = NULL;
mp_m_axi_rvalid_converter_3 = NULL;
mp_m_axi_rready_converter_3 = NULL;
+ mp_M04_AXI_transactor = NULL;
+ mp_m_axi_awaddr_converter_4 = NULL;
+ mp_m_axi_awprot_converter_4 = NULL;
+ mp_m_axi_awvalid_converter_4 = NULL;
+ mp_m_axi_awready_converter_4 = NULL;
+ mp_m_axi_wdata_converter_4 = NULL;
+ mp_m_axi_wstrb_converter_4 = NULL;
+ mp_m_axi_wvalid_converter_4 = NULL;
+ mp_m_axi_wready_converter_4 = NULL;
+ mp_m_axi_bresp_converter_4 = NULL;
+ mp_m_axi_bvalid_converter_4 = NULL;
+ mp_m_axi_bready_converter_4 = NULL;
+ mp_m_axi_araddr_converter_4 = NULL;
+ mp_m_axi_arprot_converter_4 = NULL;
+ mp_m_axi_arvalid_converter_4 = NULL;
+ mp_m_axi_arready_converter_4 = NULL;
+ mp_m_axi_rdata_converter_4 = NULL;
+ mp_m_axi_rresp_converter_4 = NULL;
+ mp_m_axi_rvalid_converter_4 = NULL;
+ mp_m_axi_rready_converter_4 = NULL;
// initialize junctures
mp_m_axi_concat_araddr = NULL;
@@ -2155,79 +2573,79 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_split_rresp = NULL;
mp_m_axi_split_rvalid = NULL;
mp_m_axi_split_wready = NULL;
- mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_awaddr");
+ mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_awaddr");
mp_m_axi_concat_awaddr->in_port[0](m_axi_concat_awaddr_out_0);
mp_m_axi_concat_awaddr->out_port(m_axi_awaddr);
mp_m_axi_concat_awaddr->offset_port(0, 0);
- mp_m_axi_concat_awprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_awprot");
+ mp_m_axi_concat_awprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_awprot");
mp_m_axi_concat_awprot->in_port[0](m_axi_concat_awprot_out_0);
mp_m_axi_concat_awprot->out_port(m_axi_awprot);
mp_m_axi_concat_awprot->offset_port(0, 0);
- mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_awvalid");
+ mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_awvalid");
mp_m_axi_concat_awvalid->in_port[0](m_axi_concat_awvalid_out_0);
mp_m_axi_concat_awvalid->out_port(m_axi_awvalid);
mp_m_axi_concat_awvalid->offset_port(0, 0);
- mp_m_axi_split_awready = new xsc::xsc_split<4, 4>("m_axi_split_awready");
+ mp_m_axi_split_awready = new xsc::xsc_split<5, 5>("m_axi_split_awready");
mp_m_axi_split_awready->in_port(m_axi_awready);
mp_m_axi_split_awready->out_port[0](m_axi_split_awready_out_0);
mp_m_axi_split_awready->add_mask(0,1,0);
- mp_m_axi_concat_wdata = new xsc::xsc_concatenator<128, 4>("m_axi_concat_wdata");
+ mp_m_axi_concat_wdata = new xsc::xsc_concatenator<160, 5>("m_axi_concat_wdata");
mp_m_axi_concat_wdata->in_port[0](m_axi_concat_wdata_out_0);
mp_m_axi_concat_wdata->out_port(m_axi_wdata);
mp_m_axi_concat_wdata->offset_port(0, 0);
- mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<16, 4>("m_axi_concat_wstrb");
+ mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<20, 5>("m_axi_concat_wstrb");
mp_m_axi_concat_wstrb->in_port[0](m_axi_concat_wstrb_out_0);
mp_m_axi_concat_wstrb->out_port(m_axi_wstrb);
mp_m_axi_concat_wstrb->offset_port(0, 0);
- mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_wvalid");
+ mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_wvalid");
mp_m_axi_concat_wvalid->in_port[0](m_axi_concat_wvalid_out_0);
mp_m_axi_concat_wvalid->out_port(m_axi_wvalid);
mp_m_axi_concat_wvalid->offset_port(0, 0);
- mp_m_axi_split_wready = new xsc::xsc_split<4, 4>("m_axi_split_wready");
+ mp_m_axi_split_wready = new xsc::xsc_split<5, 5>("m_axi_split_wready");
mp_m_axi_split_wready->in_port(m_axi_wready);
mp_m_axi_split_wready->out_port[0](m_axi_split_wready_out_0);
mp_m_axi_split_wready->add_mask(0,1,0);
- mp_m_axi_split_bresp = new xsc::xsc_split<8, 4>("m_axi_split_bresp");
+ mp_m_axi_split_bresp = new xsc::xsc_split<10, 5>("m_axi_split_bresp");
mp_m_axi_split_bresp->in_port(m_axi_bresp);
mp_m_axi_split_bresp->out_port[0](m_axi_split_bresp_out_0);
mp_m_axi_split_bresp->add_mask(0,2,0);
- mp_m_axi_split_bvalid = new xsc::xsc_split<4, 4>("m_axi_split_bvalid");
+ mp_m_axi_split_bvalid = new xsc::xsc_split<5, 5>("m_axi_split_bvalid");
mp_m_axi_split_bvalid->in_port(m_axi_bvalid);
mp_m_axi_split_bvalid->out_port[0](m_axi_split_bvalid_out_0);
mp_m_axi_split_bvalid->add_mask(0,1,0);
- mp_m_axi_concat_bready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_bready");
+ mp_m_axi_concat_bready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_bready");
mp_m_axi_concat_bready->in_port[0](m_axi_concat_bready_out_0);
mp_m_axi_concat_bready->out_port(m_axi_bready);
mp_m_axi_concat_bready->offset_port(0, 0);
- mp_m_axi_concat_araddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_araddr");
+ mp_m_axi_concat_araddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_araddr");
mp_m_axi_concat_araddr->in_port[0](m_axi_concat_araddr_out_0);
mp_m_axi_concat_araddr->out_port(m_axi_araddr);
mp_m_axi_concat_araddr->offset_port(0, 0);
- mp_m_axi_concat_arprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_arprot");
+ mp_m_axi_concat_arprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_arprot");
mp_m_axi_concat_arprot->in_port[0](m_axi_concat_arprot_out_0);
mp_m_axi_concat_arprot->out_port(m_axi_arprot);
mp_m_axi_concat_arprot->offset_port(0, 0);
- mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_arvalid");
+ mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_arvalid");
mp_m_axi_concat_arvalid->in_port[0](m_axi_concat_arvalid_out_0);
mp_m_axi_concat_arvalid->out_port(m_axi_arvalid);
mp_m_axi_concat_arvalid->offset_port(0, 0);
- mp_m_axi_split_arready = new xsc::xsc_split<4, 4>("m_axi_split_arready");
+ mp_m_axi_split_arready = new xsc::xsc_split<5, 5>("m_axi_split_arready");
mp_m_axi_split_arready->in_port(m_axi_arready);
mp_m_axi_split_arready->out_port[0](m_axi_split_arready_out_0);
mp_m_axi_split_arready->add_mask(0,1,0);
- mp_m_axi_split_rdata = new xsc::xsc_split<128, 4>("m_axi_split_rdata");
+ mp_m_axi_split_rdata = new xsc::xsc_split<160, 5>("m_axi_split_rdata");
mp_m_axi_split_rdata->in_port(m_axi_rdata);
mp_m_axi_split_rdata->out_port[0](m_axi_split_rdata_out_0);
mp_m_axi_split_rdata->add_mask(0,32,0);
- mp_m_axi_split_rresp = new xsc::xsc_split<8, 4>("m_axi_split_rresp");
+ mp_m_axi_split_rresp = new xsc::xsc_split<10, 5>("m_axi_split_rresp");
mp_m_axi_split_rresp->in_port(m_axi_rresp);
mp_m_axi_split_rresp->out_port[0](m_axi_split_rresp_out_0);
mp_m_axi_split_rresp->add_mask(0,2,0);
- mp_m_axi_split_rvalid = new xsc::xsc_split<4, 4>("m_axi_split_rvalid");
+ mp_m_axi_split_rvalid = new xsc::xsc_split<5, 5>("m_axi_split_rvalid");
mp_m_axi_split_rvalid->in_port(m_axi_rvalid);
mp_m_axi_split_rvalid->out_port[0](m_axi_split_rvalid_out_0);
mp_m_axi_split_rvalid->add_mask(0,1,0);
- mp_m_axi_concat_rready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_rready");
+ mp_m_axi_concat_rready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_rready");
mp_m_axi_concat_rready->in_port[0](m_axi_concat_rready_out_0);
mp_m_axi_concat_rready->out_port(m_axi_rready);
mp_m_axi_concat_rready->offset_port(0, 0);
@@ -2369,6 +2787,52 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_split_rvalid->add_mask(3,4,3);
mp_m_axi_concat_rready->in_port[3](m_axi_concat_rready_out_3);
mp_m_axi_concat_rready->offset_port(3, 3);
+ mp_m_axi_concat_awaddr->in_port[4](m_axi_concat_awaddr_out_4);
+ mp_m_axi_concat_awaddr->offset_port(4, 128);
+ mp_m_axi_concat_awprot->in_port[4](m_axi_concat_awprot_out_4);
+ mp_m_axi_concat_awprot->offset_port(4, 12);
+ mp_m_axi_concat_awvalid->in_port[4](m_axi_concat_awvalid_out_4);
+ mp_m_axi_concat_awvalid->offset_port(4, 4);
+
+ mp_m_axi_split_awready->out_port[4](m_axi_split_awready_out_4);
+ mp_m_axi_split_awready->add_mask(4,5,4);
+ mp_m_axi_concat_wdata->in_port[4](m_axi_concat_wdata_out_4);
+ mp_m_axi_concat_wdata->offset_port(4, 128);
+ mp_m_axi_concat_wstrb->in_port[4](m_axi_concat_wstrb_out_4);
+ mp_m_axi_concat_wstrb->offset_port(4, 16);
+ mp_m_axi_concat_wvalid->in_port[4](m_axi_concat_wvalid_out_4);
+ mp_m_axi_concat_wvalid->offset_port(4, 4);
+
+ mp_m_axi_split_wready->out_port[4](m_axi_split_wready_out_4);
+ mp_m_axi_split_wready->add_mask(4,5,4);
+
+ mp_m_axi_split_bresp->out_port[4](m_axi_split_bresp_out_4);
+ mp_m_axi_split_bresp->add_mask(4,10,8);
+
+ mp_m_axi_split_bvalid->out_port[4](m_axi_split_bvalid_out_4);
+ mp_m_axi_split_bvalid->add_mask(4,5,4);
+ mp_m_axi_concat_bready->in_port[4](m_axi_concat_bready_out_4);
+ mp_m_axi_concat_bready->offset_port(4, 4);
+ mp_m_axi_concat_araddr->in_port[4](m_axi_concat_araddr_out_4);
+ mp_m_axi_concat_araddr->offset_port(4, 128);
+ mp_m_axi_concat_arprot->in_port[4](m_axi_concat_arprot_out_4);
+ mp_m_axi_concat_arprot->offset_port(4, 12);
+ mp_m_axi_concat_arvalid->in_port[4](m_axi_concat_arvalid_out_4);
+ mp_m_axi_concat_arvalid->offset_port(4, 4);
+
+ mp_m_axi_split_arready->out_port[4](m_axi_split_arready_out_4);
+ mp_m_axi_split_arready->add_mask(4,5,4);
+
+ mp_m_axi_split_rdata->out_port[4](m_axi_split_rdata_out_4);
+ mp_m_axi_split_rdata->add_mask(4,160,128);
+
+ mp_m_axi_split_rresp->out_port[4](m_axi_split_rresp_out_4);
+ mp_m_axi_split_rresp->add_mask(4,10,8);
+
+ mp_m_axi_split_rvalid->out_port[4](m_axi_split_rvalid_out_4);
+ mp_m_axi_split_rvalid->add_mask(4,5,4);
+ mp_m_axi_concat_rready->in_port[4](m_axi_concat_rready_out_4);
+ mp_m_axi_concat_rready->offset_port(4, 4);
// initialize socket stubs
@@ -2527,79 +2991,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M00_AXI' transactor ports
- mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_0");
+ mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_0");
mp_m_axi_awaddr_converter_0->vector_in(m_m_axi_awaddr_converter_0_signal);
mp_m_axi_awaddr_converter_0->vector_out(m_axi_concat_awaddr_out_0);
mp_M00_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_0_signal);
- mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_0");
+ mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_0");
mp_m_axi_awprot_converter_0->vector_in(m_m_axi_awprot_converter_0_signal);
mp_m_axi_awprot_converter_0->vector_out(m_axi_concat_awprot_out_0);
mp_M00_AXI_transactor->AWPROT(m_m_axi_awprot_converter_0_signal);
- mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_0");
+ mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_0");
mp_m_axi_awvalid_converter_0->scalar_in(m_m_axi_awvalid_converter_0_signal);
mp_m_axi_awvalid_converter_0->vector_out(m_axi_concat_awvalid_out_0);
mp_M00_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_0_signal);
- mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_0");
+ mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_0");
mp_m_axi_awready_converter_0->vector_in(m_axi_split_awready_out_0);
mp_m_axi_awready_converter_0->scalar_out(m_m_axi_awready_converter_0_signal);
mp_M00_AXI_transactor->AWREADY(m_m_axi_awready_converter_0_signal);
- mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_0");
+ mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_0");
mp_m_axi_wdata_converter_0->vector_in(m_m_axi_wdata_converter_0_signal);
mp_m_axi_wdata_converter_0->vector_out(m_axi_concat_wdata_out_0);
mp_M00_AXI_transactor->WDATA(m_m_axi_wdata_converter_0_signal);
- mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_0");
+ mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_0");
mp_m_axi_wstrb_converter_0->vector_in(m_m_axi_wstrb_converter_0_signal);
mp_m_axi_wstrb_converter_0->vector_out(m_axi_concat_wstrb_out_0);
mp_M00_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_0_signal);
- mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_0");
+ mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_0");
mp_m_axi_wvalid_converter_0->scalar_in(m_m_axi_wvalid_converter_0_signal);
mp_m_axi_wvalid_converter_0->vector_out(m_axi_concat_wvalid_out_0);
mp_M00_AXI_transactor->WVALID(m_m_axi_wvalid_converter_0_signal);
- mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_0");
+ mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_0");
mp_m_axi_wready_converter_0->vector_in(m_axi_split_wready_out_0);
mp_m_axi_wready_converter_0->scalar_out(m_m_axi_wready_converter_0_signal);
mp_M00_AXI_transactor->WREADY(m_m_axi_wready_converter_0_signal);
- mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_0");
+ mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_0");
mp_m_axi_bresp_converter_0->vector_in(m_axi_split_bresp_out_0);
mp_m_axi_bresp_converter_0->vector_out(m_m_axi_bresp_converter_0_signal);
mp_M00_AXI_transactor->BRESP(m_m_axi_bresp_converter_0_signal);
- mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_0");
+ mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_0");
mp_m_axi_bvalid_converter_0->vector_in(m_axi_split_bvalid_out_0);
mp_m_axi_bvalid_converter_0->scalar_out(m_m_axi_bvalid_converter_0_signal);
mp_M00_AXI_transactor->BVALID(m_m_axi_bvalid_converter_0_signal);
- mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_0");
+ mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_0");
mp_m_axi_bready_converter_0->scalar_in(m_m_axi_bready_converter_0_signal);
mp_m_axi_bready_converter_0->vector_out(m_axi_concat_bready_out_0);
mp_M00_AXI_transactor->BREADY(m_m_axi_bready_converter_0_signal);
- mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_0");
+ mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_0");
mp_m_axi_araddr_converter_0->vector_in(m_m_axi_araddr_converter_0_signal);
mp_m_axi_araddr_converter_0->vector_out(m_axi_concat_araddr_out_0);
mp_M00_AXI_transactor->ARADDR(m_m_axi_araddr_converter_0_signal);
- mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_0");
+ mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_0");
mp_m_axi_arprot_converter_0->vector_in(m_m_axi_arprot_converter_0_signal);
mp_m_axi_arprot_converter_0->vector_out(m_axi_concat_arprot_out_0);
mp_M00_AXI_transactor->ARPROT(m_m_axi_arprot_converter_0_signal);
- mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_0");
+ mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_0");
mp_m_axi_arvalid_converter_0->scalar_in(m_m_axi_arvalid_converter_0_signal);
mp_m_axi_arvalid_converter_0->vector_out(m_axi_concat_arvalid_out_0);
mp_M00_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_0_signal);
- mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_0");
+ mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_0");
mp_m_axi_arready_converter_0->vector_in(m_axi_split_arready_out_0);
mp_m_axi_arready_converter_0->scalar_out(m_m_axi_arready_converter_0_signal);
mp_M00_AXI_transactor->ARREADY(m_m_axi_arready_converter_0_signal);
- mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_0");
+ mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_0");
mp_m_axi_rdata_converter_0->vector_in(m_axi_split_rdata_out_0);
mp_m_axi_rdata_converter_0->vector_out(m_m_axi_rdata_converter_0_signal);
mp_M00_AXI_transactor->RDATA(m_m_axi_rdata_converter_0_signal);
- mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_0");
+ mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_0");
mp_m_axi_rresp_converter_0->vector_in(m_axi_split_rresp_out_0);
mp_m_axi_rresp_converter_0->vector_out(m_m_axi_rresp_converter_0_signal);
mp_M00_AXI_transactor->RRESP(m_m_axi_rresp_converter_0_signal);
- mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_0");
+ mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_0");
mp_m_axi_rvalid_converter_0->vector_in(m_axi_split_rvalid_out_0);
mp_m_axi_rvalid_converter_0->scalar_out(m_m_axi_rvalid_converter_0_signal);
mp_M00_AXI_transactor->RVALID(m_m_axi_rvalid_converter_0_signal);
- mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_0");
+ mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_0");
mp_m_axi_rready_converter_0->scalar_in(m_m_axi_rready_converter_0_signal);
mp_m_axi_rready_converter_0->vector_out(m_axi_concat_rready_out_0);
mp_M00_AXI_transactor->RREADY(m_m_axi_rready_converter_0_signal);
@@ -2660,79 +3124,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M01_AXI' transactor ports
- mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_1");
+ mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_1");
mp_m_axi_awaddr_converter_1->vector_in(m_m_axi_awaddr_converter_1_signal);
mp_m_axi_awaddr_converter_1->vector_out(m_axi_concat_awaddr_out_1);
mp_M01_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_1_signal);
- mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_1");
+ mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_1");
mp_m_axi_awprot_converter_1->vector_in(m_m_axi_awprot_converter_1_signal);
mp_m_axi_awprot_converter_1->vector_out(m_axi_concat_awprot_out_1);
mp_M01_AXI_transactor->AWPROT(m_m_axi_awprot_converter_1_signal);
- mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_1");
+ mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_1");
mp_m_axi_awvalid_converter_1->scalar_in(m_m_axi_awvalid_converter_1_signal);
mp_m_axi_awvalid_converter_1->vector_out(m_axi_concat_awvalid_out_1);
mp_M01_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_1_signal);
- mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_1");
+ mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_1");
mp_m_axi_awready_converter_1->vector_in(m_axi_split_awready_out_1);
mp_m_axi_awready_converter_1->scalar_out(m_m_axi_awready_converter_1_signal);
mp_M01_AXI_transactor->AWREADY(m_m_axi_awready_converter_1_signal);
- mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_1");
+ mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_1");
mp_m_axi_wdata_converter_1->vector_in(m_m_axi_wdata_converter_1_signal);
mp_m_axi_wdata_converter_1->vector_out(m_axi_concat_wdata_out_1);
mp_M01_AXI_transactor->WDATA(m_m_axi_wdata_converter_1_signal);
- mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_1");
+ mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_1");
mp_m_axi_wstrb_converter_1->vector_in(m_m_axi_wstrb_converter_1_signal);
mp_m_axi_wstrb_converter_1->vector_out(m_axi_concat_wstrb_out_1);
mp_M01_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_1_signal);
- mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_1");
+ mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_1");
mp_m_axi_wvalid_converter_1->scalar_in(m_m_axi_wvalid_converter_1_signal);
mp_m_axi_wvalid_converter_1->vector_out(m_axi_concat_wvalid_out_1);
mp_M01_AXI_transactor->WVALID(m_m_axi_wvalid_converter_1_signal);
- mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_1");
+ mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_1");
mp_m_axi_wready_converter_1->vector_in(m_axi_split_wready_out_1);
mp_m_axi_wready_converter_1->scalar_out(m_m_axi_wready_converter_1_signal);
mp_M01_AXI_transactor->WREADY(m_m_axi_wready_converter_1_signal);
- mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_1");
+ mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_1");
mp_m_axi_bresp_converter_1->vector_in(m_axi_split_bresp_out_1);
mp_m_axi_bresp_converter_1->vector_out(m_m_axi_bresp_converter_1_signal);
mp_M01_AXI_transactor->BRESP(m_m_axi_bresp_converter_1_signal);
- mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_1");
+ mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_1");
mp_m_axi_bvalid_converter_1->vector_in(m_axi_split_bvalid_out_1);
mp_m_axi_bvalid_converter_1->scalar_out(m_m_axi_bvalid_converter_1_signal);
mp_M01_AXI_transactor->BVALID(m_m_axi_bvalid_converter_1_signal);
- mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_1");
+ mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_1");
mp_m_axi_bready_converter_1->scalar_in(m_m_axi_bready_converter_1_signal);
mp_m_axi_bready_converter_1->vector_out(m_axi_concat_bready_out_1);
mp_M01_AXI_transactor->BREADY(m_m_axi_bready_converter_1_signal);
- mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_1");
+ mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_1");
mp_m_axi_araddr_converter_1->vector_in(m_m_axi_araddr_converter_1_signal);
mp_m_axi_araddr_converter_1->vector_out(m_axi_concat_araddr_out_1);
mp_M01_AXI_transactor->ARADDR(m_m_axi_araddr_converter_1_signal);
- mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_1");
+ mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_1");
mp_m_axi_arprot_converter_1->vector_in(m_m_axi_arprot_converter_1_signal);
mp_m_axi_arprot_converter_1->vector_out(m_axi_concat_arprot_out_1);
mp_M01_AXI_transactor->ARPROT(m_m_axi_arprot_converter_1_signal);
- mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_1");
+ mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_1");
mp_m_axi_arvalid_converter_1->scalar_in(m_m_axi_arvalid_converter_1_signal);
mp_m_axi_arvalid_converter_1->vector_out(m_axi_concat_arvalid_out_1);
mp_M01_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_1_signal);
- mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_1");
+ mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_1");
mp_m_axi_arready_converter_1->vector_in(m_axi_split_arready_out_1);
mp_m_axi_arready_converter_1->scalar_out(m_m_axi_arready_converter_1_signal);
mp_M01_AXI_transactor->ARREADY(m_m_axi_arready_converter_1_signal);
- mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_1");
+ mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_1");
mp_m_axi_rdata_converter_1->vector_in(m_axi_split_rdata_out_1);
mp_m_axi_rdata_converter_1->vector_out(m_m_axi_rdata_converter_1_signal);
mp_M01_AXI_transactor->RDATA(m_m_axi_rdata_converter_1_signal);
- mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_1");
+ mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_1");
mp_m_axi_rresp_converter_1->vector_in(m_axi_split_rresp_out_1);
mp_m_axi_rresp_converter_1->vector_out(m_m_axi_rresp_converter_1_signal);
mp_M01_AXI_transactor->RRESP(m_m_axi_rresp_converter_1_signal);
- mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_1");
+ mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_1");
mp_m_axi_rvalid_converter_1->vector_in(m_axi_split_rvalid_out_1);
mp_m_axi_rvalid_converter_1->scalar_out(m_m_axi_rvalid_converter_1_signal);
mp_M01_AXI_transactor->RVALID(m_m_axi_rvalid_converter_1_signal);
- mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_1");
+ mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_1");
mp_m_axi_rready_converter_1->scalar_in(m_m_axi_rready_converter_1_signal);
mp_m_axi_rready_converter_1->vector_out(m_axi_concat_rready_out_1);
mp_M01_AXI_transactor->RREADY(m_m_axi_rready_converter_1_signal);
@@ -2793,79 +3257,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M02_AXI' transactor ports
- mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_2");
+ mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_2");
mp_m_axi_awaddr_converter_2->vector_in(m_m_axi_awaddr_converter_2_signal);
mp_m_axi_awaddr_converter_2->vector_out(m_axi_concat_awaddr_out_2);
mp_M02_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_2_signal);
- mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_2");
+ mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_2");
mp_m_axi_awprot_converter_2->vector_in(m_m_axi_awprot_converter_2_signal);
mp_m_axi_awprot_converter_2->vector_out(m_axi_concat_awprot_out_2);
mp_M02_AXI_transactor->AWPROT(m_m_axi_awprot_converter_2_signal);
- mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_2");
+ mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_2");
mp_m_axi_awvalid_converter_2->scalar_in(m_m_axi_awvalid_converter_2_signal);
mp_m_axi_awvalid_converter_2->vector_out(m_axi_concat_awvalid_out_2);
mp_M02_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_2_signal);
- mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_2");
+ mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_2");
mp_m_axi_awready_converter_2->vector_in(m_axi_split_awready_out_2);
mp_m_axi_awready_converter_2->scalar_out(m_m_axi_awready_converter_2_signal);
mp_M02_AXI_transactor->AWREADY(m_m_axi_awready_converter_2_signal);
- mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_2");
+ mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_2");
mp_m_axi_wdata_converter_2->vector_in(m_m_axi_wdata_converter_2_signal);
mp_m_axi_wdata_converter_2->vector_out(m_axi_concat_wdata_out_2);
mp_M02_AXI_transactor->WDATA(m_m_axi_wdata_converter_2_signal);
- mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_2");
+ mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_2");
mp_m_axi_wstrb_converter_2->vector_in(m_m_axi_wstrb_converter_2_signal);
mp_m_axi_wstrb_converter_2->vector_out(m_axi_concat_wstrb_out_2);
mp_M02_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_2_signal);
- mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_2");
+ mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_2");
mp_m_axi_wvalid_converter_2->scalar_in(m_m_axi_wvalid_converter_2_signal);
mp_m_axi_wvalid_converter_2->vector_out(m_axi_concat_wvalid_out_2);
mp_M02_AXI_transactor->WVALID(m_m_axi_wvalid_converter_2_signal);
- mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_2");
+ mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_2");
mp_m_axi_wready_converter_2->vector_in(m_axi_split_wready_out_2);
mp_m_axi_wready_converter_2->scalar_out(m_m_axi_wready_converter_2_signal);
mp_M02_AXI_transactor->WREADY(m_m_axi_wready_converter_2_signal);
- mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_2");
+ mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_2");
mp_m_axi_bresp_converter_2->vector_in(m_axi_split_bresp_out_2);
mp_m_axi_bresp_converter_2->vector_out(m_m_axi_bresp_converter_2_signal);
mp_M02_AXI_transactor->BRESP(m_m_axi_bresp_converter_2_signal);
- mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_2");
+ mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_2");
mp_m_axi_bvalid_converter_2->vector_in(m_axi_split_bvalid_out_2);
mp_m_axi_bvalid_converter_2->scalar_out(m_m_axi_bvalid_converter_2_signal);
mp_M02_AXI_transactor->BVALID(m_m_axi_bvalid_converter_2_signal);
- mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_2");
+ mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_2");
mp_m_axi_bready_converter_2->scalar_in(m_m_axi_bready_converter_2_signal);
mp_m_axi_bready_converter_2->vector_out(m_axi_concat_bready_out_2);
mp_M02_AXI_transactor->BREADY(m_m_axi_bready_converter_2_signal);
- mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_2");
+ mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_2");
mp_m_axi_araddr_converter_2->vector_in(m_m_axi_araddr_converter_2_signal);
mp_m_axi_araddr_converter_2->vector_out(m_axi_concat_araddr_out_2);
mp_M02_AXI_transactor->ARADDR(m_m_axi_araddr_converter_2_signal);
- mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_2");
+ mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_2");
mp_m_axi_arprot_converter_2->vector_in(m_m_axi_arprot_converter_2_signal);
mp_m_axi_arprot_converter_2->vector_out(m_axi_concat_arprot_out_2);
mp_M02_AXI_transactor->ARPROT(m_m_axi_arprot_converter_2_signal);
- mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_2");
+ mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_2");
mp_m_axi_arvalid_converter_2->scalar_in(m_m_axi_arvalid_converter_2_signal);
mp_m_axi_arvalid_converter_2->vector_out(m_axi_concat_arvalid_out_2);
mp_M02_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_2_signal);
- mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_2");
+ mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_2");
mp_m_axi_arready_converter_2->vector_in(m_axi_split_arready_out_2);
mp_m_axi_arready_converter_2->scalar_out(m_m_axi_arready_converter_2_signal);
mp_M02_AXI_transactor->ARREADY(m_m_axi_arready_converter_2_signal);
- mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_2");
+ mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_2");
mp_m_axi_rdata_converter_2->vector_in(m_axi_split_rdata_out_2);
mp_m_axi_rdata_converter_2->vector_out(m_m_axi_rdata_converter_2_signal);
mp_M02_AXI_transactor->RDATA(m_m_axi_rdata_converter_2_signal);
- mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_2");
+ mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_2");
mp_m_axi_rresp_converter_2->vector_in(m_axi_split_rresp_out_2);
mp_m_axi_rresp_converter_2->vector_out(m_m_axi_rresp_converter_2_signal);
mp_M02_AXI_transactor->RRESP(m_m_axi_rresp_converter_2_signal);
- mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_2");
+ mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_2");
mp_m_axi_rvalid_converter_2->vector_in(m_axi_split_rvalid_out_2);
mp_m_axi_rvalid_converter_2->scalar_out(m_m_axi_rvalid_converter_2_signal);
mp_M02_AXI_transactor->RVALID(m_m_axi_rvalid_converter_2_signal);
- mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_2");
+ mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_2");
mp_m_axi_rready_converter_2->scalar_in(m_m_axi_rready_converter_2_signal);
mp_m_axi_rready_converter_2->vector_out(m_axi_concat_rready_out_2);
mp_M02_AXI_transactor->RREADY(m_m_axi_rready_converter_2_signal);
@@ -2908,8 +3372,8 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
M03_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
M03_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
M03_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
- M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
- M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+ M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
M03_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
M03_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
M03_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
@@ -2926,79 +3390,79 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
// M03_AXI' transactor ports
- mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_3");
+ mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_3");
mp_m_axi_awaddr_converter_3->vector_in(m_m_axi_awaddr_converter_3_signal);
mp_m_axi_awaddr_converter_3->vector_out(m_axi_concat_awaddr_out_3);
mp_M03_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_3_signal);
- mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_3");
+ mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_3");
mp_m_axi_awprot_converter_3->vector_in(m_m_axi_awprot_converter_3_signal);
mp_m_axi_awprot_converter_3->vector_out(m_axi_concat_awprot_out_3);
mp_M03_AXI_transactor->AWPROT(m_m_axi_awprot_converter_3_signal);
- mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_3");
+ mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_3");
mp_m_axi_awvalid_converter_3->scalar_in(m_m_axi_awvalid_converter_3_signal);
mp_m_axi_awvalid_converter_3->vector_out(m_axi_concat_awvalid_out_3);
mp_M03_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_3_signal);
- mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_3");
+ mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_3");
mp_m_axi_awready_converter_3->vector_in(m_axi_split_awready_out_3);
mp_m_axi_awready_converter_3->scalar_out(m_m_axi_awready_converter_3_signal);
mp_M03_AXI_transactor->AWREADY(m_m_axi_awready_converter_3_signal);
- mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_3");
+ mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_3");
mp_m_axi_wdata_converter_3->vector_in(m_m_axi_wdata_converter_3_signal);
mp_m_axi_wdata_converter_3->vector_out(m_axi_concat_wdata_out_3);
mp_M03_AXI_transactor->WDATA(m_m_axi_wdata_converter_3_signal);
- mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_3");
+ mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_3");
mp_m_axi_wstrb_converter_3->vector_in(m_m_axi_wstrb_converter_3_signal);
mp_m_axi_wstrb_converter_3->vector_out(m_axi_concat_wstrb_out_3);
mp_M03_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_3_signal);
- mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_3");
+ mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_3");
mp_m_axi_wvalid_converter_3->scalar_in(m_m_axi_wvalid_converter_3_signal);
mp_m_axi_wvalid_converter_3->vector_out(m_axi_concat_wvalid_out_3);
mp_M03_AXI_transactor->WVALID(m_m_axi_wvalid_converter_3_signal);
- mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_3");
+ mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_3");
mp_m_axi_wready_converter_3->vector_in(m_axi_split_wready_out_3);
mp_m_axi_wready_converter_3->scalar_out(m_m_axi_wready_converter_3_signal);
mp_M03_AXI_transactor->WREADY(m_m_axi_wready_converter_3_signal);
- mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_3");
+ mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_3");
mp_m_axi_bresp_converter_3->vector_in(m_axi_split_bresp_out_3);
mp_m_axi_bresp_converter_3->vector_out(m_m_axi_bresp_converter_3_signal);
mp_M03_AXI_transactor->BRESP(m_m_axi_bresp_converter_3_signal);
- mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_3");
+ mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_3");
mp_m_axi_bvalid_converter_3->vector_in(m_axi_split_bvalid_out_3);
mp_m_axi_bvalid_converter_3->scalar_out(m_m_axi_bvalid_converter_3_signal);
mp_M03_AXI_transactor->BVALID(m_m_axi_bvalid_converter_3_signal);
- mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_3");
+ mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_3");
mp_m_axi_bready_converter_3->scalar_in(m_m_axi_bready_converter_3_signal);
mp_m_axi_bready_converter_3->vector_out(m_axi_concat_bready_out_3);
mp_M03_AXI_transactor->BREADY(m_m_axi_bready_converter_3_signal);
- mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_3");
+ mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_3");
mp_m_axi_araddr_converter_3->vector_in(m_m_axi_araddr_converter_3_signal);
mp_m_axi_araddr_converter_3->vector_out(m_axi_concat_araddr_out_3);
mp_M03_AXI_transactor->ARADDR(m_m_axi_araddr_converter_3_signal);
- mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_3");
+ mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_3");
mp_m_axi_arprot_converter_3->vector_in(m_m_axi_arprot_converter_3_signal);
mp_m_axi_arprot_converter_3->vector_out(m_axi_concat_arprot_out_3);
mp_M03_AXI_transactor->ARPROT(m_m_axi_arprot_converter_3_signal);
- mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_3");
+ mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_3");
mp_m_axi_arvalid_converter_3->scalar_in(m_m_axi_arvalid_converter_3_signal);
mp_m_axi_arvalid_converter_3->vector_out(m_axi_concat_arvalid_out_3);
mp_M03_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_3_signal);
- mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_3");
+ mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_3");
mp_m_axi_arready_converter_3->vector_in(m_axi_split_arready_out_3);
mp_m_axi_arready_converter_3->scalar_out(m_m_axi_arready_converter_3_signal);
mp_M03_AXI_transactor->ARREADY(m_m_axi_arready_converter_3_signal);
- mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_3");
+ mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_3");
mp_m_axi_rdata_converter_3->vector_in(m_axi_split_rdata_out_3);
mp_m_axi_rdata_converter_3->vector_out(m_m_axi_rdata_converter_3_signal);
mp_M03_AXI_transactor->RDATA(m_m_axi_rdata_converter_3_signal);
- mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_3");
+ mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_3");
mp_m_axi_rresp_converter_3->vector_in(m_axi_split_rresp_out_3);
mp_m_axi_rresp_converter_3->vector_out(m_m_axi_rresp_converter_3_signal);
mp_M03_AXI_transactor->RRESP(m_m_axi_rresp_converter_3_signal);
- mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_3");
+ mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_3");
mp_m_axi_rvalid_converter_3->vector_in(m_axi_split_rvalid_out_3);
mp_m_axi_rvalid_converter_3->scalar_out(m_m_axi_rvalid_converter_3_signal);
mp_M03_AXI_transactor->RVALID(m_m_axi_rvalid_converter_3_signal);
- mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_3");
+ mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_3");
mp_m_axi_rready_converter_3->scalar_in(m_m_axi_rready_converter_3_signal);
mp_m_axi_rready_converter_3->vector_out(m_axi_concat_rready_out_3);
mp_M03_AXI_transactor->RREADY(m_m_axi_rready_converter_3_signal);
@@ -3014,6 +3478,139 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
{
}
+ // configure 'M04_AXI' transactor
+
+ if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("mb_design_1_xbar_0", "M04_AXI_TLM_MODE") != 1)
+ {
+ // Instantiate Socket Stubs
+
+ // 'M04_AXI' transactor parameters
+ xsc::common_cpp::properties M04_AXI_transactor_param_props;
+ M04_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000");
+ M04_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+ M04_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+ M04_AXI_transactor_param_props.addFloat("PHASE", "0.0");
+ M04_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+ M04_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+ M04_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
+
+ mp_M04_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M04_AXI_transactor", M04_AXI_transactor_param_props);
+
+ // M04_AXI' transactor ports
+
+ mp_m_axi_awaddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_4");
+ mp_m_axi_awaddr_converter_4->vector_in(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awaddr_converter_4->vector_out(m_axi_concat_awaddr_out_4);
+ mp_M04_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_4");
+ mp_m_axi_awprot_converter_4->vector_in(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awprot_converter_4->vector_out(m_axi_concat_awprot_out_4);
+ mp_M04_AXI_transactor->AWPROT(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_4");
+ mp_m_axi_awvalid_converter_4->scalar_in(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awvalid_converter_4->vector_out(m_axi_concat_awvalid_out_4);
+ mp_M04_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_4");
+ mp_m_axi_awready_converter_4->vector_in(m_axi_split_awready_out_4);
+ mp_m_axi_awready_converter_4->scalar_out(m_m_axi_awready_converter_4_signal);
+ mp_M04_AXI_transactor->AWREADY(m_m_axi_awready_converter_4_signal);
+ mp_m_axi_wdata_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_4");
+ mp_m_axi_wdata_converter_4->vector_in(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wdata_converter_4->vector_out(m_axi_concat_wdata_out_4);
+ mp_M04_AXI_transactor->WDATA(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wstrb_converter_4 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_4");
+ mp_m_axi_wstrb_converter_4->vector_in(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wstrb_converter_4->vector_out(m_axi_concat_wstrb_out_4);
+ mp_M04_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_4");
+ mp_m_axi_wvalid_converter_4->scalar_in(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wvalid_converter_4->vector_out(m_axi_concat_wvalid_out_4);
+ mp_M04_AXI_transactor->WVALID(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_4");
+ mp_m_axi_wready_converter_4->vector_in(m_axi_split_wready_out_4);
+ mp_m_axi_wready_converter_4->scalar_out(m_m_axi_wready_converter_4_signal);
+ mp_M04_AXI_transactor->WREADY(m_m_axi_wready_converter_4_signal);
+ mp_m_axi_bresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_4");
+ mp_m_axi_bresp_converter_4->vector_in(m_axi_split_bresp_out_4);
+ mp_m_axi_bresp_converter_4->vector_out(m_m_axi_bresp_converter_4_signal);
+ mp_M04_AXI_transactor->BRESP(m_m_axi_bresp_converter_4_signal);
+ mp_m_axi_bvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_4");
+ mp_m_axi_bvalid_converter_4->vector_in(m_axi_split_bvalid_out_4);
+ mp_m_axi_bvalid_converter_4->scalar_out(m_m_axi_bvalid_converter_4_signal);
+ mp_M04_AXI_transactor->BVALID(m_m_axi_bvalid_converter_4_signal);
+ mp_m_axi_bready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_4");
+ mp_m_axi_bready_converter_4->scalar_in(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_bready_converter_4->vector_out(m_axi_concat_bready_out_4);
+ mp_M04_AXI_transactor->BREADY(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_araddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_4");
+ mp_m_axi_araddr_converter_4->vector_in(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_araddr_converter_4->vector_out(m_axi_concat_araddr_out_4);
+ mp_M04_AXI_transactor->ARADDR(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_arprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_4");
+ mp_m_axi_arprot_converter_4->vector_in(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arprot_converter_4->vector_out(m_axi_concat_arprot_out_4);
+ mp_M04_AXI_transactor->ARPROT(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_4");
+ mp_m_axi_arvalid_converter_4->scalar_in(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arvalid_converter_4->vector_out(m_axi_concat_arvalid_out_4);
+ mp_M04_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_4");
+ mp_m_axi_arready_converter_4->vector_in(m_axi_split_arready_out_4);
+ mp_m_axi_arready_converter_4->scalar_out(m_m_axi_arready_converter_4_signal);
+ mp_M04_AXI_transactor->ARREADY(m_m_axi_arready_converter_4_signal);
+ mp_m_axi_rdata_converter_4 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_4");
+ mp_m_axi_rdata_converter_4->vector_in(m_axi_split_rdata_out_4);
+ mp_m_axi_rdata_converter_4->vector_out(m_m_axi_rdata_converter_4_signal);
+ mp_M04_AXI_transactor->RDATA(m_m_axi_rdata_converter_4_signal);
+ mp_m_axi_rresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_4");
+ mp_m_axi_rresp_converter_4->vector_in(m_axi_split_rresp_out_4);
+ mp_m_axi_rresp_converter_4->vector_out(m_m_axi_rresp_converter_4_signal);
+ mp_M04_AXI_transactor->RRESP(m_m_axi_rresp_converter_4_signal);
+ mp_m_axi_rvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_4");
+ mp_m_axi_rvalid_converter_4->vector_in(m_axi_split_rvalid_out_4);
+ mp_m_axi_rvalid_converter_4->scalar_out(m_m_axi_rvalid_converter_4_signal);
+ mp_M04_AXI_transactor->RVALID(m_m_axi_rvalid_converter_4_signal);
+ mp_m_axi_rready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_4");
+ mp_m_axi_rready_converter_4->scalar_in(m_m_axi_rready_converter_4_signal);
+ mp_m_axi_rready_converter_4->vector_out(m_axi_concat_rready_out_4);
+ mp_M04_AXI_transactor->RREADY(m_m_axi_rready_converter_4_signal);
+ mp_M04_AXI_transactor->CLK(aclk);
+ mp_M04_AXI_transactor->RST(aresetn);
+
+ // M04_AXI' transactor sockets
+
+ mp_impl->initiator_4_rd_socket->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_impl->initiator_4_wr_socket->bind(*(mp_M04_AXI_transactor->wr_socket));
+ }
+ else
+ {
+ }
+
}
#endif // RIVIERA
@@ -3120,6 +3717,26 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_rresp_converter_3 = NULL;
mp_m_axi_rvalid_converter_3 = NULL;
mp_m_axi_rready_converter_3 = NULL;
+ mp_M04_AXI_transactor = NULL;
+ mp_m_axi_awaddr_converter_4 = NULL;
+ mp_m_axi_awprot_converter_4 = NULL;
+ mp_m_axi_awvalid_converter_4 = NULL;
+ mp_m_axi_awready_converter_4 = NULL;
+ mp_m_axi_wdata_converter_4 = NULL;
+ mp_m_axi_wstrb_converter_4 = NULL;
+ mp_m_axi_wvalid_converter_4 = NULL;
+ mp_m_axi_wready_converter_4 = NULL;
+ mp_m_axi_bresp_converter_4 = NULL;
+ mp_m_axi_bvalid_converter_4 = NULL;
+ mp_m_axi_bready_converter_4 = NULL;
+ mp_m_axi_araddr_converter_4 = NULL;
+ mp_m_axi_arprot_converter_4 = NULL;
+ mp_m_axi_arvalid_converter_4 = NULL;
+ mp_m_axi_arready_converter_4 = NULL;
+ mp_m_axi_rdata_converter_4 = NULL;
+ mp_m_axi_rresp_converter_4 = NULL;
+ mp_m_axi_rvalid_converter_4 = NULL;
+ mp_m_axi_rready_converter_4 = NULL;
// initialize port junctures
mp_m_axi_concat_araddr = NULL;
@@ -3267,152 +3884,152 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M00_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M00_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M00_AXI_transactor", M00_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_0");
- mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_awaddr");
+ mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_0");
+ mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_awaddr");
mp_m_axi_concat_awaddr->in_port[0](m_axi_concat_awaddr_out_0);
mp_m_axi_concat_awaddr->out_port(m_axi_awaddr);
mp_m_axi_concat_awaddr->offset_port(0, 0);
mp_m_axi_awaddr_converter_0->vector_in(m_m_axi_awaddr_converter_0_signal);
mp_m_axi_awaddr_converter_0->vector_out(m_axi_concat_awaddr_out_0);
mp_M00_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_0_signal);
- mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_0");
- mp_m_axi_concat_awprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_awprot");
+ mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_0");
+ mp_m_axi_concat_awprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_awprot");
mp_m_axi_concat_awprot->in_port[0](m_axi_concat_awprot_out_0);
mp_m_axi_concat_awprot->out_port(m_axi_awprot);
mp_m_axi_concat_awprot->offset_port(0, 0);
mp_m_axi_awprot_converter_0->vector_in(m_m_axi_awprot_converter_0_signal);
mp_m_axi_awprot_converter_0->vector_out(m_axi_concat_awprot_out_0);
mp_M00_AXI_transactor->AWPROT(m_m_axi_awprot_converter_0_signal);
- mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_0");
- mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_awvalid");
+ mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_0");
+ mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_awvalid");
mp_m_axi_concat_awvalid->in_port[0](m_axi_concat_awvalid_out_0);
mp_m_axi_concat_awvalid->out_port(m_axi_awvalid);
mp_m_axi_concat_awvalid->offset_port(0, 0);
mp_m_axi_awvalid_converter_0->scalar_in(m_m_axi_awvalid_converter_0_signal);
mp_m_axi_awvalid_converter_0->vector_out(m_axi_concat_awvalid_out_0);
mp_M00_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_0_signal);
- mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_0");
- mp_m_axi_split_awready = new xsc::xsc_split<4, 4>("m_axi_split_awready");
+ mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_0");
+ mp_m_axi_split_awready = new xsc::xsc_split<5, 5>("m_axi_split_awready");
mp_m_axi_split_awready->in_port(m_axi_awready);
mp_m_axi_split_awready->out_port[0](m_axi_split_awready_out_0);
mp_m_axi_split_awready->add_mask(0,1,0);
mp_m_axi_awready_converter_0->vector_in(m_axi_split_awready_out_0);
mp_m_axi_awready_converter_0->scalar_out(m_m_axi_awready_converter_0_signal);
mp_M00_AXI_transactor->AWREADY(m_m_axi_awready_converter_0_signal);
- mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_0");
- mp_m_axi_concat_wdata = new xsc::xsc_concatenator<128, 4>("m_axi_concat_wdata");
+ mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_0");
+ mp_m_axi_concat_wdata = new xsc::xsc_concatenator<160, 5>("m_axi_concat_wdata");
mp_m_axi_concat_wdata->in_port[0](m_axi_concat_wdata_out_0);
mp_m_axi_concat_wdata->out_port(m_axi_wdata);
mp_m_axi_concat_wdata->offset_port(0, 0);
mp_m_axi_wdata_converter_0->vector_in(m_m_axi_wdata_converter_0_signal);
mp_m_axi_wdata_converter_0->vector_out(m_axi_concat_wdata_out_0);
mp_M00_AXI_transactor->WDATA(m_m_axi_wdata_converter_0_signal);
- mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_0");
- mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<16, 4>("m_axi_concat_wstrb");
+ mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_0");
+ mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<20, 5>("m_axi_concat_wstrb");
mp_m_axi_concat_wstrb->in_port[0](m_axi_concat_wstrb_out_0);
mp_m_axi_concat_wstrb->out_port(m_axi_wstrb);
mp_m_axi_concat_wstrb->offset_port(0, 0);
mp_m_axi_wstrb_converter_0->vector_in(m_m_axi_wstrb_converter_0_signal);
mp_m_axi_wstrb_converter_0->vector_out(m_axi_concat_wstrb_out_0);
mp_M00_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_0_signal);
- mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_0");
- mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_wvalid");
+ mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_0");
+ mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_wvalid");
mp_m_axi_concat_wvalid->in_port[0](m_axi_concat_wvalid_out_0);
mp_m_axi_concat_wvalid->out_port(m_axi_wvalid);
mp_m_axi_concat_wvalid->offset_port(0, 0);
mp_m_axi_wvalid_converter_0->scalar_in(m_m_axi_wvalid_converter_0_signal);
mp_m_axi_wvalid_converter_0->vector_out(m_axi_concat_wvalid_out_0);
mp_M00_AXI_transactor->WVALID(m_m_axi_wvalid_converter_0_signal);
- mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_0");
- mp_m_axi_split_wready = new xsc::xsc_split<4, 4>("m_axi_split_wready");
+ mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_0");
+ mp_m_axi_split_wready = new xsc::xsc_split<5, 5>("m_axi_split_wready");
mp_m_axi_split_wready->in_port(m_axi_wready);
mp_m_axi_split_wready->out_port[0](m_axi_split_wready_out_0);
mp_m_axi_split_wready->add_mask(0,1,0);
mp_m_axi_wready_converter_0->vector_in(m_axi_split_wready_out_0);
mp_m_axi_wready_converter_0->scalar_out(m_m_axi_wready_converter_0_signal);
mp_M00_AXI_transactor->WREADY(m_m_axi_wready_converter_0_signal);
- mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_0");
- mp_m_axi_split_bresp = new xsc::xsc_split<8, 4>("m_axi_split_bresp");
+ mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_0");
+ mp_m_axi_split_bresp = new xsc::xsc_split<10, 5>("m_axi_split_bresp");
mp_m_axi_split_bresp->in_port(m_axi_bresp);
mp_m_axi_split_bresp->out_port[0](m_axi_split_bresp_out_0);
mp_m_axi_split_bresp->add_mask(0,2,0);
mp_m_axi_bresp_converter_0->vector_in(m_axi_split_bresp_out_0);
mp_m_axi_bresp_converter_0->vector_out(m_m_axi_bresp_converter_0_signal);
mp_M00_AXI_transactor->BRESP(m_m_axi_bresp_converter_0_signal);
- mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_0");
- mp_m_axi_split_bvalid = new xsc::xsc_split<4, 4>("m_axi_split_bvalid");
+ mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_0");
+ mp_m_axi_split_bvalid = new xsc::xsc_split<5, 5>("m_axi_split_bvalid");
mp_m_axi_split_bvalid->in_port(m_axi_bvalid);
mp_m_axi_split_bvalid->out_port[0](m_axi_split_bvalid_out_0);
mp_m_axi_split_bvalid->add_mask(0,1,0);
mp_m_axi_bvalid_converter_0->vector_in(m_axi_split_bvalid_out_0);
mp_m_axi_bvalid_converter_0->scalar_out(m_m_axi_bvalid_converter_0_signal);
mp_M00_AXI_transactor->BVALID(m_m_axi_bvalid_converter_0_signal);
- mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_0");
- mp_m_axi_concat_bready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_bready");
+ mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_0");
+ mp_m_axi_concat_bready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_bready");
mp_m_axi_concat_bready->in_port[0](m_axi_concat_bready_out_0);
mp_m_axi_concat_bready->out_port(m_axi_bready);
mp_m_axi_concat_bready->offset_port(0, 0);
mp_m_axi_bready_converter_0->scalar_in(m_m_axi_bready_converter_0_signal);
mp_m_axi_bready_converter_0->vector_out(m_axi_concat_bready_out_0);
mp_M00_AXI_transactor->BREADY(m_m_axi_bready_converter_0_signal);
- mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_0");
- mp_m_axi_concat_araddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_araddr");
+ mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_0");
+ mp_m_axi_concat_araddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_araddr");
mp_m_axi_concat_araddr->in_port[0](m_axi_concat_araddr_out_0);
mp_m_axi_concat_araddr->out_port(m_axi_araddr);
mp_m_axi_concat_araddr->offset_port(0, 0);
mp_m_axi_araddr_converter_0->vector_in(m_m_axi_araddr_converter_0_signal);
mp_m_axi_araddr_converter_0->vector_out(m_axi_concat_araddr_out_0);
mp_M00_AXI_transactor->ARADDR(m_m_axi_araddr_converter_0_signal);
- mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_0");
- mp_m_axi_concat_arprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_arprot");
+ mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_0");
+ mp_m_axi_concat_arprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_arprot");
mp_m_axi_concat_arprot->in_port[0](m_axi_concat_arprot_out_0);
mp_m_axi_concat_arprot->out_port(m_axi_arprot);
mp_m_axi_concat_arprot->offset_port(0, 0);
mp_m_axi_arprot_converter_0->vector_in(m_m_axi_arprot_converter_0_signal);
mp_m_axi_arprot_converter_0->vector_out(m_axi_concat_arprot_out_0);
mp_M00_AXI_transactor->ARPROT(m_m_axi_arprot_converter_0_signal);
- mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_0");
- mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_arvalid");
+ mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_0");
+ mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_arvalid");
mp_m_axi_concat_arvalid->in_port[0](m_axi_concat_arvalid_out_0);
mp_m_axi_concat_arvalid->out_port(m_axi_arvalid);
mp_m_axi_concat_arvalid->offset_port(0, 0);
mp_m_axi_arvalid_converter_0->scalar_in(m_m_axi_arvalid_converter_0_signal);
mp_m_axi_arvalid_converter_0->vector_out(m_axi_concat_arvalid_out_0);
mp_M00_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_0_signal);
- mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_0");
- mp_m_axi_split_arready = new xsc::xsc_split<4, 4>("m_axi_split_arready");
+ mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_0");
+ mp_m_axi_split_arready = new xsc::xsc_split<5, 5>("m_axi_split_arready");
mp_m_axi_split_arready->in_port(m_axi_arready);
mp_m_axi_split_arready->out_port[0](m_axi_split_arready_out_0);
mp_m_axi_split_arready->add_mask(0,1,0);
mp_m_axi_arready_converter_0->vector_in(m_axi_split_arready_out_0);
mp_m_axi_arready_converter_0->scalar_out(m_m_axi_arready_converter_0_signal);
mp_M00_AXI_transactor->ARREADY(m_m_axi_arready_converter_0_signal);
- mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_0");
- mp_m_axi_split_rdata = new xsc::xsc_split<128, 4>("m_axi_split_rdata");
+ mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_0");
+ mp_m_axi_split_rdata = new xsc::xsc_split<160, 5>("m_axi_split_rdata");
mp_m_axi_split_rdata->in_port(m_axi_rdata);
mp_m_axi_split_rdata->out_port[0](m_axi_split_rdata_out_0);
mp_m_axi_split_rdata->add_mask(0,32,0);
mp_m_axi_rdata_converter_0->vector_in(m_axi_split_rdata_out_0);
mp_m_axi_rdata_converter_0->vector_out(m_m_axi_rdata_converter_0_signal);
mp_M00_AXI_transactor->RDATA(m_m_axi_rdata_converter_0_signal);
- mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_0");
- mp_m_axi_split_rresp = new xsc::xsc_split<8, 4>("m_axi_split_rresp");
+ mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_0");
+ mp_m_axi_split_rresp = new xsc::xsc_split<10, 5>("m_axi_split_rresp");
mp_m_axi_split_rresp->in_port(m_axi_rresp);
mp_m_axi_split_rresp->out_port[0](m_axi_split_rresp_out_0);
mp_m_axi_split_rresp->add_mask(0,2,0);
mp_m_axi_rresp_converter_0->vector_in(m_axi_split_rresp_out_0);
mp_m_axi_rresp_converter_0->vector_out(m_m_axi_rresp_converter_0_signal);
mp_M00_AXI_transactor->RRESP(m_m_axi_rresp_converter_0_signal);
- mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_0");
- mp_m_axi_split_rvalid = new xsc::xsc_split<4, 4>("m_axi_split_rvalid");
+ mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_0");
+ mp_m_axi_split_rvalid = new xsc::xsc_split<5, 5>("m_axi_split_rvalid");
mp_m_axi_split_rvalid->in_port(m_axi_rvalid);
mp_m_axi_split_rvalid->out_port[0](m_axi_split_rvalid_out_0);
mp_m_axi_split_rvalid->add_mask(0,1,0);
mp_m_axi_rvalid_converter_0->vector_in(m_axi_split_rvalid_out_0);
mp_m_axi_rvalid_converter_0->scalar_out(m_m_axi_rvalid_converter_0_signal);
mp_M00_AXI_transactor->RVALID(m_m_axi_rvalid_converter_0_signal);
- mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_0");
- mp_m_axi_concat_rready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_rready");
+ mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_0");
+ mp_m_axi_concat_rready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_rready");
mp_m_axi_concat_rready->in_port[0](m_axi_concat_rready_out_0);
mp_m_axi_concat_rready->out_port(m_axi_rready);
mp_m_axi_concat_rready->offset_port(0, 0);
@@ -3457,123 +4074,123 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M01_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M01_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M01_AXI_transactor", M01_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_1");
+ mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_1");
mp_m_axi_concat_awaddr->in_port[1](m_axi_concat_awaddr_out_1);
mp_m_axi_concat_awaddr->offset_port(1, 32);
mp_m_axi_awaddr_converter_1->vector_in(m_m_axi_awaddr_converter_1_signal);
mp_m_axi_awaddr_converter_1->vector_out(m_axi_concat_awaddr_out_1);
mp_M01_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_1_signal);
- mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_1");
+ mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_1");
mp_m_axi_concat_awprot->in_port[1](m_axi_concat_awprot_out_1);
mp_m_axi_concat_awprot->offset_port(1, 3);
mp_m_axi_awprot_converter_1->vector_in(m_m_axi_awprot_converter_1_signal);
mp_m_axi_awprot_converter_1->vector_out(m_axi_concat_awprot_out_1);
mp_M01_AXI_transactor->AWPROT(m_m_axi_awprot_converter_1_signal);
- mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_1");
+ mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_1");
mp_m_axi_concat_awvalid->in_port[1](m_axi_concat_awvalid_out_1);
mp_m_axi_concat_awvalid->offset_port(1, 1);
mp_m_axi_awvalid_converter_1->scalar_in(m_m_axi_awvalid_converter_1_signal);
mp_m_axi_awvalid_converter_1->vector_out(m_axi_concat_awvalid_out_1);
mp_M01_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_1_signal);
- mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_1");
+ mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_1");
mp_m_axi_split_awready->out_port[1](m_axi_split_awready_out_1);
mp_m_axi_split_awready->add_mask(1,2,1);
mp_m_axi_awready_converter_1->vector_in(m_axi_split_awready_out_1);
mp_m_axi_awready_converter_1->scalar_out(m_m_axi_awready_converter_1_signal);
mp_M01_AXI_transactor->AWREADY(m_m_axi_awready_converter_1_signal);
- mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_1");
+ mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_1");
mp_m_axi_concat_wdata->in_port[1](m_axi_concat_wdata_out_1);
mp_m_axi_concat_wdata->offset_port(1, 32);
mp_m_axi_wdata_converter_1->vector_in(m_m_axi_wdata_converter_1_signal);
mp_m_axi_wdata_converter_1->vector_out(m_axi_concat_wdata_out_1);
mp_M01_AXI_transactor->WDATA(m_m_axi_wdata_converter_1_signal);
- mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_1");
+ mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_1");
mp_m_axi_concat_wstrb->in_port[1](m_axi_concat_wstrb_out_1);
mp_m_axi_concat_wstrb->offset_port(1, 4);
mp_m_axi_wstrb_converter_1->vector_in(m_m_axi_wstrb_converter_1_signal);
mp_m_axi_wstrb_converter_1->vector_out(m_axi_concat_wstrb_out_1);
mp_M01_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_1_signal);
- mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_1");
+ mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_1");
mp_m_axi_concat_wvalid->in_port[1](m_axi_concat_wvalid_out_1);
mp_m_axi_concat_wvalid->offset_port(1, 1);
mp_m_axi_wvalid_converter_1->scalar_in(m_m_axi_wvalid_converter_1_signal);
mp_m_axi_wvalid_converter_1->vector_out(m_axi_concat_wvalid_out_1);
mp_M01_AXI_transactor->WVALID(m_m_axi_wvalid_converter_1_signal);
- mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_1");
+ mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_1");
mp_m_axi_split_wready->out_port[1](m_axi_split_wready_out_1);
mp_m_axi_split_wready->add_mask(1,2,1);
mp_m_axi_wready_converter_1->vector_in(m_axi_split_wready_out_1);
mp_m_axi_wready_converter_1->scalar_out(m_m_axi_wready_converter_1_signal);
mp_M01_AXI_transactor->WREADY(m_m_axi_wready_converter_1_signal);
- mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_1");
+ mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_1");
mp_m_axi_split_bresp->out_port[1](m_axi_split_bresp_out_1);
mp_m_axi_split_bresp->add_mask(1,4,2);
mp_m_axi_bresp_converter_1->vector_in(m_axi_split_bresp_out_1);
mp_m_axi_bresp_converter_1->vector_out(m_m_axi_bresp_converter_1_signal);
mp_M01_AXI_transactor->BRESP(m_m_axi_bresp_converter_1_signal);
- mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_1");
+ mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_1");
mp_m_axi_split_bvalid->out_port[1](m_axi_split_bvalid_out_1);
mp_m_axi_split_bvalid->add_mask(1,2,1);
mp_m_axi_bvalid_converter_1->vector_in(m_axi_split_bvalid_out_1);
mp_m_axi_bvalid_converter_1->scalar_out(m_m_axi_bvalid_converter_1_signal);
mp_M01_AXI_transactor->BVALID(m_m_axi_bvalid_converter_1_signal);
- mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_1");
+ mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_1");
mp_m_axi_concat_bready->in_port[1](m_axi_concat_bready_out_1);
mp_m_axi_concat_bready->offset_port(1, 1);
mp_m_axi_bready_converter_1->scalar_in(m_m_axi_bready_converter_1_signal);
mp_m_axi_bready_converter_1->vector_out(m_axi_concat_bready_out_1);
mp_M01_AXI_transactor->BREADY(m_m_axi_bready_converter_1_signal);
- mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_1");
+ mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_1");
mp_m_axi_concat_araddr->in_port[1](m_axi_concat_araddr_out_1);
mp_m_axi_concat_araddr->offset_port(1, 32);
mp_m_axi_araddr_converter_1->vector_in(m_m_axi_araddr_converter_1_signal);
mp_m_axi_araddr_converter_1->vector_out(m_axi_concat_araddr_out_1);
mp_M01_AXI_transactor->ARADDR(m_m_axi_araddr_converter_1_signal);
- mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_1");
+ mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_1");
mp_m_axi_concat_arprot->in_port[1](m_axi_concat_arprot_out_1);
mp_m_axi_concat_arprot->offset_port(1, 3);
mp_m_axi_arprot_converter_1->vector_in(m_m_axi_arprot_converter_1_signal);
mp_m_axi_arprot_converter_1->vector_out(m_axi_concat_arprot_out_1);
mp_M01_AXI_transactor->ARPROT(m_m_axi_arprot_converter_1_signal);
- mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_1");
+ mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_1");
mp_m_axi_concat_arvalid->in_port[1](m_axi_concat_arvalid_out_1);
mp_m_axi_concat_arvalid->offset_port(1, 1);
mp_m_axi_arvalid_converter_1->scalar_in(m_m_axi_arvalid_converter_1_signal);
mp_m_axi_arvalid_converter_1->vector_out(m_axi_concat_arvalid_out_1);
mp_M01_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_1_signal);
- mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_1");
+ mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_1");
mp_m_axi_split_arready->out_port[1](m_axi_split_arready_out_1);
mp_m_axi_split_arready->add_mask(1,2,1);
mp_m_axi_arready_converter_1->vector_in(m_axi_split_arready_out_1);
mp_m_axi_arready_converter_1->scalar_out(m_m_axi_arready_converter_1_signal);
mp_M01_AXI_transactor->ARREADY(m_m_axi_arready_converter_1_signal);
- mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_1");
+ mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_1");
mp_m_axi_split_rdata->out_port[1](m_axi_split_rdata_out_1);
mp_m_axi_split_rdata->add_mask(1,64,32);
mp_m_axi_rdata_converter_1->vector_in(m_axi_split_rdata_out_1);
mp_m_axi_rdata_converter_1->vector_out(m_m_axi_rdata_converter_1_signal);
mp_M01_AXI_transactor->RDATA(m_m_axi_rdata_converter_1_signal);
- mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_1");
+ mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_1");
mp_m_axi_split_rresp->out_port[1](m_axi_split_rresp_out_1);
mp_m_axi_split_rresp->add_mask(1,4,2);
mp_m_axi_rresp_converter_1->vector_in(m_axi_split_rresp_out_1);
mp_m_axi_rresp_converter_1->vector_out(m_m_axi_rresp_converter_1_signal);
mp_M01_AXI_transactor->RRESP(m_m_axi_rresp_converter_1_signal);
- mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_1");
+ mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_1");
mp_m_axi_split_rvalid->out_port[1](m_axi_split_rvalid_out_1);
mp_m_axi_split_rvalid->add_mask(1,2,1);
mp_m_axi_rvalid_converter_1->vector_in(m_axi_split_rvalid_out_1);
mp_m_axi_rvalid_converter_1->scalar_out(m_m_axi_rvalid_converter_1_signal);
mp_M01_AXI_transactor->RVALID(m_m_axi_rvalid_converter_1_signal);
- mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_1");
+ mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_1");
mp_m_axi_concat_rready->in_port[1](m_axi_concat_rready_out_1);
mp_m_axi_concat_rready->offset_port(1, 1);
mp_m_axi_rready_converter_1->scalar_in(m_m_axi_rready_converter_1_signal);
@@ -3617,123 +4234,123 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M02_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M02_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M02_AXI_transactor", M02_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_2");
+ mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_2");
mp_m_axi_concat_awaddr->in_port[2](m_axi_concat_awaddr_out_2);
mp_m_axi_concat_awaddr->offset_port(2, 64);
mp_m_axi_awaddr_converter_2->vector_in(m_m_axi_awaddr_converter_2_signal);
mp_m_axi_awaddr_converter_2->vector_out(m_axi_concat_awaddr_out_2);
mp_M02_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_2_signal);
- mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_2");
+ mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_2");
mp_m_axi_concat_awprot->in_port[2](m_axi_concat_awprot_out_2);
mp_m_axi_concat_awprot->offset_port(2, 6);
mp_m_axi_awprot_converter_2->vector_in(m_m_axi_awprot_converter_2_signal);
mp_m_axi_awprot_converter_2->vector_out(m_axi_concat_awprot_out_2);
mp_M02_AXI_transactor->AWPROT(m_m_axi_awprot_converter_2_signal);
- mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_2");
+ mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_2");
mp_m_axi_concat_awvalid->in_port[2](m_axi_concat_awvalid_out_2);
mp_m_axi_concat_awvalid->offset_port(2, 2);
mp_m_axi_awvalid_converter_2->scalar_in(m_m_axi_awvalid_converter_2_signal);
mp_m_axi_awvalid_converter_2->vector_out(m_axi_concat_awvalid_out_2);
mp_M02_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_2_signal);
- mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_2");
+ mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_2");
mp_m_axi_split_awready->out_port[2](m_axi_split_awready_out_2);
mp_m_axi_split_awready->add_mask(2,3,2);
mp_m_axi_awready_converter_2->vector_in(m_axi_split_awready_out_2);
mp_m_axi_awready_converter_2->scalar_out(m_m_axi_awready_converter_2_signal);
mp_M02_AXI_transactor->AWREADY(m_m_axi_awready_converter_2_signal);
- mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_2");
+ mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_2");
mp_m_axi_concat_wdata->in_port[2](m_axi_concat_wdata_out_2);
mp_m_axi_concat_wdata->offset_port(2, 64);
mp_m_axi_wdata_converter_2->vector_in(m_m_axi_wdata_converter_2_signal);
mp_m_axi_wdata_converter_2->vector_out(m_axi_concat_wdata_out_2);
mp_M02_AXI_transactor->WDATA(m_m_axi_wdata_converter_2_signal);
- mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_2");
+ mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_2");
mp_m_axi_concat_wstrb->in_port[2](m_axi_concat_wstrb_out_2);
mp_m_axi_concat_wstrb->offset_port(2, 8);
mp_m_axi_wstrb_converter_2->vector_in(m_m_axi_wstrb_converter_2_signal);
mp_m_axi_wstrb_converter_2->vector_out(m_axi_concat_wstrb_out_2);
mp_M02_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_2_signal);
- mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_2");
+ mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_2");
mp_m_axi_concat_wvalid->in_port[2](m_axi_concat_wvalid_out_2);
mp_m_axi_concat_wvalid->offset_port(2, 2);
mp_m_axi_wvalid_converter_2->scalar_in(m_m_axi_wvalid_converter_2_signal);
mp_m_axi_wvalid_converter_2->vector_out(m_axi_concat_wvalid_out_2);
mp_M02_AXI_transactor->WVALID(m_m_axi_wvalid_converter_2_signal);
- mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_2");
+ mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_2");
mp_m_axi_split_wready->out_port[2](m_axi_split_wready_out_2);
mp_m_axi_split_wready->add_mask(2,3,2);
mp_m_axi_wready_converter_2->vector_in(m_axi_split_wready_out_2);
mp_m_axi_wready_converter_2->scalar_out(m_m_axi_wready_converter_2_signal);
mp_M02_AXI_transactor->WREADY(m_m_axi_wready_converter_2_signal);
- mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_2");
+ mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_2");
mp_m_axi_split_bresp->out_port[2](m_axi_split_bresp_out_2);
mp_m_axi_split_bresp->add_mask(2,6,4);
mp_m_axi_bresp_converter_2->vector_in(m_axi_split_bresp_out_2);
mp_m_axi_bresp_converter_2->vector_out(m_m_axi_bresp_converter_2_signal);
mp_M02_AXI_transactor->BRESP(m_m_axi_bresp_converter_2_signal);
- mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_2");
+ mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_2");
mp_m_axi_split_bvalid->out_port[2](m_axi_split_bvalid_out_2);
mp_m_axi_split_bvalid->add_mask(2,3,2);
mp_m_axi_bvalid_converter_2->vector_in(m_axi_split_bvalid_out_2);
mp_m_axi_bvalid_converter_2->scalar_out(m_m_axi_bvalid_converter_2_signal);
mp_M02_AXI_transactor->BVALID(m_m_axi_bvalid_converter_2_signal);
- mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_2");
+ mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_2");
mp_m_axi_concat_bready->in_port[2](m_axi_concat_bready_out_2);
mp_m_axi_concat_bready->offset_port(2, 2);
mp_m_axi_bready_converter_2->scalar_in(m_m_axi_bready_converter_2_signal);
mp_m_axi_bready_converter_2->vector_out(m_axi_concat_bready_out_2);
mp_M02_AXI_transactor->BREADY(m_m_axi_bready_converter_2_signal);
- mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_2");
+ mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_2");
mp_m_axi_concat_araddr->in_port[2](m_axi_concat_araddr_out_2);
mp_m_axi_concat_araddr->offset_port(2, 64);
mp_m_axi_araddr_converter_2->vector_in(m_m_axi_araddr_converter_2_signal);
mp_m_axi_araddr_converter_2->vector_out(m_axi_concat_araddr_out_2);
mp_M02_AXI_transactor->ARADDR(m_m_axi_araddr_converter_2_signal);
- mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_2");
+ mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_2");
mp_m_axi_concat_arprot->in_port[2](m_axi_concat_arprot_out_2);
mp_m_axi_concat_arprot->offset_port(2, 6);
mp_m_axi_arprot_converter_2->vector_in(m_m_axi_arprot_converter_2_signal);
mp_m_axi_arprot_converter_2->vector_out(m_axi_concat_arprot_out_2);
mp_M02_AXI_transactor->ARPROT(m_m_axi_arprot_converter_2_signal);
- mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_2");
+ mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_2");
mp_m_axi_concat_arvalid->in_port[2](m_axi_concat_arvalid_out_2);
mp_m_axi_concat_arvalid->offset_port(2, 2);
mp_m_axi_arvalid_converter_2->scalar_in(m_m_axi_arvalid_converter_2_signal);
mp_m_axi_arvalid_converter_2->vector_out(m_axi_concat_arvalid_out_2);
mp_M02_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_2_signal);
- mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_2");
+ mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_2");
mp_m_axi_split_arready->out_port[2](m_axi_split_arready_out_2);
mp_m_axi_split_arready->add_mask(2,3,2);
mp_m_axi_arready_converter_2->vector_in(m_axi_split_arready_out_2);
mp_m_axi_arready_converter_2->scalar_out(m_m_axi_arready_converter_2_signal);
mp_M02_AXI_transactor->ARREADY(m_m_axi_arready_converter_2_signal);
- mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_2");
+ mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_2");
mp_m_axi_split_rdata->out_port[2](m_axi_split_rdata_out_2);
mp_m_axi_split_rdata->add_mask(2,96,64);
mp_m_axi_rdata_converter_2->vector_in(m_axi_split_rdata_out_2);
mp_m_axi_rdata_converter_2->vector_out(m_m_axi_rdata_converter_2_signal);
mp_M02_AXI_transactor->RDATA(m_m_axi_rdata_converter_2_signal);
- mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_2");
+ mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_2");
mp_m_axi_split_rresp->out_port[2](m_axi_split_rresp_out_2);
mp_m_axi_split_rresp->add_mask(2,6,4);
mp_m_axi_rresp_converter_2->vector_in(m_axi_split_rresp_out_2);
mp_m_axi_rresp_converter_2->vector_out(m_m_axi_rresp_converter_2_signal);
mp_M02_AXI_transactor->RRESP(m_m_axi_rresp_converter_2_signal);
- mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_2");
+ mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_2");
mp_m_axi_split_rvalid->out_port[2](m_axi_split_rvalid_out_2);
mp_m_axi_split_rvalid->add_mask(2,3,2);
mp_m_axi_rvalid_converter_2->vector_in(m_axi_split_rvalid_out_2);
mp_m_axi_rvalid_converter_2->scalar_out(m_m_axi_rvalid_converter_2_signal);
mp_M02_AXI_transactor->RVALID(m_m_axi_rvalid_converter_2_signal);
- mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_2");
+ mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_2");
mp_m_axi_concat_rready->in_port[2](m_axi_concat_rready_out_2);
mp_m_axi_concat_rready->offset_port(2, 2);
mp_m_axi_rready_converter_2->scalar_in(m_m_axi_rready_converter_2_signal);
@@ -3762,8 +4379,8 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M03_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
M03_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
M03_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
- M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
- M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+ M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
M03_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
M03_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
M03_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
@@ -3777,123 +4394,123 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M03_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M03_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M03_AXI_transactor", M03_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_3");
+ mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_3");
mp_m_axi_concat_awaddr->in_port[3](m_axi_concat_awaddr_out_3);
mp_m_axi_concat_awaddr->offset_port(3, 96);
mp_m_axi_awaddr_converter_3->vector_in(m_m_axi_awaddr_converter_3_signal);
mp_m_axi_awaddr_converter_3->vector_out(m_axi_concat_awaddr_out_3);
mp_M03_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_3_signal);
- mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_3");
+ mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_3");
mp_m_axi_concat_awprot->in_port[3](m_axi_concat_awprot_out_3);
mp_m_axi_concat_awprot->offset_port(3, 9);
mp_m_axi_awprot_converter_3->vector_in(m_m_axi_awprot_converter_3_signal);
mp_m_axi_awprot_converter_3->vector_out(m_axi_concat_awprot_out_3);
mp_M03_AXI_transactor->AWPROT(m_m_axi_awprot_converter_3_signal);
- mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_3");
+ mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_3");
mp_m_axi_concat_awvalid->in_port[3](m_axi_concat_awvalid_out_3);
mp_m_axi_concat_awvalid->offset_port(3, 3);
mp_m_axi_awvalid_converter_3->scalar_in(m_m_axi_awvalid_converter_3_signal);
mp_m_axi_awvalid_converter_3->vector_out(m_axi_concat_awvalid_out_3);
mp_M03_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_3_signal);
- mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_3");
+ mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_3");
mp_m_axi_split_awready->out_port[3](m_axi_split_awready_out_3);
mp_m_axi_split_awready->add_mask(3,4,3);
mp_m_axi_awready_converter_3->vector_in(m_axi_split_awready_out_3);
mp_m_axi_awready_converter_3->scalar_out(m_m_axi_awready_converter_3_signal);
mp_M03_AXI_transactor->AWREADY(m_m_axi_awready_converter_3_signal);
- mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_3");
+ mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_3");
mp_m_axi_concat_wdata->in_port[3](m_axi_concat_wdata_out_3);
mp_m_axi_concat_wdata->offset_port(3, 96);
mp_m_axi_wdata_converter_3->vector_in(m_m_axi_wdata_converter_3_signal);
mp_m_axi_wdata_converter_3->vector_out(m_axi_concat_wdata_out_3);
mp_M03_AXI_transactor->WDATA(m_m_axi_wdata_converter_3_signal);
- mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_3");
+ mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_3");
mp_m_axi_concat_wstrb->in_port[3](m_axi_concat_wstrb_out_3);
mp_m_axi_concat_wstrb->offset_port(3, 12);
mp_m_axi_wstrb_converter_3->vector_in(m_m_axi_wstrb_converter_3_signal);
mp_m_axi_wstrb_converter_3->vector_out(m_axi_concat_wstrb_out_3);
mp_M03_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_3_signal);
- mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_3");
+ mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_3");
mp_m_axi_concat_wvalid->in_port[3](m_axi_concat_wvalid_out_3);
mp_m_axi_concat_wvalid->offset_port(3, 3);
mp_m_axi_wvalid_converter_3->scalar_in(m_m_axi_wvalid_converter_3_signal);
mp_m_axi_wvalid_converter_3->vector_out(m_axi_concat_wvalid_out_3);
mp_M03_AXI_transactor->WVALID(m_m_axi_wvalid_converter_3_signal);
- mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_3");
+ mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_3");
mp_m_axi_split_wready->out_port[3](m_axi_split_wready_out_3);
mp_m_axi_split_wready->add_mask(3,4,3);
mp_m_axi_wready_converter_3->vector_in(m_axi_split_wready_out_3);
mp_m_axi_wready_converter_3->scalar_out(m_m_axi_wready_converter_3_signal);
mp_M03_AXI_transactor->WREADY(m_m_axi_wready_converter_3_signal);
- mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_3");
+ mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_3");
mp_m_axi_split_bresp->out_port[3](m_axi_split_bresp_out_3);
mp_m_axi_split_bresp->add_mask(3,8,6);
mp_m_axi_bresp_converter_3->vector_in(m_axi_split_bresp_out_3);
mp_m_axi_bresp_converter_3->vector_out(m_m_axi_bresp_converter_3_signal);
mp_M03_AXI_transactor->BRESP(m_m_axi_bresp_converter_3_signal);
- mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_3");
+ mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_3");
mp_m_axi_split_bvalid->out_port[3](m_axi_split_bvalid_out_3);
mp_m_axi_split_bvalid->add_mask(3,4,3);
mp_m_axi_bvalid_converter_3->vector_in(m_axi_split_bvalid_out_3);
mp_m_axi_bvalid_converter_3->scalar_out(m_m_axi_bvalid_converter_3_signal);
mp_M03_AXI_transactor->BVALID(m_m_axi_bvalid_converter_3_signal);
- mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_3");
+ mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_3");
mp_m_axi_concat_bready->in_port[3](m_axi_concat_bready_out_3);
mp_m_axi_concat_bready->offset_port(3, 3);
mp_m_axi_bready_converter_3->scalar_in(m_m_axi_bready_converter_3_signal);
mp_m_axi_bready_converter_3->vector_out(m_axi_concat_bready_out_3);
mp_M03_AXI_transactor->BREADY(m_m_axi_bready_converter_3_signal);
- mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_3");
+ mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_3");
mp_m_axi_concat_araddr->in_port[3](m_axi_concat_araddr_out_3);
mp_m_axi_concat_araddr->offset_port(3, 96);
mp_m_axi_araddr_converter_3->vector_in(m_m_axi_araddr_converter_3_signal);
mp_m_axi_araddr_converter_3->vector_out(m_axi_concat_araddr_out_3);
mp_M03_AXI_transactor->ARADDR(m_m_axi_araddr_converter_3_signal);
- mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_3");
+ mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_3");
mp_m_axi_concat_arprot->in_port[3](m_axi_concat_arprot_out_3);
mp_m_axi_concat_arprot->offset_port(3, 9);
mp_m_axi_arprot_converter_3->vector_in(m_m_axi_arprot_converter_3_signal);
mp_m_axi_arprot_converter_3->vector_out(m_axi_concat_arprot_out_3);
mp_M03_AXI_transactor->ARPROT(m_m_axi_arprot_converter_3_signal);
- mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_3");
+ mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_3");
mp_m_axi_concat_arvalid->in_port[3](m_axi_concat_arvalid_out_3);
mp_m_axi_concat_arvalid->offset_port(3, 3);
mp_m_axi_arvalid_converter_3->scalar_in(m_m_axi_arvalid_converter_3_signal);
mp_m_axi_arvalid_converter_3->vector_out(m_axi_concat_arvalid_out_3);
mp_M03_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_3_signal);
- mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_3");
+ mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_3");
mp_m_axi_split_arready->out_port[3](m_axi_split_arready_out_3);
mp_m_axi_split_arready->add_mask(3,4,3);
mp_m_axi_arready_converter_3->vector_in(m_axi_split_arready_out_3);
mp_m_axi_arready_converter_3->scalar_out(m_m_axi_arready_converter_3_signal);
mp_M03_AXI_transactor->ARREADY(m_m_axi_arready_converter_3_signal);
- mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_3");
+ mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_3");
mp_m_axi_split_rdata->out_port[3](m_axi_split_rdata_out_3);
mp_m_axi_split_rdata->add_mask(3,128,96);
mp_m_axi_rdata_converter_3->vector_in(m_axi_split_rdata_out_3);
mp_m_axi_rdata_converter_3->vector_out(m_m_axi_rdata_converter_3_signal);
mp_M03_AXI_transactor->RDATA(m_m_axi_rdata_converter_3_signal);
- mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_3");
+ mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_3");
mp_m_axi_split_rresp->out_port[3](m_axi_split_rresp_out_3);
mp_m_axi_split_rresp->add_mask(3,8,6);
mp_m_axi_rresp_converter_3->vector_in(m_axi_split_rresp_out_3);
mp_m_axi_rresp_converter_3->vector_out(m_m_axi_rresp_converter_3_signal);
mp_M03_AXI_transactor->RRESP(m_m_axi_rresp_converter_3_signal);
- mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_3");
+ mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_3");
mp_m_axi_split_rvalid->out_port[3](m_axi_split_rvalid_out_3);
mp_m_axi_split_rvalid->add_mask(3,4,3);
mp_m_axi_rvalid_converter_3->vector_in(m_axi_split_rvalid_out_3);
mp_m_axi_rvalid_converter_3->scalar_out(m_m_axi_rvalid_converter_3_signal);
mp_M03_AXI_transactor->RVALID(m_m_axi_rvalid_converter_3_signal);
- mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_3");
+ mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_3");
mp_m_axi_concat_rready->in_port[3](m_axi_concat_rready_out_3);
mp_m_axi_concat_rready->offset_port(3, 3);
mp_m_axi_rready_converter_3->scalar_in(m_m_axi_rready_converter_3_signal);
@@ -3901,6 +4518,166 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_M03_AXI_transactor->RREADY(m_m_axi_rready_converter_3_signal);
mp_M03_AXI_transactor->CLK(aclk);
mp_M03_AXI_transactor->RST(aresetn);
+ // configure M04_AXI_transactor
+ xsc::common_cpp::properties M04_AXI_transactor_param_props;
+ M04_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000");
+ M04_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+ M04_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+ M04_AXI_transactor_param_props.addFloat("PHASE", "0.0");
+ M04_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+ M04_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+ M04_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
+
+ mp_M04_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M04_AXI_transactor", M04_AXI_transactor_param_props);
+ mp_m_axi_awaddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_4");
+ mp_m_axi_concat_awaddr->in_port[4](m_axi_concat_awaddr_out_4);
+ mp_m_axi_concat_awaddr->offset_port(4, 128);
+ mp_m_axi_awaddr_converter_4->vector_in(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awaddr_converter_4->vector_out(m_axi_concat_awaddr_out_4);
+ mp_M04_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_4");
+ mp_m_axi_concat_awprot->in_port[4](m_axi_concat_awprot_out_4);
+ mp_m_axi_concat_awprot->offset_port(4, 12);
+ mp_m_axi_awprot_converter_4->vector_in(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awprot_converter_4->vector_out(m_axi_concat_awprot_out_4);
+ mp_M04_AXI_transactor->AWPROT(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_4");
+ mp_m_axi_concat_awvalid->in_port[4](m_axi_concat_awvalid_out_4);
+ mp_m_axi_concat_awvalid->offset_port(4, 4);
+ mp_m_axi_awvalid_converter_4->scalar_in(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awvalid_converter_4->vector_out(m_axi_concat_awvalid_out_4);
+ mp_M04_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_4");
+
+ mp_m_axi_split_awready->out_port[4](m_axi_split_awready_out_4);
+ mp_m_axi_split_awready->add_mask(4,5,4);
+ mp_m_axi_awready_converter_4->vector_in(m_axi_split_awready_out_4);
+ mp_m_axi_awready_converter_4->scalar_out(m_m_axi_awready_converter_4_signal);
+ mp_M04_AXI_transactor->AWREADY(m_m_axi_awready_converter_4_signal);
+ mp_m_axi_wdata_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_4");
+ mp_m_axi_concat_wdata->in_port[4](m_axi_concat_wdata_out_4);
+ mp_m_axi_concat_wdata->offset_port(4, 128);
+ mp_m_axi_wdata_converter_4->vector_in(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wdata_converter_4->vector_out(m_axi_concat_wdata_out_4);
+ mp_M04_AXI_transactor->WDATA(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wstrb_converter_4 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_4");
+ mp_m_axi_concat_wstrb->in_port[4](m_axi_concat_wstrb_out_4);
+ mp_m_axi_concat_wstrb->offset_port(4, 16);
+ mp_m_axi_wstrb_converter_4->vector_in(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wstrb_converter_4->vector_out(m_axi_concat_wstrb_out_4);
+ mp_M04_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_4");
+ mp_m_axi_concat_wvalid->in_port[4](m_axi_concat_wvalid_out_4);
+ mp_m_axi_concat_wvalid->offset_port(4, 4);
+ mp_m_axi_wvalid_converter_4->scalar_in(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wvalid_converter_4->vector_out(m_axi_concat_wvalid_out_4);
+ mp_M04_AXI_transactor->WVALID(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_4");
+
+ mp_m_axi_split_wready->out_port[4](m_axi_split_wready_out_4);
+ mp_m_axi_split_wready->add_mask(4,5,4);
+ mp_m_axi_wready_converter_4->vector_in(m_axi_split_wready_out_4);
+ mp_m_axi_wready_converter_4->scalar_out(m_m_axi_wready_converter_4_signal);
+ mp_M04_AXI_transactor->WREADY(m_m_axi_wready_converter_4_signal);
+ mp_m_axi_bresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_4");
+
+ mp_m_axi_split_bresp->out_port[4](m_axi_split_bresp_out_4);
+ mp_m_axi_split_bresp->add_mask(4,10,8);
+ mp_m_axi_bresp_converter_4->vector_in(m_axi_split_bresp_out_4);
+ mp_m_axi_bresp_converter_4->vector_out(m_m_axi_bresp_converter_4_signal);
+ mp_M04_AXI_transactor->BRESP(m_m_axi_bresp_converter_4_signal);
+ mp_m_axi_bvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_4");
+
+ mp_m_axi_split_bvalid->out_port[4](m_axi_split_bvalid_out_4);
+ mp_m_axi_split_bvalid->add_mask(4,5,4);
+ mp_m_axi_bvalid_converter_4->vector_in(m_axi_split_bvalid_out_4);
+ mp_m_axi_bvalid_converter_4->scalar_out(m_m_axi_bvalid_converter_4_signal);
+ mp_M04_AXI_transactor->BVALID(m_m_axi_bvalid_converter_4_signal);
+ mp_m_axi_bready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_4");
+ mp_m_axi_concat_bready->in_port[4](m_axi_concat_bready_out_4);
+ mp_m_axi_concat_bready->offset_port(4, 4);
+ mp_m_axi_bready_converter_4->scalar_in(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_bready_converter_4->vector_out(m_axi_concat_bready_out_4);
+ mp_M04_AXI_transactor->BREADY(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_araddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_4");
+ mp_m_axi_concat_araddr->in_port[4](m_axi_concat_araddr_out_4);
+ mp_m_axi_concat_araddr->offset_port(4, 128);
+ mp_m_axi_araddr_converter_4->vector_in(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_araddr_converter_4->vector_out(m_axi_concat_araddr_out_4);
+ mp_M04_AXI_transactor->ARADDR(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_arprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_4");
+ mp_m_axi_concat_arprot->in_port[4](m_axi_concat_arprot_out_4);
+ mp_m_axi_concat_arprot->offset_port(4, 12);
+ mp_m_axi_arprot_converter_4->vector_in(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arprot_converter_4->vector_out(m_axi_concat_arprot_out_4);
+ mp_M04_AXI_transactor->ARPROT(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_4");
+ mp_m_axi_concat_arvalid->in_port[4](m_axi_concat_arvalid_out_4);
+ mp_m_axi_concat_arvalid->offset_port(4, 4);
+ mp_m_axi_arvalid_converter_4->scalar_in(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arvalid_converter_4->vector_out(m_axi_concat_arvalid_out_4);
+ mp_M04_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_4");
+
+ mp_m_axi_split_arready->out_port[4](m_axi_split_arready_out_4);
+ mp_m_axi_split_arready->add_mask(4,5,4);
+ mp_m_axi_arready_converter_4->vector_in(m_axi_split_arready_out_4);
+ mp_m_axi_arready_converter_4->scalar_out(m_m_axi_arready_converter_4_signal);
+ mp_M04_AXI_transactor->ARREADY(m_m_axi_arready_converter_4_signal);
+ mp_m_axi_rdata_converter_4 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_4");
+
+ mp_m_axi_split_rdata->out_port[4](m_axi_split_rdata_out_4);
+ mp_m_axi_split_rdata->add_mask(4,160,128);
+ mp_m_axi_rdata_converter_4->vector_in(m_axi_split_rdata_out_4);
+ mp_m_axi_rdata_converter_4->vector_out(m_m_axi_rdata_converter_4_signal);
+ mp_M04_AXI_transactor->RDATA(m_m_axi_rdata_converter_4_signal);
+ mp_m_axi_rresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_4");
+
+ mp_m_axi_split_rresp->out_port[4](m_axi_split_rresp_out_4);
+ mp_m_axi_split_rresp->add_mask(4,10,8);
+ mp_m_axi_rresp_converter_4->vector_in(m_axi_split_rresp_out_4);
+ mp_m_axi_rresp_converter_4->vector_out(m_m_axi_rresp_converter_4_signal);
+ mp_M04_AXI_transactor->RRESP(m_m_axi_rresp_converter_4_signal);
+ mp_m_axi_rvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_4");
+
+ mp_m_axi_split_rvalid->out_port[4](m_axi_split_rvalid_out_4);
+ mp_m_axi_split_rvalid->add_mask(4,5,4);
+ mp_m_axi_rvalid_converter_4->vector_in(m_axi_split_rvalid_out_4);
+ mp_m_axi_rvalid_converter_4->scalar_out(m_m_axi_rvalid_converter_4_signal);
+ mp_M04_AXI_transactor->RVALID(m_m_axi_rvalid_converter_4_signal);
+ mp_m_axi_rready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_4");
+ mp_m_axi_concat_rready->in_port[4](m_axi_concat_rready_out_4);
+ mp_m_axi_concat_rready->offset_port(4, 4);
+ mp_m_axi_rready_converter_4->scalar_in(m_m_axi_rready_converter_4_signal);
+ mp_m_axi_rready_converter_4->vector_out(m_axi_concat_rready_out_4);
+ mp_M04_AXI_transactor->RREADY(m_m_axi_rready_converter_4_signal);
+ mp_M04_AXI_transactor->CLK(aclk);
+ mp_M04_AXI_transactor->RST(aresetn);
// initialize transactors stubs
S00_AXI_transactor_target_wr_socket_stub = nullptr;
@@ -3913,6 +4690,8 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M02_AXI_transactor_initiator_rd_socket_stub = nullptr;
M03_AXI_transactor_initiator_wr_socket_stub = nullptr;
M03_AXI_transactor_initiator_rd_socket_stub = nullptr;
+ M04_AXI_transactor_initiator_wr_socket_stub = nullptr;
+ M04_AXI_transactor_initiator_rd_socket_stub = nullptr;
}
@@ -3998,6 +4777,22 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
mp_M03_AXI_transactor->disable_transactor();
}
+ // configure 'M04_AXI' transactor
+ if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("mb_design_1_xbar_0", "M04_AXI_TLM_MODE") != 1)
+ {
+ mp_impl->initiator_4_rd_socket->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_impl->initiator_4_wr_socket->bind(*(mp_M04_AXI_transactor->wr_socket));
+
+ }
+ else
+ {
+ M04_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+ M04_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M04_AXI_transactor->wr_socket));
+ M04_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+ M04_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_M04_AXI_transactor->disable_transactor();
+ }
+
}
#endif // VCSSYSTEMC
@@ -4104,6 +4899,26 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_m_axi_rresp_converter_3 = NULL;
mp_m_axi_rvalid_converter_3 = NULL;
mp_m_axi_rready_converter_3 = NULL;
+ mp_M04_AXI_transactor = NULL;
+ mp_m_axi_awaddr_converter_4 = NULL;
+ mp_m_axi_awprot_converter_4 = NULL;
+ mp_m_axi_awvalid_converter_4 = NULL;
+ mp_m_axi_awready_converter_4 = NULL;
+ mp_m_axi_wdata_converter_4 = NULL;
+ mp_m_axi_wstrb_converter_4 = NULL;
+ mp_m_axi_wvalid_converter_4 = NULL;
+ mp_m_axi_wready_converter_4 = NULL;
+ mp_m_axi_bresp_converter_4 = NULL;
+ mp_m_axi_bvalid_converter_4 = NULL;
+ mp_m_axi_bready_converter_4 = NULL;
+ mp_m_axi_araddr_converter_4 = NULL;
+ mp_m_axi_arprot_converter_4 = NULL;
+ mp_m_axi_arvalid_converter_4 = NULL;
+ mp_m_axi_arready_converter_4 = NULL;
+ mp_m_axi_rdata_converter_4 = NULL;
+ mp_m_axi_rresp_converter_4 = NULL;
+ mp_m_axi_rvalid_converter_4 = NULL;
+ mp_m_axi_rready_converter_4 = NULL;
// initialize port junctures
mp_m_axi_concat_araddr = NULL;
@@ -4251,152 +5066,152 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M00_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M00_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M00_AXI_transactor", M00_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_0");
- mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_awaddr");
+ mp_m_axi_awaddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_0");
+ mp_m_axi_concat_awaddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_awaddr");
mp_m_axi_concat_awaddr->in_port[0](m_axi_concat_awaddr_out_0);
mp_m_axi_concat_awaddr->out_port(m_axi_awaddr);
mp_m_axi_concat_awaddr->offset_port(0, 0);
mp_m_axi_awaddr_converter_0->vector_in(m_m_axi_awaddr_converter_0_signal);
mp_m_axi_awaddr_converter_0->vector_out(m_axi_concat_awaddr_out_0);
mp_M00_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_0_signal);
- mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_0");
- mp_m_axi_concat_awprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_awprot");
+ mp_m_axi_awprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_0");
+ mp_m_axi_concat_awprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_awprot");
mp_m_axi_concat_awprot->in_port[0](m_axi_concat_awprot_out_0);
mp_m_axi_concat_awprot->out_port(m_axi_awprot);
mp_m_axi_concat_awprot->offset_port(0, 0);
mp_m_axi_awprot_converter_0->vector_in(m_m_axi_awprot_converter_0_signal);
mp_m_axi_awprot_converter_0->vector_out(m_axi_concat_awprot_out_0);
mp_M00_AXI_transactor->AWPROT(m_m_axi_awprot_converter_0_signal);
- mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_0");
- mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_awvalid");
+ mp_m_axi_awvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_0");
+ mp_m_axi_concat_awvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_awvalid");
mp_m_axi_concat_awvalid->in_port[0](m_axi_concat_awvalid_out_0);
mp_m_axi_concat_awvalid->out_port(m_axi_awvalid);
mp_m_axi_concat_awvalid->offset_port(0, 0);
mp_m_axi_awvalid_converter_0->scalar_in(m_m_axi_awvalid_converter_0_signal);
mp_m_axi_awvalid_converter_0->vector_out(m_axi_concat_awvalid_out_0);
mp_M00_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_0_signal);
- mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_0");
- mp_m_axi_split_awready = new xsc::xsc_split<4, 4>("m_axi_split_awready");
+ mp_m_axi_awready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_0");
+ mp_m_axi_split_awready = new xsc::xsc_split<5, 5>("m_axi_split_awready");
mp_m_axi_split_awready->in_port(m_axi_awready);
mp_m_axi_split_awready->out_port[0](m_axi_split_awready_out_0);
mp_m_axi_split_awready->add_mask(0,1,0);
mp_m_axi_awready_converter_0->vector_in(m_axi_split_awready_out_0);
mp_m_axi_awready_converter_0->scalar_out(m_m_axi_awready_converter_0_signal);
mp_M00_AXI_transactor->AWREADY(m_m_axi_awready_converter_0_signal);
- mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_0");
- mp_m_axi_concat_wdata = new xsc::xsc_concatenator<128, 4>("m_axi_concat_wdata");
+ mp_m_axi_wdata_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_0");
+ mp_m_axi_concat_wdata = new xsc::xsc_concatenator<160, 5>("m_axi_concat_wdata");
mp_m_axi_concat_wdata->in_port[0](m_axi_concat_wdata_out_0);
mp_m_axi_concat_wdata->out_port(m_axi_wdata);
mp_m_axi_concat_wdata->offset_port(0, 0);
mp_m_axi_wdata_converter_0->vector_in(m_m_axi_wdata_converter_0_signal);
mp_m_axi_wdata_converter_0->vector_out(m_axi_concat_wdata_out_0);
mp_M00_AXI_transactor->WDATA(m_m_axi_wdata_converter_0_signal);
- mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_0");
- mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<16, 4>("m_axi_concat_wstrb");
+ mp_m_axi_wstrb_converter_0 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_0");
+ mp_m_axi_concat_wstrb = new xsc::xsc_concatenator<20, 5>("m_axi_concat_wstrb");
mp_m_axi_concat_wstrb->in_port[0](m_axi_concat_wstrb_out_0);
mp_m_axi_concat_wstrb->out_port(m_axi_wstrb);
mp_m_axi_concat_wstrb->offset_port(0, 0);
mp_m_axi_wstrb_converter_0->vector_in(m_m_axi_wstrb_converter_0_signal);
mp_m_axi_wstrb_converter_0->vector_out(m_axi_concat_wstrb_out_0);
mp_M00_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_0_signal);
- mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_0");
- mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_wvalid");
+ mp_m_axi_wvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_0");
+ mp_m_axi_concat_wvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_wvalid");
mp_m_axi_concat_wvalid->in_port[0](m_axi_concat_wvalid_out_0);
mp_m_axi_concat_wvalid->out_port(m_axi_wvalid);
mp_m_axi_concat_wvalid->offset_port(0, 0);
mp_m_axi_wvalid_converter_0->scalar_in(m_m_axi_wvalid_converter_0_signal);
mp_m_axi_wvalid_converter_0->vector_out(m_axi_concat_wvalid_out_0);
mp_M00_AXI_transactor->WVALID(m_m_axi_wvalid_converter_0_signal);
- mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_0");
- mp_m_axi_split_wready = new xsc::xsc_split<4, 4>("m_axi_split_wready");
+ mp_m_axi_wready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_0");
+ mp_m_axi_split_wready = new xsc::xsc_split<5, 5>("m_axi_split_wready");
mp_m_axi_split_wready->in_port(m_axi_wready);
mp_m_axi_split_wready->out_port[0](m_axi_split_wready_out_0);
mp_m_axi_split_wready->add_mask(0,1,0);
mp_m_axi_wready_converter_0->vector_in(m_axi_split_wready_out_0);
mp_m_axi_wready_converter_0->scalar_out(m_m_axi_wready_converter_0_signal);
mp_M00_AXI_transactor->WREADY(m_m_axi_wready_converter_0_signal);
- mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_0");
- mp_m_axi_split_bresp = new xsc::xsc_split<8, 4>("m_axi_split_bresp");
+ mp_m_axi_bresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_0");
+ mp_m_axi_split_bresp = new xsc::xsc_split<10, 5>("m_axi_split_bresp");
mp_m_axi_split_bresp->in_port(m_axi_bresp);
mp_m_axi_split_bresp->out_port[0](m_axi_split_bresp_out_0);
mp_m_axi_split_bresp->add_mask(0,2,0);
mp_m_axi_bresp_converter_0->vector_in(m_axi_split_bresp_out_0);
mp_m_axi_bresp_converter_0->vector_out(m_m_axi_bresp_converter_0_signal);
mp_M00_AXI_transactor->BRESP(m_m_axi_bresp_converter_0_signal);
- mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_0");
- mp_m_axi_split_bvalid = new xsc::xsc_split<4, 4>("m_axi_split_bvalid");
+ mp_m_axi_bvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_0");
+ mp_m_axi_split_bvalid = new xsc::xsc_split<5, 5>("m_axi_split_bvalid");
mp_m_axi_split_bvalid->in_port(m_axi_bvalid);
mp_m_axi_split_bvalid->out_port[0](m_axi_split_bvalid_out_0);
mp_m_axi_split_bvalid->add_mask(0,1,0);
mp_m_axi_bvalid_converter_0->vector_in(m_axi_split_bvalid_out_0);
mp_m_axi_bvalid_converter_0->scalar_out(m_m_axi_bvalid_converter_0_signal);
mp_M00_AXI_transactor->BVALID(m_m_axi_bvalid_converter_0_signal);
- mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_0");
- mp_m_axi_concat_bready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_bready");
+ mp_m_axi_bready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_0");
+ mp_m_axi_concat_bready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_bready");
mp_m_axi_concat_bready->in_port[0](m_axi_concat_bready_out_0);
mp_m_axi_concat_bready->out_port(m_axi_bready);
mp_m_axi_concat_bready->offset_port(0, 0);
mp_m_axi_bready_converter_0->scalar_in(m_m_axi_bready_converter_0_signal);
mp_m_axi_bready_converter_0->vector_out(m_axi_concat_bready_out_0);
mp_M00_AXI_transactor->BREADY(m_m_axi_bready_converter_0_signal);
- mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_0");
- mp_m_axi_concat_araddr = new xsc::xsc_concatenator<128, 4>("m_axi_concat_araddr");
+ mp_m_axi_araddr_converter_0 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_0");
+ mp_m_axi_concat_araddr = new xsc::xsc_concatenator<160, 5>("m_axi_concat_araddr");
mp_m_axi_concat_araddr->in_port[0](m_axi_concat_araddr_out_0);
mp_m_axi_concat_araddr->out_port(m_axi_araddr);
mp_m_axi_concat_araddr->offset_port(0, 0);
mp_m_axi_araddr_converter_0->vector_in(m_m_axi_araddr_converter_0_signal);
mp_m_axi_araddr_converter_0->vector_out(m_axi_concat_araddr_out_0);
mp_M00_AXI_transactor->ARADDR(m_m_axi_araddr_converter_0_signal);
- mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_0");
- mp_m_axi_concat_arprot = new xsc::xsc_concatenator<12, 4>("m_axi_concat_arprot");
+ mp_m_axi_arprot_converter_0 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_0");
+ mp_m_axi_concat_arprot = new xsc::xsc_concatenator<15, 5>("m_axi_concat_arprot");
mp_m_axi_concat_arprot->in_port[0](m_axi_concat_arprot_out_0);
mp_m_axi_concat_arprot->out_port(m_axi_arprot);
mp_m_axi_concat_arprot->offset_port(0, 0);
mp_m_axi_arprot_converter_0->vector_in(m_m_axi_arprot_converter_0_signal);
mp_m_axi_arprot_converter_0->vector_out(m_axi_concat_arprot_out_0);
mp_M00_AXI_transactor->ARPROT(m_m_axi_arprot_converter_0_signal);
- mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_0");
- mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<4, 4>("m_axi_concat_arvalid");
+ mp_m_axi_arvalid_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_0");
+ mp_m_axi_concat_arvalid = new xsc::xsc_concatenator<5, 5>("m_axi_concat_arvalid");
mp_m_axi_concat_arvalid->in_port[0](m_axi_concat_arvalid_out_0);
mp_m_axi_concat_arvalid->out_port(m_axi_arvalid);
mp_m_axi_concat_arvalid->offset_port(0, 0);
mp_m_axi_arvalid_converter_0->scalar_in(m_m_axi_arvalid_converter_0_signal);
mp_m_axi_arvalid_converter_0->vector_out(m_axi_concat_arvalid_out_0);
mp_M00_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_0_signal);
- mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_0");
- mp_m_axi_split_arready = new xsc::xsc_split<4, 4>("m_axi_split_arready");
+ mp_m_axi_arready_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_0");
+ mp_m_axi_split_arready = new xsc::xsc_split<5, 5>("m_axi_split_arready");
mp_m_axi_split_arready->in_port(m_axi_arready);
mp_m_axi_split_arready->out_port[0](m_axi_split_arready_out_0);
mp_m_axi_split_arready->add_mask(0,1,0);
mp_m_axi_arready_converter_0->vector_in(m_axi_split_arready_out_0);
mp_m_axi_arready_converter_0->scalar_out(m_m_axi_arready_converter_0_signal);
mp_M00_AXI_transactor->ARREADY(m_m_axi_arready_converter_0_signal);
- mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_0");
- mp_m_axi_split_rdata = new xsc::xsc_split<128, 4>("m_axi_split_rdata");
+ mp_m_axi_rdata_converter_0 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_0");
+ mp_m_axi_split_rdata = new xsc::xsc_split<160, 5>("m_axi_split_rdata");
mp_m_axi_split_rdata->in_port(m_axi_rdata);
mp_m_axi_split_rdata->out_port[0](m_axi_split_rdata_out_0);
mp_m_axi_split_rdata->add_mask(0,32,0);
mp_m_axi_rdata_converter_0->vector_in(m_axi_split_rdata_out_0);
mp_m_axi_rdata_converter_0->vector_out(m_m_axi_rdata_converter_0_signal);
mp_M00_AXI_transactor->RDATA(m_m_axi_rdata_converter_0_signal);
- mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_0");
- mp_m_axi_split_rresp = new xsc::xsc_split<8, 4>("m_axi_split_rresp");
+ mp_m_axi_rresp_converter_0 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_0");
+ mp_m_axi_split_rresp = new xsc::xsc_split<10, 5>("m_axi_split_rresp");
mp_m_axi_split_rresp->in_port(m_axi_rresp);
mp_m_axi_split_rresp->out_port[0](m_axi_split_rresp_out_0);
mp_m_axi_split_rresp->add_mask(0,2,0);
mp_m_axi_rresp_converter_0->vector_in(m_axi_split_rresp_out_0);
mp_m_axi_rresp_converter_0->vector_out(m_m_axi_rresp_converter_0_signal);
mp_M00_AXI_transactor->RRESP(m_m_axi_rresp_converter_0_signal);
- mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_0");
- mp_m_axi_split_rvalid = new xsc::xsc_split<4, 4>("m_axi_split_rvalid");
+ mp_m_axi_rvalid_converter_0 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_0");
+ mp_m_axi_split_rvalid = new xsc::xsc_split<5, 5>("m_axi_split_rvalid");
mp_m_axi_split_rvalid->in_port(m_axi_rvalid);
mp_m_axi_split_rvalid->out_port[0](m_axi_split_rvalid_out_0);
mp_m_axi_split_rvalid->add_mask(0,1,0);
mp_m_axi_rvalid_converter_0->vector_in(m_axi_split_rvalid_out_0);
mp_m_axi_rvalid_converter_0->scalar_out(m_m_axi_rvalid_converter_0_signal);
mp_M00_AXI_transactor->RVALID(m_m_axi_rvalid_converter_0_signal);
- mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_0");
- mp_m_axi_concat_rready = new xsc::xsc_concatenator<4, 4>("m_axi_concat_rready");
+ mp_m_axi_rready_converter_0 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_0");
+ mp_m_axi_concat_rready = new xsc::xsc_concatenator<5, 5>("m_axi_concat_rready");
mp_m_axi_concat_rready->in_port[0](m_axi_concat_rready_out_0);
mp_m_axi_concat_rready->out_port(m_axi_rready);
mp_m_axi_concat_rready->offset_port(0, 0);
@@ -4441,123 +5256,123 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M01_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M01_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M01_AXI_transactor", M01_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_1");
+ mp_m_axi_awaddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_1");
mp_m_axi_concat_awaddr->in_port[1](m_axi_concat_awaddr_out_1);
mp_m_axi_concat_awaddr->offset_port(1, 32);
mp_m_axi_awaddr_converter_1->vector_in(m_m_axi_awaddr_converter_1_signal);
mp_m_axi_awaddr_converter_1->vector_out(m_axi_concat_awaddr_out_1);
mp_M01_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_1_signal);
- mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_1");
+ mp_m_axi_awprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_1");
mp_m_axi_concat_awprot->in_port[1](m_axi_concat_awprot_out_1);
mp_m_axi_concat_awprot->offset_port(1, 3);
mp_m_axi_awprot_converter_1->vector_in(m_m_axi_awprot_converter_1_signal);
mp_m_axi_awprot_converter_1->vector_out(m_axi_concat_awprot_out_1);
mp_M01_AXI_transactor->AWPROT(m_m_axi_awprot_converter_1_signal);
- mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_1");
+ mp_m_axi_awvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_1");
mp_m_axi_concat_awvalid->in_port[1](m_axi_concat_awvalid_out_1);
mp_m_axi_concat_awvalid->offset_port(1, 1);
mp_m_axi_awvalid_converter_1->scalar_in(m_m_axi_awvalid_converter_1_signal);
mp_m_axi_awvalid_converter_1->vector_out(m_axi_concat_awvalid_out_1);
mp_M01_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_1_signal);
- mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_1");
+ mp_m_axi_awready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_1");
mp_m_axi_split_awready->out_port[1](m_axi_split_awready_out_1);
mp_m_axi_split_awready->add_mask(1,2,1);
mp_m_axi_awready_converter_1->vector_in(m_axi_split_awready_out_1);
mp_m_axi_awready_converter_1->scalar_out(m_m_axi_awready_converter_1_signal);
mp_M01_AXI_transactor->AWREADY(m_m_axi_awready_converter_1_signal);
- mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_1");
+ mp_m_axi_wdata_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_1");
mp_m_axi_concat_wdata->in_port[1](m_axi_concat_wdata_out_1);
mp_m_axi_concat_wdata->offset_port(1, 32);
mp_m_axi_wdata_converter_1->vector_in(m_m_axi_wdata_converter_1_signal);
mp_m_axi_wdata_converter_1->vector_out(m_axi_concat_wdata_out_1);
mp_M01_AXI_transactor->WDATA(m_m_axi_wdata_converter_1_signal);
- mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_1");
+ mp_m_axi_wstrb_converter_1 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_1");
mp_m_axi_concat_wstrb->in_port[1](m_axi_concat_wstrb_out_1);
mp_m_axi_concat_wstrb->offset_port(1, 4);
mp_m_axi_wstrb_converter_1->vector_in(m_m_axi_wstrb_converter_1_signal);
mp_m_axi_wstrb_converter_1->vector_out(m_axi_concat_wstrb_out_1);
mp_M01_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_1_signal);
- mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_1");
+ mp_m_axi_wvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_1");
mp_m_axi_concat_wvalid->in_port[1](m_axi_concat_wvalid_out_1);
mp_m_axi_concat_wvalid->offset_port(1, 1);
mp_m_axi_wvalid_converter_1->scalar_in(m_m_axi_wvalid_converter_1_signal);
mp_m_axi_wvalid_converter_1->vector_out(m_axi_concat_wvalid_out_1);
mp_M01_AXI_transactor->WVALID(m_m_axi_wvalid_converter_1_signal);
- mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_1");
+ mp_m_axi_wready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_1");
mp_m_axi_split_wready->out_port[1](m_axi_split_wready_out_1);
mp_m_axi_split_wready->add_mask(1,2,1);
mp_m_axi_wready_converter_1->vector_in(m_axi_split_wready_out_1);
mp_m_axi_wready_converter_1->scalar_out(m_m_axi_wready_converter_1_signal);
mp_M01_AXI_transactor->WREADY(m_m_axi_wready_converter_1_signal);
- mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_1");
+ mp_m_axi_bresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_1");
mp_m_axi_split_bresp->out_port[1](m_axi_split_bresp_out_1);
mp_m_axi_split_bresp->add_mask(1,4,2);
mp_m_axi_bresp_converter_1->vector_in(m_axi_split_bresp_out_1);
mp_m_axi_bresp_converter_1->vector_out(m_m_axi_bresp_converter_1_signal);
mp_M01_AXI_transactor->BRESP(m_m_axi_bresp_converter_1_signal);
- mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_1");
+ mp_m_axi_bvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_1");
mp_m_axi_split_bvalid->out_port[1](m_axi_split_bvalid_out_1);
mp_m_axi_split_bvalid->add_mask(1,2,1);
mp_m_axi_bvalid_converter_1->vector_in(m_axi_split_bvalid_out_1);
mp_m_axi_bvalid_converter_1->scalar_out(m_m_axi_bvalid_converter_1_signal);
mp_M01_AXI_transactor->BVALID(m_m_axi_bvalid_converter_1_signal);
- mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_1");
+ mp_m_axi_bready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_1");
mp_m_axi_concat_bready->in_port[1](m_axi_concat_bready_out_1);
mp_m_axi_concat_bready->offset_port(1, 1);
mp_m_axi_bready_converter_1->scalar_in(m_m_axi_bready_converter_1_signal);
mp_m_axi_bready_converter_1->vector_out(m_axi_concat_bready_out_1);
mp_M01_AXI_transactor->BREADY(m_m_axi_bready_converter_1_signal);
- mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_1");
+ mp_m_axi_araddr_converter_1 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_1");
mp_m_axi_concat_araddr->in_port[1](m_axi_concat_araddr_out_1);
mp_m_axi_concat_araddr->offset_port(1, 32);
mp_m_axi_araddr_converter_1->vector_in(m_m_axi_araddr_converter_1_signal);
mp_m_axi_araddr_converter_1->vector_out(m_axi_concat_araddr_out_1);
mp_M01_AXI_transactor->ARADDR(m_m_axi_araddr_converter_1_signal);
- mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_1");
+ mp_m_axi_arprot_converter_1 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_1");
mp_m_axi_concat_arprot->in_port[1](m_axi_concat_arprot_out_1);
mp_m_axi_concat_arprot->offset_port(1, 3);
mp_m_axi_arprot_converter_1->vector_in(m_m_axi_arprot_converter_1_signal);
mp_m_axi_arprot_converter_1->vector_out(m_axi_concat_arprot_out_1);
mp_M01_AXI_transactor->ARPROT(m_m_axi_arprot_converter_1_signal);
- mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_1");
+ mp_m_axi_arvalid_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_1");
mp_m_axi_concat_arvalid->in_port[1](m_axi_concat_arvalid_out_1);
mp_m_axi_concat_arvalid->offset_port(1, 1);
mp_m_axi_arvalid_converter_1->scalar_in(m_m_axi_arvalid_converter_1_signal);
mp_m_axi_arvalid_converter_1->vector_out(m_axi_concat_arvalid_out_1);
mp_M01_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_1_signal);
- mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_1");
+ mp_m_axi_arready_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_1");
mp_m_axi_split_arready->out_port[1](m_axi_split_arready_out_1);
mp_m_axi_split_arready->add_mask(1,2,1);
mp_m_axi_arready_converter_1->vector_in(m_axi_split_arready_out_1);
mp_m_axi_arready_converter_1->scalar_out(m_m_axi_arready_converter_1_signal);
mp_M01_AXI_transactor->ARREADY(m_m_axi_arready_converter_1_signal);
- mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_1");
+ mp_m_axi_rdata_converter_1 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_1");
mp_m_axi_split_rdata->out_port[1](m_axi_split_rdata_out_1);
mp_m_axi_split_rdata->add_mask(1,64,32);
mp_m_axi_rdata_converter_1->vector_in(m_axi_split_rdata_out_1);
mp_m_axi_rdata_converter_1->vector_out(m_m_axi_rdata_converter_1_signal);
mp_M01_AXI_transactor->RDATA(m_m_axi_rdata_converter_1_signal);
- mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_1");
+ mp_m_axi_rresp_converter_1 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_1");
mp_m_axi_split_rresp->out_port[1](m_axi_split_rresp_out_1);
mp_m_axi_split_rresp->add_mask(1,4,2);
mp_m_axi_rresp_converter_1->vector_in(m_axi_split_rresp_out_1);
mp_m_axi_rresp_converter_1->vector_out(m_m_axi_rresp_converter_1_signal);
mp_M01_AXI_transactor->RRESP(m_m_axi_rresp_converter_1_signal);
- mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_1");
+ mp_m_axi_rvalid_converter_1 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_1");
mp_m_axi_split_rvalid->out_port[1](m_axi_split_rvalid_out_1);
mp_m_axi_split_rvalid->add_mask(1,2,1);
mp_m_axi_rvalid_converter_1->vector_in(m_axi_split_rvalid_out_1);
mp_m_axi_rvalid_converter_1->scalar_out(m_m_axi_rvalid_converter_1_signal);
mp_M01_AXI_transactor->RVALID(m_m_axi_rvalid_converter_1_signal);
- mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_1");
+ mp_m_axi_rready_converter_1 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_1");
mp_m_axi_concat_rready->in_port[1](m_axi_concat_rready_out_1);
mp_m_axi_concat_rready->offset_port(1, 1);
mp_m_axi_rready_converter_1->scalar_in(m_m_axi_rready_converter_1_signal);
@@ -4601,123 +5416,123 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M02_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M02_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M02_AXI_transactor", M02_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_2");
+ mp_m_axi_awaddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_2");
mp_m_axi_concat_awaddr->in_port[2](m_axi_concat_awaddr_out_2);
mp_m_axi_concat_awaddr->offset_port(2, 64);
mp_m_axi_awaddr_converter_2->vector_in(m_m_axi_awaddr_converter_2_signal);
mp_m_axi_awaddr_converter_2->vector_out(m_axi_concat_awaddr_out_2);
mp_M02_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_2_signal);
- mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_2");
+ mp_m_axi_awprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_2");
mp_m_axi_concat_awprot->in_port[2](m_axi_concat_awprot_out_2);
mp_m_axi_concat_awprot->offset_port(2, 6);
mp_m_axi_awprot_converter_2->vector_in(m_m_axi_awprot_converter_2_signal);
mp_m_axi_awprot_converter_2->vector_out(m_axi_concat_awprot_out_2);
mp_M02_AXI_transactor->AWPROT(m_m_axi_awprot_converter_2_signal);
- mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_2");
+ mp_m_axi_awvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_2");
mp_m_axi_concat_awvalid->in_port[2](m_axi_concat_awvalid_out_2);
mp_m_axi_concat_awvalid->offset_port(2, 2);
mp_m_axi_awvalid_converter_2->scalar_in(m_m_axi_awvalid_converter_2_signal);
mp_m_axi_awvalid_converter_2->vector_out(m_axi_concat_awvalid_out_2);
mp_M02_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_2_signal);
- mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_2");
+ mp_m_axi_awready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_2");
mp_m_axi_split_awready->out_port[2](m_axi_split_awready_out_2);
mp_m_axi_split_awready->add_mask(2,3,2);
mp_m_axi_awready_converter_2->vector_in(m_axi_split_awready_out_2);
mp_m_axi_awready_converter_2->scalar_out(m_m_axi_awready_converter_2_signal);
mp_M02_AXI_transactor->AWREADY(m_m_axi_awready_converter_2_signal);
- mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_2");
+ mp_m_axi_wdata_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_2");
mp_m_axi_concat_wdata->in_port[2](m_axi_concat_wdata_out_2);
mp_m_axi_concat_wdata->offset_port(2, 64);
mp_m_axi_wdata_converter_2->vector_in(m_m_axi_wdata_converter_2_signal);
mp_m_axi_wdata_converter_2->vector_out(m_axi_concat_wdata_out_2);
mp_M02_AXI_transactor->WDATA(m_m_axi_wdata_converter_2_signal);
- mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_2");
+ mp_m_axi_wstrb_converter_2 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_2");
mp_m_axi_concat_wstrb->in_port[2](m_axi_concat_wstrb_out_2);
mp_m_axi_concat_wstrb->offset_port(2, 8);
mp_m_axi_wstrb_converter_2->vector_in(m_m_axi_wstrb_converter_2_signal);
mp_m_axi_wstrb_converter_2->vector_out(m_axi_concat_wstrb_out_2);
mp_M02_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_2_signal);
- mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_2");
+ mp_m_axi_wvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_2");
mp_m_axi_concat_wvalid->in_port[2](m_axi_concat_wvalid_out_2);
mp_m_axi_concat_wvalid->offset_port(2, 2);
mp_m_axi_wvalid_converter_2->scalar_in(m_m_axi_wvalid_converter_2_signal);
mp_m_axi_wvalid_converter_2->vector_out(m_axi_concat_wvalid_out_2);
mp_M02_AXI_transactor->WVALID(m_m_axi_wvalid_converter_2_signal);
- mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_2");
+ mp_m_axi_wready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_2");
mp_m_axi_split_wready->out_port[2](m_axi_split_wready_out_2);
mp_m_axi_split_wready->add_mask(2,3,2);
mp_m_axi_wready_converter_2->vector_in(m_axi_split_wready_out_2);
mp_m_axi_wready_converter_2->scalar_out(m_m_axi_wready_converter_2_signal);
mp_M02_AXI_transactor->WREADY(m_m_axi_wready_converter_2_signal);
- mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_2");
+ mp_m_axi_bresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_2");
mp_m_axi_split_bresp->out_port[2](m_axi_split_bresp_out_2);
mp_m_axi_split_bresp->add_mask(2,6,4);
mp_m_axi_bresp_converter_2->vector_in(m_axi_split_bresp_out_2);
mp_m_axi_bresp_converter_2->vector_out(m_m_axi_bresp_converter_2_signal);
mp_M02_AXI_transactor->BRESP(m_m_axi_bresp_converter_2_signal);
- mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_2");
+ mp_m_axi_bvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_2");
mp_m_axi_split_bvalid->out_port[2](m_axi_split_bvalid_out_2);
mp_m_axi_split_bvalid->add_mask(2,3,2);
mp_m_axi_bvalid_converter_2->vector_in(m_axi_split_bvalid_out_2);
mp_m_axi_bvalid_converter_2->scalar_out(m_m_axi_bvalid_converter_2_signal);
mp_M02_AXI_transactor->BVALID(m_m_axi_bvalid_converter_2_signal);
- mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_2");
+ mp_m_axi_bready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_2");
mp_m_axi_concat_bready->in_port[2](m_axi_concat_bready_out_2);
mp_m_axi_concat_bready->offset_port(2, 2);
mp_m_axi_bready_converter_2->scalar_in(m_m_axi_bready_converter_2_signal);
mp_m_axi_bready_converter_2->vector_out(m_axi_concat_bready_out_2);
mp_M02_AXI_transactor->BREADY(m_m_axi_bready_converter_2_signal);
- mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_2");
+ mp_m_axi_araddr_converter_2 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_2");
mp_m_axi_concat_araddr->in_port[2](m_axi_concat_araddr_out_2);
mp_m_axi_concat_araddr->offset_port(2, 64);
mp_m_axi_araddr_converter_2->vector_in(m_m_axi_araddr_converter_2_signal);
mp_m_axi_araddr_converter_2->vector_out(m_axi_concat_araddr_out_2);
mp_M02_AXI_transactor->ARADDR(m_m_axi_araddr_converter_2_signal);
- mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_2");
+ mp_m_axi_arprot_converter_2 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_2");
mp_m_axi_concat_arprot->in_port[2](m_axi_concat_arprot_out_2);
mp_m_axi_concat_arprot->offset_port(2, 6);
mp_m_axi_arprot_converter_2->vector_in(m_m_axi_arprot_converter_2_signal);
mp_m_axi_arprot_converter_2->vector_out(m_axi_concat_arprot_out_2);
mp_M02_AXI_transactor->ARPROT(m_m_axi_arprot_converter_2_signal);
- mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_2");
+ mp_m_axi_arvalid_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_2");
mp_m_axi_concat_arvalid->in_port[2](m_axi_concat_arvalid_out_2);
mp_m_axi_concat_arvalid->offset_port(2, 2);
mp_m_axi_arvalid_converter_2->scalar_in(m_m_axi_arvalid_converter_2_signal);
mp_m_axi_arvalid_converter_2->vector_out(m_axi_concat_arvalid_out_2);
mp_M02_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_2_signal);
- mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_2");
+ mp_m_axi_arready_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_2");
mp_m_axi_split_arready->out_port[2](m_axi_split_arready_out_2);
mp_m_axi_split_arready->add_mask(2,3,2);
mp_m_axi_arready_converter_2->vector_in(m_axi_split_arready_out_2);
mp_m_axi_arready_converter_2->scalar_out(m_m_axi_arready_converter_2_signal);
mp_M02_AXI_transactor->ARREADY(m_m_axi_arready_converter_2_signal);
- mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_2");
+ mp_m_axi_rdata_converter_2 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_2");
mp_m_axi_split_rdata->out_port[2](m_axi_split_rdata_out_2);
mp_m_axi_split_rdata->add_mask(2,96,64);
mp_m_axi_rdata_converter_2->vector_in(m_axi_split_rdata_out_2);
mp_m_axi_rdata_converter_2->vector_out(m_m_axi_rdata_converter_2_signal);
mp_M02_AXI_transactor->RDATA(m_m_axi_rdata_converter_2_signal);
- mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_2");
+ mp_m_axi_rresp_converter_2 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_2");
mp_m_axi_split_rresp->out_port[2](m_axi_split_rresp_out_2);
mp_m_axi_split_rresp->add_mask(2,6,4);
mp_m_axi_rresp_converter_2->vector_in(m_axi_split_rresp_out_2);
mp_m_axi_rresp_converter_2->vector_out(m_m_axi_rresp_converter_2_signal);
mp_M02_AXI_transactor->RRESP(m_m_axi_rresp_converter_2_signal);
- mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_2");
+ mp_m_axi_rvalid_converter_2 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_2");
mp_m_axi_split_rvalid->out_port[2](m_axi_split_rvalid_out_2);
mp_m_axi_split_rvalid->add_mask(2,3,2);
mp_m_axi_rvalid_converter_2->vector_in(m_axi_split_rvalid_out_2);
mp_m_axi_rvalid_converter_2->scalar_out(m_m_axi_rvalid_converter_2_signal);
mp_M02_AXI_transactor->RVALID(m_m_axi_rvalid_converter_2_signal);
- mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_2");
+ mp_m_axi_rready_converter_2 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_2");
mp_m_axi_concat_rready->in_port[2](m_axi_concat_rready_out_2);
mp_m_axi_concat_rready->offset_port(2, 2);
mp_m_axi_rready_converter_2->scalar_in(m_m_axi_rready_converter_2_signal);
@@ -4746,8 +5561,8 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M03_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
M03_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
M03_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
- M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
- M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M03_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "2");
+ M03_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "2");
M03_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
M03_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
M03_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
@@ -4761,123 +5576,123 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M03_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
mp_M03_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M03_AXI_transactor", M03_AXI_transactor_param_props);
- mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_awaddr_converter_3");
+ mp_m_axi_awaddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_3");
mp_m_axi_concat_awaddr->in_port[3](m_axi_concat_awaddr_out_3);
mp_m_axi_concat_awaddr->offset_port(3, 96);
mp_m_axi_awaddr_converter_3->vector_in(m_m_axi_awaddr_converter_3_signal);
mp_m_axi_awaddr_converter_3->vector_out(m_axi_concat_awaddr_out_3);
mp_M03_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_3_signal);
- mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_awprot_converter_3");
+ mp_m_axi_awprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_3");
mp_m_axi_concat_awprot->in_port[3](m_axi_concat_awprot_out_3);
mp_m_axi_concat_awprot->offset_port(3, 9);
mp_m_axi_awprot_converter_3->vector_in(m_m_axi_awprot_converter_3_signal);
mp_m_axi_awprot_converter_3->vector_out(m_axi_concat_awprot_out_3);
mp_M03_AXI_transactor->AWPROT(m_m_axi_awprot_converter_3_signal);
- mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_awvalid_converter_3");
+ mp_m_axi_awvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_3");
mp_m_axi_concat_awvalid->in_port[3](m_axi_concat_awvalid_out_3);
mp_m_axi_concat_awvalid->offset_port(3, 3);
mp_m_axi_awvalid_converter_3->scalar_in(m_m_axi_awvalid_converter_3_signal);
mp_m_axi_awvalid_converter_3->vector_out(m_axi_concat_awvalid_out_3);
mp_M03_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_3_signal);
- mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_awready_converter_3");
+ mp_m_axi_awready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_3");
mp_m_axi_split_awready->out_port[3](m_axi_split_awready_out_3);
mp_m_axi_split_awready->add_mask(3,4,3);
mp_m_axi_awready_converter_3->vector_in(m_axi_split_awready_out_3);
mp_m_axi_awready_converter_3->scalar_out(m_m_axi_awready_converter_3_signal);
mp_M03_AXI_transactor->AWREADY(m_m_axi_awready_converter_3_signal);
- mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_wdata_converter_3");
+ mp_m_axi_wdata_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_3");
mp_m_axi_concat_wdata->in_port[3](m_axi_concat_wdata_out_3);
mp_m_axi_concat_wdata->offset_port(3, 96);
mp_m_axi_wdata_converter_3->vector_in(m_m_axi_wdata_converter_3_signal);
mp_m_axi_wdata_converter_3->vector_out(m_axi_concat_wdata_out_3);
mp_M03_AXI_transactor->WDATA(m_m_axi_wdata_converter_3_signal);
- mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,16>("m_axi_wstrb_converter_3");
+ mp_m_axi_wstrb_converter_3 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_3");
mp_m_axi_concat_wstrb->in_port[3](m_axi_concat_wstrb_out_3);
mp_m_axi_concat_wstrb->offset_port(3, 12);
mp_m_axi_wstrb_converter_3->vector_in(m_m_axi_wstrb_converter_3_signal);
mp_m_axi_wstrb_converter_3->vector_out(m_axi_concat_wstrb_out_3);
mp_M03_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_3_signal);
- mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_wvalid_converter_3");
+ mp_m_axi_wvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_3");
mp_m_axi_concat_wvalid->in_port[3](m_axi_concat_wvalid_out_3);
mp_m_axi_concat_wvalid->offset_port(3, 3);
mp_m_axi_wvalid_converter_3->scalar_in(m_m_axi_wvalid_converter_3_signal);
mp_m_axi_wvalid_converter_3->vector_out(m_axi_concat_wvalid_out_3);
mp_M03_AXI_transactor->WVALID(m_m_axi_wvalid_converter_3_signal);
- mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_wready_converter_3");
+ mp_m_axi_wready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_3");
mp_m_axi_split_wready->out_port[3](m_axi_split_wready_out_3);
mp_m_axi_split_wready->add_mask(3,4,3);
mp_m_axi_wready_converter_3->vector_in(m_axi_split_wready_out_3);
mp_m_axi_wready_converter_3->scalar_out(m_m_axi_wready_converter_3_signal);
mp_M03_AXI_transactor->WREADY(m_m_axi_wready_converter_3_signal);
- mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_bresp_converter_3");
+ mp_m_axi_bresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_3");
mp_m_axi_split_bresp->out_port[3](m_axi_split_bresp_out_3);
mp_m_axi_split_bresp->add_mask(3,8,6);
mp_m_axi_bresp_converter_3->vector_in(m_axi_split_bresp_out_3);
mp_m_axi_bresp_converter_3->vector_out(m_m_axi_bresp_converter_3_signal);
mp_M03_AXI_transactor->BRESP(m_m_axi_bresp_converter_3_signal);
- mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_bvalid_converter_3");
+ mp_m_axi_bvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_3");
mp_m_axi_split_bvalid->out_port[3](m_axi_split_bvalid_out_3);
mp_m_axi_split_bvalid->add_mask(3,4,3);
mp_m_axi_bvalid_converter_3->vector_in(m_axi_split_bvalid_out_3);
mp_m_axi_bvalid_converter_3->scalar_out(m_m_axi_bvalid_converter_3_signal);
mp_M03_AXI_transactor->BVALID(m_m_axi_bvalid_converter_3_signal);
- mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_bready_converter_3");
+ mp_m_axi_bready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_3");
mp_m_axi_concat_bready->in_port[3](m_axi_concat_bready_out_3);
mp_m_axi_concat_bready->offset_port(3, 3);
mp_m_axi_bready_converter_3->scalar_in(m_m_axi_bready_converter_3_signal);
mp_m_axi_bready_converter_3->vector_out(m_axi_concat_bready_out_3);
mp_M03_AXI_transactor->BREADY(m_m_axi_bready_converter_3_signal);
- mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,128>("m_axi_araddr_converter_3");
+ mp_m_axi_araddr_converter_3 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_3");
mp_m_axi_concat_araddr->in_port[3](m_axi_concat_araddr_out_3);
mp_m_axi_concat_araddr->offset_port(3, 96);
mp_m_axi_araddr_converter_3->vector_in(m_m_axi_araddr_converter_3_signal);
mp_m_axi_araddr_converter_3->vector_out(m_axi_concat_araddr_out_3);
mp_M03_AXI_transactor->ARADDR(m_m_axi_araddr_converter_3_signal);
- mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,12>("m_axi_arprot_converter_3");
+ mp_m_axi_arprot_converter_3 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_3");
mp_m_axi_concat_arprot->in_port[3](m_axi_concat_arprot_out_3);
mp_m_axi_concat_arprot->offset_port(3, 9);
mp_m_axi_arprot_converter_3->vector_in(m_m_axi_arprot_converter_3_signal);
mp_m_axi_arprot_converter_3->vector_out(m_axi_concat_arprot_out_3);
mp_M03_AXI_transactor->ARPROT(m_m_axi_arprot_converter_3_signal);
- mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_arvalid_converter_3");
+ mp_m_axi_arvalid_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_3");
mp_m_axi_concat_arvalid->in_port[3](m_axi_concat_arvalid_out_3);
mp_m_axi_concat_arvalid->offset_port(3, 3);
mp_m_axi_arvalid_converter_3->scalar_in(m_m_axi_arvalid_converter_3_signal);
mp_m_axi_arvalid_converter_3->vector_out(m_axi_concat_arvalid_out_3);
mp_M03_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_3_signal);
- mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_arready_converter_3");
+ mp_m_axi_arready_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_3");
mp_m_axi_split_arready->out_port[3](m_axi_split_arready_out_3);
mp_m_axi_split_arready->add_mask(3,4,3);
mp_m_axi_arready_converter_3->vector_in(m_axi_split_arready_out_3);
mp_m_axi_arready_converter_3->scalar_out(m_m_axi_arready_converter_3_signal);
mp_M03_AXI_transactor->ARREADY(m_m_axi_arready_converter_3_signal);
- mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<128,32>("m_axi_rdata_converter_3");
+ mp_m_axi_rdata_converter_3 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_3");
mp_m_axi_split_rdata->out_port[3](m_axi_split_rdata_out_3);
mp_m_axi_split_rdata->add_mask(3,128,96);
mp_m_axi_rdata_converter_3->vector_in(m_axi_split_rdata_out_3);
mp_m_axi_rdata_converter_3->vector_out(m_m_axi_rdata_converter_3_signal);
mp_M03_AXI_transactor->RDATA(m_m_axi_rdata_converter_3_signal);
- mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<8,2>("m_axi_rresp_converter_3");
+ mp_m_axi_rresp_converter_3 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_3");
mp_m_axi_split_rresp->out_port[3](m_axi_split_rresp_out_3);
mp_m_axi_split_rresp->add_mask(3,8,6);
mp_m_axi_rresp_converter_3->vector_in(m_axi_split_rresp_out_3);
mp_m_axi_rresp_converter_3->vector_out(m_m_axi_rresp_converter_3_signal);
mp_M03_AXI_transactor->RRESP(m_m_axi_rresp_converter_3_signal);
- mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<4>("m_axi_rvalid_converter_3");
+ mp_m_axi_rvalid_converter_3 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_3");
mp_m_axi_split_rvalid->out_port[3](m_axi_split_rvalid_out_3);
mp_m_axi_split_rvalid->add_mask(3,4,3);
mp_m_axi_rvalid_converter_3->vector_in(m_axi_split_rvalid_out_3);
mp_m_axi_rvalid_converter_3->scalar_out(m_m_axi_rvalid_converter_3_signal);
mp_M03_AXI_transactor->RVALID(m_m_axi_rvalid_converter_3_signal);
- mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<4>("m_axi_rready_converter_3");
+ mp_m_axi_rready_converter_3 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_3");
mp_m_axi_concat_rready->in_port[3](m_axi_concat_rready_out_3);
mp_m_axi_concat_rready->offset_port(3, 3);
mp_m_axi_rready_converter_3->scalar_in(m_m_axi_rready_converter_3_signal);
@@ -4885,6 +5700,166 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
mp_M03_AXI_transactor->RREADY(m_m_axi_rready_converter_3_signal);
mp_M03_AXI_transactor->CLK(aclk);
mp_M03_AXI_transactor->RST(aresetn);
+ // configure M04_AXI_transactor
+ xsc::common_cpp::properties M04_AXI_transactor_param_props;
+ M04_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("FREQ_HZ", "100000000");
+ M04_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ADDR_WIDTH", "32");
+ M04_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_LOCK", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_PROT", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_CACHE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_QOS", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_REGION", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
+ M04_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
+ M04_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "1");
+ M04_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
+ M04_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_SIZE", "0");
+ M04_AXI_transactor_param_props.addLong("HAS_RESET", "1");
+ M04_AXI_transactor_param_props.addFloat("PHASE", "0.0");
+ M04_AXI_transactor_param_props.addString("PROTOCOL", "AXI4LITE");
+ M04_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
+ M04_AXI_transactor_param_props.addString("CLK_DOMAIN", "/clk_wiz_0_clk_out1");
+
+ mp_M04_AXI_transactor = new xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>("M04_AXI_transactor", M04_AXI_transactor_param_props);
+ mp_m_axi_awaddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_awaddr_converter_4");
+ mp_m_axi_concat_awaddr->in_port[4](m_axi_concat_awaddr_out_4);
+ mp_m_axi_concat_awaddr->offset_port(4, 128);
+ mp_m_axi_awaddr_converter_4->vector_in(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awaddr_converter_4->vector_out(m_axi_concat_awaddr_out_4);
+ mp_M04_AXI_transactor->AWADDR(m_m_axi_awaddr_converter_4_signal);
+ mp_m_axi_awprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_awprot_converter_4");
+ mp_m_axi_concat_awprot->in_port[4](m_axi_concat_awprot_out_4);
+ mp_m_axi_concat_awprot->offset_port(4, 12);
+ mp_m_axi_awprot_converter_4->vector_in(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awprot_converter_4->vector_out(m_axi_concat_awprot_out_4);
+ mp_M04_AXI_transactor->AWPROT(m_m_axi_awprot_converter_4_signal);
+ mp_m_axi_awvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_awvalid_converter_4");
+ mp_m_axi_concat_awvalid->in_port[4](m_axi_concat_awvalid_out_4);
+ mp_m_axi_concat_awvalid->offset_port(4, 4);
+ mp_m_axi_awvalid_converter_4->scalar_in(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awvalid_converter_4->vector_out(m_axi_concat_awvalid_out_4);
+ mp_M04_AXI_transactor->AWVALID(m_m_axi_awvalid_converter_4_signal);
+ mp_m_axi_awready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_awready_converter_4");
+
+ mp_m_axi_split_awready->out_port[4](m_axi_split_awready_out_4);
+ mp_m_axi_split_awready->add_mask(4,5,4);
+ mp_m_axi_awready_converter_4->vector_in(m_axi_split_awready_out_4);
+ mp_m_axi_awready_converter_4->scalar_out(m_m_axi_awready_converter_4_signal);
+ mp_M04_AXI_transactor->AWREADY(m_m_axi_awready_converter_4_signal);
+ mp_m_axi_wdata_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_wdata_converter_4");
+ mp_m_axi_concat_wdata->in_port[4](m_axi_concat_wdata_out_4);
+ mp_m_axi_concat_wdata->offset_port(4, 128);
+ mp_m_axi_wdata_converter_4->vector_in(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wdata_converter_4->vector_out(m_axi_concat_wdata_out_4);
+ mp_M04_AXI_transactor->WDATA(m_m_axi_wdata_converter_4_signal);
+ mp_m_axi_wstrb_converter_4 = new xsc::common::vector2vector_converter<4,20>("m_axi_wstrb_converter_4");
+ mp_m_axi_concat_wstrb->in_port[4](m_axi_concat_wstrb_out_4);
+ mp_m_axi_concat_wstrb->offset_port(4, 16);
+ mp_m_axi_wstrb_converter_4->vector_in(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wstrb_converter_4->vector_out(m_axi_concat_wstrb_out_4);
+ mp_M04_AXI_transactor->WSTRB(m_m_axi_wstrb_converter_4_signal);
+ mp_m_axi_wvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_wvalid_converter_4");
+ mp_m_axi_concat_wvalid->in_port[4](m_axi_concat_wvalid_out_4);
+ mp_m_axi_concat_wvalid->offset_port(4, 4);
+ mp_m_axi_wvalid_converter_4->scalar_in(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wvalid_converter_4->vector_out(m_axi_concat_wvalid_out_4);
+ mp_M04_AXI_transactor->WVALID(m_m_axi_wvalid_converter_4_signal);
+ mp_m_axi_wready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_wready_converter_4");
+
+ mp_m_axi_split_wready->out_port[4](m_axi_split_wready_out_4);
+ mp_m_axi_split_wready->add_mask(4,5,4);
+ mp_m_axi_wready_converter_4->vector_in(m_axi_split_wready_out_4);
+ mp_m_axi_wready_converter_4->scalar_out(m_m_axi_wready_converter_4_signal);
+ mp_M04_AXI_transactor->WREADY(m_m_axi_wready_converter_4_signal);
+ mp_m_axi_bresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_bresp_converter_4");
+
+ mp_m_axi_split_bresp->out_port[4](m_axi_split_bresp_out_4);
+ mp_m_axi_split_bresp->add_mask(4,10,8);
+ mp_m_axi_bresp_converter_4->vector_in(m_axi_split_bresp_out_4);
+ mp_m_axi_bresp_converter_4->vector_out(m_m_axi_bresp_converter_4_signal);
+ mp_M04_AXI_transactor->BRESP(m_m_axi_bresp_converter_4_signal);
+ mp_m_axi_bvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_bvalid_converter_4");
+
+ mp_m_axi_split_bvalid->out_port[4](m_axi_split_bvalid_out_4);
+ mp_m_axi_split_bvalid->add_mask(4,5,4);
+ mp_m_axi_bvalid_converter_4->vector_in(m_axi_split_bvalid_out_4);
+ mp_m_axi_bvalid_converter_4->scalar_out(m_m_axi_bvalid_converter_4_signal);
+ mp_M04_AXI_transactor->BVALID(m_m_axi_bvalid_converter_4_signal);
+ mp_m_axi_bready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_bready_converter_4");
+ mp_m_axi_concat_bready->in_port[4](m_axi_concat_bready_out_4);
+ mp_m_axi_concat_bready->offset_port(4, 4);
+ mp_m_axi_bready_converter_4->scalar_in(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_bready_converter_4->vector_out(m_axi_concat_bready_out_4);
+ mp_M04_AXI_transactor->BREADY(m_m_axi_bready_converter_4_signal);
+ mp_m_axi_araddr_converter_4 = new xsc::common::vector2vector_converter<32,160>("m_axi_araddr_converter_4");
+ mp_m_axi_concat_araddr->in_port[4](m_axi_concat_araddr_out_4);
+ mp_m_axi_concat_araddr->offset_port(4, 128);
+ mp_m_axi_araddr_converter_4->vector_in(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_araddr_converter_4->vector_out(m_axi_concat_araddr_out_4);
+ mp_M04_AXI_transactor->ARADDR(m_m_axi_araddr_converter_4_signal);
+ mp_m_axi_arprot_converter_4 = new xsc::common::vector2vector_converter<3,15>("m_axi_arprot_converter_4");
+ mp_m_axi_concat_arprot->in_port[4](m_axi_concat_arprot_out_4);
+ mp_m_axi_concat_arprot->offset_port(4, 12);
+ mp_m_axi_arprot_converter_4->vector_in(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arprot_converter_4->vector_out(m_axi_concat_arprot_out_4);
+ mp_M04_AXI_transactor->ARPROT(m_m_axi_arprot_converter_4_signal);
+ mp_m_axi_arvalid_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_arvalid_converter_4");
+ mp_m_axi_concat_arvalid->in_port[4](m_axi_concat_arvalid_out_4);
+ mp_m_axi_concat_arvalid->offset_port(4, 4);
+ mp_m_axi_arvalid_converter_4->scalar_in(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arvalid_converter_4->vector_out(m_axi_concat_arvalid_out_4);
+ mp_M04_AXI_transactor->ARVALID(m_m_axi_arvalid_converter_4_signal);
+ mp_m_axi_arready_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_arready_converter_4");
+
+ mp_m_axi_split_arready->out_port[4](m_axi_split_arready_out_4);
+ mp_m_axi_split_arready->add_mask(4,5,4);
+ mp_m_axi_arready_converter_4->vector_in(m_axi_split_arready_out_4);
+ mp_m_axi_arready_converter_4->scalar_out(m_m_axi_arready_converter_4_signal);
+ mp_M04_AXI_transactor->ARREADY(m_m_axi_arready_converter_4_signal);
+ mp_m_axi_rdata_converter_4 = new xsc::common::vector2vector_converter<160,32>("m_axi_rdata_converter_4");
+
+ mp_m_axi_split_rdata->out_port[4](m_axi_split_rdata_out_4);
+ mp_m_axi_split_rdata->add_mask(4,160,128);
+ mp_m_axi_rdata_converter_4->vector_in(m_axi_split_rdata_out_4);
+ mp_m_axi_rdata_converter_4->vector_out(m_m_axi_rdata_converter_4_signal);
+ mp_M04_AXI_transactor->RDATA(m_m_axi_rdata_converter_4_signal);
+ mp_m_axi_rresp_converter_4 = new xsc::common::vector2vector_converter<10,2>("m_axi_rresp_converter_4");
+
+ mp_m_axi_split_rresp->out_port[4](m_axi_split_rresp_out_4);
+ mp_m_axi_split_rresp->add_mask(4,10,8);
+ mp_m_axi_rresp_converter_4->vector_in(m_axi_split_rresp_out_4);
+ mp_m_axi_rresp_converter_4->vector_out(m_m_axi_rresp_converter_4_signal);
+ mp_M04_AXI_transactor->RRESP(m_m_axi_rresp_converter_4_signal);
+ mp_m_axi_rvalid_converter_4 = new xsc::common::vectorN2scalar_converter<5>("m_axi_rvalid_converter_4");
+
+ mp_m_axi_split_rvalid->out_port[4](m_axi_split_rvalid_out_4);
+ mp_m_axi_split_rvalid->add_mask(4,5,4);
+ mp_m_axi_rvalid_converter_4->vector_in(m_axi_split_rvalid_out_4);
+ mp_m_axi_rvalid_converter_4->scalar_out(m_m_axi_rvalid_converter_4_signal);
+ mp_M04_AXI_transactor->RVALID(m_m_axi_rvalid_converter_4_signal);
+ mp_m_axi_rready_converter_4 = new xsc::common::scalar2vectorN_converter<5>("m_axi_rready_converter_4");
+ mp_m_axi_concat_rready->in_port[4](m_axi_concat_rready_out_4);
+ mp_m_axi_concat_rready->offset_port(4, 4);
+ mp_m_axi_rready_converter_4->scalar_in(m_m_axi_rready_converter_4_signal);
+ mp_m_axi_rready_converter_4->vector_out(m_axi_concat_rready_out_4);
+ mp_M04_AXI_transactor->RREADY(m_m_axi_rready_converter_4_signal);
+ mp_M04_AXI_transactor->CLK(aclk);
+ mp_M04_AXI_transactor->RST(aresetn);
// initialize transactors stubs
S00_AXI_transactor_target_wr_socket_stub = nullptr;
@@ -4897,6 +5872,8 @@ mb_design_1_xbar_0::mb_design_1_xbar_0(const sc_core::sc_module_name& nm) : mb_d
M02_AXI_transactor_initiator_rd_socket_stub = nullptr;
M03_AXI_transactor_initiator_wr_socket_stub = nullptr;
M03_AXI_transactor_initiator_rd_socket_stub = nullptr;
+ M04_AXI_transactor_initiator_wr_socket_stub = nullptr;
+ M04_AXI_transactor_initiator_rd_socket_stub = nullptr;
}
@@ -4982,6 +5959,22 @@ void mb_design_1_xbar_0::before_end_of_elaboration()
mp_M03_AXI_transactor->disable_transactor();
}
+ // configure 'M04_AXI' transactor
+ if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("mb_design_1_xbar_0", "M04_AXI_TLM_MODE") != 1)
+ {
+ mp_impl->initiator_4_rd_socket->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_impl->initiator_4_wr_socket->bind(*(mp_M04_AXI_transactor->wr_socket));
+
+ }
+ else
+ {
+ M04_AXI_transactor_initiator_wr_socket_stub = new xtlm::xtlm_aximm_initiator_stub("wr_socket",0);
+ M04_AXI_transactor_initiator_wr_socket_stub->bind(*(mp_M04_AXI_transactor->wr_socket));
+ M04_AXI_transactor_initiator_rd_socket_stub = new xtlm::xtlm_aximm_initiator_stub("rd_socket",0);
+ M04_AXI_transactor_initiator_rd_socket_stub->bind(*(mp_M04_AXI_transactor->rd_socket));
+ mp_M04_AXI_transactor->disable_transactor();
+ }
+
}
#endif // MTI_SYSTEMC
@@ -5087,6 +6080,27 @@ mb_design_1_xbar_0::~mb_design_1_xbar_0()
delete mp_m_axi_rvalid_converter_3;
delete mp_m_axi_rready_converter_3;
+ delete mp_M04_AXI_transactor;
+ delete mp_m_axi_awaddr_converter_4;
+ delete mp_m_axi_awprot_converter_4;
+ delete mp_m_axi_awvalid_converter_4;
+ delete mp_m_axi_awready_converter_4;
+ delete mp_m_axi_wdata_converter_4;
+ delete mp_m_axi_wstrb_converter_4;
+ delete mp_m_axi_wvalid_converter_4;
+ delete mp_m_axi_wready_converter_4;
+ delete mp_m_axi_bresp_converter_4;
+ delete mp_m_axi_bvalid_converter_4;
+ delete mp_m_axi_bready_converter_4;
+ delete mp_m_axi_araddr_converter_4;
+ delete mp_m_axi_arprot_converter_4;
+ delete mp_m_axi_arvalid_converter_4;
+ delete mp_m_axi_arready_converter_4;
+ delete mp_m_axi_rdata_converter_4;
+ delete mp_m_axi_rresp_converter_4;
+ delete mp_m_axi_rvalid_converter_4;
+ delete mp_m_axi_rready_converter_4;
+
delete mp_m_axi_concat_araddr;
delete mp_m_axi_concat_arprot;
delete mp_m_axi_concat_arvalid;
@@ -5118,6 +6132,6 @@ XMSC_MODULE_EXPORT(mb_design_1_xbar_0);
#ifdef RIVIERA
SC_MODULE_EXPORT(mb_design_1_xbar_0);
-SC_REGISTER_BV(128);
+SC_REGISTER_BV(160);
#endif
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.h b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.h
index fc9423ae50f48f0a6c77ed8d1ce186801dcc6847..0a4e1162b10c549188397e01e25f2171835bdb12 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.h
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.h
@@ -101,25 +101,25 @@ public:
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_awaddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_awprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_awready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
- sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_wready;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_bresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_bvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_bready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_araddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_arprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_arready;
- sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_rresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_rvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_rready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_awaddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_awprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_awvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_awready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_wdata;
+ sc_core::sc_out< sc_dt::sc_bv<20> > m_axi_wstrb;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_wvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_wready;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_bresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_bvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_bready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_araddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_arprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_arvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_arready;
+ sc_core::sc_in< sc_dt::sc_bv<160> > m_axi_rdata;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_rresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_rvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_rready;
// Dummy Signals for IP Ports
@@ -152,301 +152,359 @@ private:
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
sc_signal< bool > m_s_axi_rready_converter_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_0;
sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_0;
sc_signal< bool > m_m_axi_awready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_0;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_0;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_0;
sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_0;
sc_signal< bool > m_m_axi_wready_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_0;
sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_0;
sc_signal< bool > m_m_axi_bready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_0;
sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_0;
sc_signal< bool > m_m_axi_arready_converter_0_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_0;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_0;
sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_0;
sc_signal< bool > m_m_axi_rready_converter_0_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_1;
sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_1;
sc_signal< bool > m_m_axi_awready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_1;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_1;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_1;
sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_1;
sc_signal< bool > m_m_axi_wready_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_1;
sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_1;
sc_signal< bool > m_m_axi_bready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_1;
sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_1;
sc_signal< bool > m_m_axi_arready_converter_1_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_1;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_1;
sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_1;
sc_signal< bool > m_m_axi_rready_converter_1_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_2;
sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_2;
sc_signal< bool > m_m_axi_awready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_2;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_2;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_2;
sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_2;
sc_signal< bool > m_m_axi_wready_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_2;
sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_2;
sc_signal< bool > m_m_axi_bready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_2;
sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_2;
sc_signal< bool > m_m_axi_arready_converter_2_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_2;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_2;
sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_2;
sc_signal< bool > m_m_axi_rready_converter_2_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M03_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_3;
sc_signal< bool > m_m_axi_awvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_3;
sc_signal< bool > m_m_axi_awready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_3_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_3;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_3;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_3;
sc_signal< bool > m_m_axi_wvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_3;
sc_signal< bool > m_m_axi_wready_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_3;
sc_signal< bool > m_m_axi_bvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_3;
sc_signal< bool > m_m_axi_bready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_3;
sc_signal< bool > m_m_axi_arvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_3;
sc_signal< bool > m_m_axi_arready_converter_3_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_3;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_3;
sc_signal< bool > m_m_axi_rvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_3;
sc_signal< bool > m_m_axi_rready_converter_3_signal;
+ xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M04_AXI_transactor;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_awprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_4;
+ sc_signal< bool > m_m_axi_awvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_4;
+ sc_signal< bool > m_m_axi_awready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_wdata_converter_4_signal;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_4;
+ sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_4;
+ sc_signal< bool > m_m_axi_wvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_4;
+ sc_signal< bool > m_m_axi_wready_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_bresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_4;
+ sc_signal< bool > m_m_axi_bvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_4;
+ sc_signal< bool > m_m_axi_bready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_araddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_arprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_4;
+ sc_signal< bool > m_m_axi_arvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_4;
+ sc_signal< bool > m_m_axi_arready_converter_4_signal;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_rdata_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_rresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_4;
+ sc_signal< bool > m_m_axi_rvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_4;
+ sc_signal< bool > m_m_axi_rready_converter_4_signal;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_araddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_arprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_arready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_arvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_4;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_awaddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_awprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_awready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_awvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_4;
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_araddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_bready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_bresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_4;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_bvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_4;
+ xsc::xsc_split<160, 5> * mp_m_axi_split_rdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_4;
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_arprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_3;
- xsc::xsc_split<4, 4> * mp_m_axi_split_arready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_rready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_rresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_4;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_rvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_arvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_3;
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_wdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_4;
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_awaddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_wready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_4;
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_awprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_awready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_3;
-
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_awvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_bready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_3;
-
- xsc::xsc_split<8, 4> * mp_m_axi_split_bresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_bvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_3;
-
- xsc::xsc_split<128, 4> * mp_m_axi_split_rdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_3;
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_rready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_3;
-
- xsc::xsc_split<8, 4> * mp_m_axi_split_rresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_rvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_wdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_3;
-
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_wready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_3;
-
- xsc::xsc_concatenator<16, 4> * mp_m_axi_concat_wstrb;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_0;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_1;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_2;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_wvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_3;
+ xsc::xsc_concatenator<20, 5> * mp_m_axi_concat_wstrb;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_0;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_1;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_2;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_3;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_4;
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_wvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_4;
};
#endif // XILINX_SIMULATOR
@@ -485,25 +543,25 @@ public:
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_awaddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_awprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_awready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
- sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_wready;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_bresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_bvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_bready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_araddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_arprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_arready;
- sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_rresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_rvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_rready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_awaddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_awprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_awvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_awready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_wdata;
+ sc_core::sc_out< sc_dt::sc_bv<20> > m_axi_wstrb;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_wvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_wready;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_bresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_bvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_bready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_araddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_arprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_arvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_arready;
+ sc_core::sc_in< sc_dt::sc_bv<160> > m_axi_rdata;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_rresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_rvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_rready;
// Dummy Signals for IP Ports
@@ -536,301 +594,359 @@ private:
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
sc_signal< bool > m_s_axi_rready_converter_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_0;
sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_0;
sc_signal< bool > m_m_axi_awready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_0;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_0;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_0;
sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_0;
sc_signal< bool > m_m_axi_wready_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_0;
sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_0;
sc_signal< bool > m_m_axi_bready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_0;
sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_0;
sc_signal< bool > m_m_axi_arready_converter_0_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_0;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_0;
sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_0;
sc_signal< bool > m_m_axi_rready_converter_0_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_1;
sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_1;
sc_signal< bool > m_m_axi_awready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_1;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_1;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_1;
sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_1;
sc_signal< bool > m_m_axi_wready_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_1;
sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_1;
sc_signal< bool > m_m_axi_bready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_1;
sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_1;
sc_signal< bool > m_m_axi_arready_converter_1_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_1;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_1;
sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_1;
sc_signal< bool > m_m_axi_rready_converter_1_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_2;
sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_2;
sc_signal< bool > m_m_axi_awready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_2;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_2;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_2;
sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_2;
sc_signal< bool > m_m_axi_wready_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_2;
sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_2;
sc_signal< bool > m_m_axi_bready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_2;
sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_2;
sc_signal< bool > m_m_axi_arready_converter_2_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_2;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_2;
sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_2;
sc_signal< bool > m_m_axi_rready_converter_2_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M03_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_3;
sc_signal< bool > m_m_axi_awvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_3;
sc_signal< bool > m_m_axi_awready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_3_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_3;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_3;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_3;
sc_signal< bool > m_m_axi_wvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_3;
sc_signal< bool > m_m_axi_wready_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_3;
sc_signal< bool > m_m_axi_bvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_3;
sc_signal< bool > m_m_axi_bready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_3;
sc_signal< bool > m_m_axi_arvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_3;
sc_signal< bool > m_m_axi_arready_converter_3_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_3;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_3;
sc_signal< bool > m_m_axi_rvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_3;
sc_signal< bool > m_m_axi_rready_converter_3_signal;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_araddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_3;
-
-
-
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_arprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_3;
+ xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M04_AXI_transactor;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_awprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_4;
+ sc_signal< bool > m_m_axi_awvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_4;
+ sc_signal< bool > m_m_axi_awready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_wdata_converter_4_signal;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_4;
+ sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_4;
+ sc_signal< bool > m_m_axi_wvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_4;
+ sc_signal< bool > m_m_axi_wready_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_bresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_4;
+ sc_signal< bool > m_m_axi_bvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_4;
+ sc_signal< bool > m_m_axi_bready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_araddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_arprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_4;
+ sc_signal< bool > m_m_axi_arvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_4;
+ sc_signal< bool > m_m_axi_arready_converter_4_signal;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_rdata_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_rresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_4;
+ sc_signal< bool > m_m_axi_rvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_4;
+ sc_signal< bool > m_m_axi_rready_converter_4_signal;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_araddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_arprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_arready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_arvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_4;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_awaddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_awprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_awready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_awvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_arready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_bready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_bresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_4;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_bvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_arvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_3;
+ xsc::xsc_split<160, 5> * mp_m_axi_split_rdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_4;
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_awaddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_rready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_rresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_4;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_rvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_4;
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_awprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_3;
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_wdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_awready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_wready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_4;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_awvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_bready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_3;
-
- xsc::xsc_split<8, 4> * mp_m_axi_split_bresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_bvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_3;
-
- xsc::xsc_split<128, 4> * mp_m_axi_split_rdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_3;
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_rready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_3;
-
- xsc::xsc_split<8, 4> * mp_m_axi_split_rresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_rvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_wdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_3;
-
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_wready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_3;
-
- xsc::xsc_concatenator<16, 4> * mp_m_axi_concat_wstrb;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_0;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_1;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_2;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_wvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_3;
+ xsc::xsc_concatenator<20, 5> * mp_m_axi_concat_wstrb;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_0;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_1;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_2;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_3;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_4;
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_wvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_4;
};
#endif // XM_SYSTEMC
@@ -869,25 +985,25 @@ public:
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_awaddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_awprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_awready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
- sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_wready;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_bresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_bvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_bready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_araddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_arprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_arready;
- sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_rresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_rvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_rready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_awaddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_awprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_awvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_awready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_wdata;
+ sc_core::sc_out< sc_dt::sc_bv<20> > m_axi_wstrb;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_wvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_wready;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_bresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_bvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_bready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_araddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_arprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_arvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_arready;
+ sc_core::sc_in< sc_dt::sc_bv<160> > m_axi_rdata;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_rresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_rvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_rready;
// Dummy Signals for IP Ports
@@ -920,301 +1036,359 @@ private:
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
sc_signal< bool > m_s_axi_rready_converter_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_0;
sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_0;
sc_signal< bool > m_m_axi_awready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_0;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_0;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_0;
sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_0;
sc_signal< bool > m_m_axi_wready_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_0;
sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_0;
sc_signal< bool > m_m_axi_bready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_0;
sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_0;
sc_signal< bool > m_m_axi_arready_converter_0_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_0;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_0;
sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_0;
sc_signal< bool > m_m_axi_rready_converter_0_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_1;
sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_1;
sc_signal< bool > m_m_axi_awready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_1;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_1;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_1;
sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_1;
sc_signal< bool > m_m_axi_wready_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_1;
sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_1;
sc_signal< bool > m_m_axi_bready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_1;
sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_1;
sc_signal< bool > m_m_axi_arready_converter_1_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_1;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_1;
sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_1;
sc_signal< bool > m_m_axi_rready_converter_1_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_2;
sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_2;
sc_signal< bool > m_m_axi_awready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_2;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_2;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_2;
sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_2;
sc_signal< bool > m_m_axi_wready_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_2;
sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_2;
sc_signal< bool > m_m_axi_bready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_2;
sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_2;
sc_signal< bool > m_m_axi_arready_converter_2_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_2;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_2;
sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_2;
sc_signal< bool > m_m_axi_rready_converter_2_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M03_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_3;
sc_signal< bool > m_m_axi_awvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_3;
sc_signal< bool > m_m_axi_awready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_3_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_3;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_3;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_3;
sc_signal< bool > m_m_axi_wvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_3;
sc_signal< bool > m_m_axi_wready_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_3;
sc_signal< bool > m_m_axi_bvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_3;
sc_signal< bool > m_m_axi_bready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_3;
sc_signal< bool > m_m_axi_arvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_3;
sc_signal< bool > m_m_axi_arready_converter_3_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_3;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_3;
sc_signal< bool > m_m_axi_rvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_3;
sc_signal< bool > m_m_axi_rready_converter_3_signal;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_araddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_3;
-
-
-
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_arprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_arready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_3;
-
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_arvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_awaddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_3;
+ xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M04_AXI_transactor;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_awprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_4;
+ sc_signal< bool > m_m_axi_awvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_4;
+ sc_signal< bool > m_m_axi_awready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_wdata_converter_4_signal;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_4;
+ sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_4;
+ sc_signal< bool > m_m_axi_wvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_4;
+ sc_signal< bool > m_m_axi_wready_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_bresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_4;
+ sc_signal< bool > m_m_axi_bvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_4;
+ sc_signal< bool > m_m_axi_bready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_araddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_arprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_4;
+ sc_signal< bool > m_m_axi_arvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_4;
+ sc_signal< bool > m_m_axi_arready_converter_4_signal;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_rdata_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_rresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_4;
+ sc_signal< bool > m_m_axi_rvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_4;
+ sc_signal< bool > m_m_axi_rready_converter_4_signal;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_araddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_arprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_arready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_arvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_4;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_awaddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_awprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_awready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_awvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_4;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_bready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_bresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_4;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_bvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_4;
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_awprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_3;
+ xsc::xsc_split<160, 5> * mp_m_axi_split_rdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_awready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_rready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_rresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_awvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_rvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_4;
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_wdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_bready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_3;
- xsc::xsc_split<8, 4> * mp_m_axi_split_bresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_wready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_bvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_3;
-
- xsc::xsc_split<128, 4> * mp_m_axi_split_rdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_3;
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_rready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_3;
-
- xsc::xsc_split<8, 4> * mp_m_axi_split_rresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_rvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_wdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_3;
-
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_wready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_3;
-
- xsc::xsc_concatenator<16, 4> * mp_m_axi_concat_wstrb;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_0;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_1;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_2;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_wvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_3;
+ xsc::xsc_concatenator<20, 5> * mp_m_axi_concat_wstrb;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_0;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_1;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_2;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_3;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_4;
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_wvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_4;
};
#endif // RIVIERA
@@ -1257,25 +1431,25 @@ public:
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_awaddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_awprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_awready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
- sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_wready;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_bresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_bvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_bready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_araddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_arprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_arready;
- sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_rresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_rvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_rready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_awaddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_awprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_awvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_awready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_wdata;
+ sc_core::sc_out< sc_dt::sc_bv<20> > m_axi_wstrb;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_wvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_wready;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_bresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_bvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_bready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_araddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_arprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_arvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_arready;
+ sc_core::sc_in< sc_dt::sc_bv<160> > m_axi_rdata;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_rresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_rvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_rready;
// Dummy Signals for IP Ports
@@ -1308,301 +1482,359 @@ private:
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
sc_signal< bool > m_s_axi_rready_converter_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_0;
sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_0;
sc_signal< bool > m_m_axi_awready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_0;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_0;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_0;
sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_0;
sc_signal< bool > m_m_axi_wready_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_0;
sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_0;
sc_signal< bool > m_m_axi_bready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_0;
sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_0;
sc_signal< bool > m_m_axi_arready_converter_0_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_0;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_0;
sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_0;
sc_signal< bool > m_m_axi_rready_converter_0_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_1;
sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_1;
sc_signal< bool > m_m_axi_awready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_1;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_1;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_1;
sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_1;
sc_signal< bool > m_m_axi_wready_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_1;
sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_1;
sc_signal< bool > m_m_axi_bready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_1;
sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_1;
sc_signal< bool > m_m_axi_arready_converter_1_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_1;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_1;
sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_1;
sc_signal< bool > m_m_axi_rready_converter_1_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_2;
sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_2;
sc_signal< bool > m_m_axi_awready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_2;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_2;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_2;
sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_2;
sc_signal< bool > m_m_axi_wready_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_2;
sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_2;
sc_signal< bool > m_m_axi_bready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_2;
sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_2;
sc_signal< bool > m_m_axi_arready_converter_2_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_2;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_2;
sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_2;
sc_signal< bool > m_m_axi_rready_converter_2_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M03_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_3;
sc_signal< bool > m_m_axi_awvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_3;
sc_signal< bool > m_m_axi_awready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_3_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_3;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_3;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_3;
sc_signal< bool > m_m_axi_wvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_3;
sc_signal< bool > m_m_axi_wready_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_3;
sc_signal< bool > m_m_axi_bvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_3;
sc_signal< bool > m_m_axi_bready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_3;
sc_signal< bool > m_m_axi_arvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_3;
sc_signal< bool > m_m_axi_arready_converter_3_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_3;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_3;
sc_signal< bool > m_m_axi_rvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_3;
sc_signal< bool > m_m_axi_rready_converter_3_signal;
+ xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M04_AXI_transactor;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_awprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_4;
+ sc_signal< bool > m_m_axi_awvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_4;
+ sc_signal< bool > m_m_axi_awready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_wdata_converter_4_signal;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_4;
+ sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_4;
+ sc_signal< bool > m_m_axi_wvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_4;
+ sc_signal< bool > m_m_axi_wready_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_bresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_4;
+ sc_signal< bool > m_m_axi_bvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_4;
+ sc_signal< bool > m_m_axi_bready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_araddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_arprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_4;
+ sc_signal< bool > m_m_axi_arvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_4;
+ sc_signal< bool > m_m_axi_arready_converter_4_signal;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_rdata_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_rresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_4;
+ sc_signal< bool > m_m_axi_rvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_4;
+ sc_signal< bool > m_m_axi_rready_converter_4_signal;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_araddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_arprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_arready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_arvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_4;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_awaddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_awprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_awready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_awvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_4;
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_araddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_3;
-
-
-
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_arprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_arready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_3;
-
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_arvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_awaddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_3;
-
-
-
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_awprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_awready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_bready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_4;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_bresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_awvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_bvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_4;
+ xsc::xsc_split<160, 5> * mp_m_axi_split_rdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_bready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_3;
- xsc::xsc_split<8, 4> * mp_m_axi_split_bresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_rready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_bvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_3;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_rresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_4;
- xsc::xsc_split<128, 4> * mp_m_axi_split_rdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_rvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_4;
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_wdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_rready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_3;
- xsc::xsc_split<8, 4> * mp_m_axi_split_rresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_wready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_rvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_wdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_3;
-
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_wready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_3;
-
- xsc::xsc_concatenator<16, 4> * mp_m_axi_concat_wstrb;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_0;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_1;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_2;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_wvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_3;
+ xsc::xsc_concatenator<20, 5> * mp_m_axi_concat_wstrb;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_0;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_1;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_2;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_3;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_4;
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_wvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_4;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M00_AXI_transactor_initiator_rd_socket_stub;
@@ -1613,6 +1845,8 @@ private:
xtlm::xtlm_aximm_initiator_stub * M02_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M03_AXI_transactor_initiator_rd_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M03_AXI_transactor_initiator_wr_socket_stub;
+ xtlm::xtlm_aximm_initiator_stub * M04_AXI_transactor_initiator_rd_socket_stub;
+ xtlm::xtlm_aximm_initiator_stub * M04_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_rd_socket_stub;
xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_wr_socket_stub;
@@ -1659,25 +1893,25 @@ public:
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
sc_core::sc_out< sc_dt::sc_bv<1> > s_axi_rvalid;
sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_rready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_awaddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_awprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_awready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_wdata;
- sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_wstrb;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_wready;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_bresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_bvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_bready;
- sc_core::sc_out< sc_dt::sc_bv<128> > m_axi_araddr;
- sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_arprot;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arvalid;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_arready;
- sc_core::sc_in< sc_dt::sc_bv<128> > m_axi_rdata;
- sc_core::sc_in< sc_dt::sc_bv<8> > m_axi_rresp;
- sc_core::sc_in< sc_dt::sc_bv<4> > m_axi_rvalid;
- sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_rready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_awaddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_awprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_awvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_awready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_wdata;
+ sc_core::sc_out< sc_dt::sc_bv<20> > m_axi_wstrb;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_wvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_wready;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_bresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_bvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_bready;
+ sc_core::sc_out< sc_dt::sc_bv<160> > m_axi_araddr;
+ sc_core::sc_out< sc_dt::sc_bv<15> > m_axi_arprot;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_arvalid;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_arready;
+ sc_core::sc_in< sc_dt::sc_bv<160> > m_axi_rdata;
+ sc_core::sc_in< sc_dt::sc_bv<10> > m_axi_rresp;
+ sc_core::sc_in< sc_dt::sc_bv<5> > m_axi_rvalid;
+ sc_core::sc_out< sc_dt::sc_bv<5> > m_axi_rready;
// Dummy Signals for IP Ports
@@ -1710,301 +1944,359 @@ private:
xsc::common::vectorN2scalar_converter<1>* mp_s_axi_rready_converter;
sc_signal< bool > m_s_axi_rready_converter_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M00_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_0;
sc_signal< bool > m_m_axi_awvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_0;
sc_signal< bool > m_m_axi_awready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_0_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_0;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_0;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_0;
sc_signal< bool > m_m_axi_wvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_0;
sc_signal< bool > m_m_axi_wready_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_0;
sc_signal< bool > m_m_axi_bvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_0;
sc_signal< bool > m_m_axi_bready_converter_0_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_0;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_0;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_0_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_0;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_0;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_0;
sc_signal< bool > m_m_axi_arvalid_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_0;
sc_signal< bool > m_m_axi_arready_converter_0_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_0;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_0;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_0_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_0;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_0;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_0_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_0;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_0;
sc_signal< bool > m_m_axi_rvalid_converter_0_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_0;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_0;
sc_signal< bool > m_m_axi_rready_converter_0_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M01_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_1;
sc_signal< bool > m_m_axi_awvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_1;
sc_signal< bool > m_m_axi_awready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_1_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_1;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_1;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_1;
sc_signal< bool > m_m_axi_wvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_1;
sc_signal< bool > m_m_axi_wready_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_1;
sc_signal< bool > m_m_axi_bvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_1;
sc_signal< bool > m_m_axi_bready_converter_1_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_1;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_1;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_1_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_1;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_1;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_1;
sc_signal< bool > m_m_axi_arvalid_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_1;
sc_signal< bool > m_m_axi_arready_converter_1_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_1;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_1;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_1_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_1;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_1;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_1_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_1;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_1;
sc_signal< bool > m_m_axi_rvalid_converter_1_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_1;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_1;
sc_signal< bool > m_m_axi_rready_converter_1_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M02_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_2;
sc_signal< bool > m_m_axi_awvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_2;
sc_signal< bool > m_m_axi_awready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_2_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_2;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_2;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_2;
sc_signal< bool > m_m_axi_wvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_2;
sc_signal< bool > m_m_axi_wready_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_2;
sc_signal< bool > m_m_axi_bvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_2;
sc_signal< bool > m_m_axi_bready_converter_2_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_2;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_2;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_2_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_2;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_2;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_2;
sc_signal< bool > m_m_axi_arvalid_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_2;
sc_signal< bool > m_m_axi_arready_converter_2_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_2;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_2;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_2_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_2;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_2;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_2_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_2;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_2;
sc_signal< bool > m_m_axi_rvalid_converter_2_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_2;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_2;
sc_signal< bool > m_m_axi_rready_converter_2_signal;
xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M03_AXI_transactor;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_awaddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_awprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_awprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_awvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_3;
sc_signal< bool > m_m_axi_awvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_awready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_3;
sc_signal< bool > m_m_axi_awready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_wdata_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_wdata_converter_3_signal;
- xsc::common::vector2vector_converter<4,16>* mp_m_axi_wstrb_converter_3;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_3;
sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_wvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_3;
sc_signal< bool > m_m_axi_wvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_wready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_3;
sc_signal< bool > m_m_axi_wready_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_bresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_bresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_bvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_3;
sc_signal< bool > m_m_axi_bvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_bready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_3;
sc_signal< bool > m_m_axi_bready_converter_3_signal;
- xsc::common::vector2vector_converter<32,128>* mp_m_axi_araddr_converter_3;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_3;
sc_signal< sc_bv<32> > m_m_axi_araddr_converter_3_signal;
- xsc::common::vector2vector_converter<3,12>* mp_m_axi_arprot_converter_3;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_3;
sc_signal< sc_bv<3> > m_m_axi_arprot_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_arvalid_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_3;
sc_signal< bool > m_m_axi_arvalid_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_arready_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_3;
sc_signal< bool > m_m_axi_arready_converter_3_signal;
- xsc::common::vector2vector_converter<128,32>* mp_m_axi_rdata_converter_3;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_3;
sc_signal< sc_bv<32> > m_m_axi_rdata_converter_3_signal;
- xsc::common::vector2vector_converter<8,2>* mp_m_axi_rresp_converter_3;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_3;
sc_signal< sc_bv<2> > m_m_axi_rresp_converter_3_signal;
- xsc::common::vectorN2scalar_converter<4>* mp_m_axi_rvalid_converter_3;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_3;
sc_signal< bool > m_m_axi_rvalid_converter_3_signal;
- xsc::common::scalar2vectorN_converter<4>* mp_m_axi_rready_converter_3;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_3;
sc_signal< bool > m_m_axi_rready_converter_3_signal;
+ xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M04_AXI_transactor;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_awaddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_awaddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_awprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_awprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_awvalid_converter_4;
+ sc_signal< bool > m_m_axi_awvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_awready_converter_4;
+ sc_signal< bool > m_m_axi_awready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_wdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_wdata_converter_4_signal;
+ xsc::common::vector2vector_converter<4,20>* mp_m_axi_wstrb_converter_4;
+ sc_signal< sc_bv<4> > m_m_axi_wstrb_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_wvalid_converter_4;
+ sc_signal< bool > m_m_axi_wvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_wready_converter_4;
+ sc_signal< bool > m_m_axi_wready_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_bresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_bresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_bvalid_converter_4;
+ sc_signal< bool > m_m_axi_bvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_bready_converter_4;
+ sc_signal< bool > m_m_axi_bready_converter_4_signal;
+ xsc::common::vector2vector_converter<32,160>* mp_m_axi_araddr_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_araddr_converter_4_signal;
+ xsc::common::vector2vector_converter<3,15>* mp_m_axi_arprot_converter_4;
+ sc_signal< sc_bv<3> > m_m_axi_arprot_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_arvalid_converter_4;
+ sc_signal< bool > m_m_axi_arvalid_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_arready_converter_4;
+ sc_signal< bool > m_m_axi_arready_converter_4_signal;
+ xsc::common::vector2vector_converter<160,32>* mp_m_axi_rdata_converter_4;
+ sc_signal< sc_bv<32> > m_m_axi_rdata_converter_4_signal;
+ xsc::common::vector2vector_converter<10,2>* mp_m_axi_rresp_converter_4;
+ sc_signal< sc_bv<2> > m_m_axi_rresp_converter_4_signal;
+ xsc::common::vectorN2scalar_converter<5>* mp_m_axi_rvalid_converter_4;
+ sc_signal< bool > m_m_axi_rvalid_converter_4_signal;
+ xsc::common::scalar2vectorN_converter<5>* mp_m_axi_rready_converter_4;
+ sc_signal< bool > m_m_axi_rready_converter_4_signal;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_araddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_araddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_arprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_arprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_arready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_arready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_arvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_arvalid_out_4;
+
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_awaddr;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_awaddr_out_4;
+
+
+
+
+
+
+ xsc::xsc_concatenator<15, 5> * mp_m_axi_concat_awprot;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_0;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_1;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_2;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_3;
+ sc_signal<sc_dt::sc_bv<15> > m_axi_concat_awprot_out_4;
+
+
+ xsc::xsc_split<5, 5> * mp_m_axi_split_awready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_awready_out_4;
+
+
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_awvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_awvalid_out_4;
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_araddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_araddr_out_3;
-
-
-
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_arprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_arprot_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_arready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_arready_out_3;
-
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_arvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_arvalid_out_3;
-
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_awaddr;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_awaddr_out_3;
-
-
-
-
-
-
- xsc::xsc_concatenator<12, 4> * mp_m_axi_concat_awprot;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_0;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_1;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_2;
- sc_signal<sc_dt::sc_bv<12> > m_axi_concat_awprot_out_3;
-
-
- xsc::xsc_split<4, 4> * mp_m_axi_split_awready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_awready_out_3;
-
-
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_awvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_awvalid_out_3;
-
-
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_bready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_bready_out_3;
-
- xsc::xsc_split<8, 4> * mp_m_axi_split_bresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_bresp_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_bready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_bready_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_bvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_bvalid_out_3;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_bresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_bresp_out_4;
- xsc::xsc_split<128, 4> * mp_m_axi_split_rdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_split_rdata_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_bvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_bvalid_out_4;
+ xsc::xsc_split<160, 5> * mp_m_axi_split_rdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_split_rdata_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_rready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_rready_out_3;
- xsc::xsc_split<8, 4> * mp_m_axi_split_rresp;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_0;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_1;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_2;
- sc_signal<sc_dt::sc_bv<8> > m_axi_split_rresp_out_3;
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_rready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_rready_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_rvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_rvalid_out_3;
+ xsc::xsc_split<10, 5> * mp_m_axi_split_rresp;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_0;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_1;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_2;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_3;
+ sc_signal<sc_dt::sc_bv<10> > m_axi_split_rresp_out_4;
- xsc::xsc_concatenator<128, 4> * mp_m_axi_concat_wdata;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_0;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_1;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_2;
- sc_signal<sc_dt::sc_bv<128> > m_axi_concat_wdata_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_rvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_rvalid_out_4;
+ xsc::xsc_concatenator<160, 5> * mp_m_axi_concat_wdata;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_0;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_1;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_2;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_3;
+ sc_signal<sc_dt::sc_bv<160> > m_axi_concat_wdata_out_4;
- xsc::xsc_split<4, 4> * mp_m_axi_split_wready;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_split_wready_out_3;
- xsc::xsc_concatenator<16, 4> * mp_m_axi_concat_wstrb;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_0;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_1;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_2;
- sc_signal<sc_dt::sc_bv<16> > m_axi_concat_wstrb_out_3;
+ xsc::xsc_split<5, 5> * mp_m_axi_split_wready;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_split_wready_out_4;
- xsc::xsc_concatenator<4, 4> * mp_m_axi_concat_wvalid;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_0;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_1;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_2;
- sc_signal<sc_dt::sc_bv<4> > m_axi_concat_wvalid_out_3;
+ xsc::xsc_concatenator<20, 5> * mp_m_axi_concat_wstrb;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_0;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_1;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_2;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_3;
+ sc_signal<sc_dt::sc_bv<20> > m_axi_concat_wstrb_out_4;
+
+
+ xsc::xsc_concatenator<5, 5> * mp_m_axi_concat_wvalid;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_0;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_1;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_2;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_3;
+ sc_signal<sc_dt::sc_bv<5> > m_axi_concat_wvalid_out_4;
// Transactor stubs
xtlm::xtlm_aximm_initiator_stub * M00_AXI_transactor_initiator_rd_socket_stub;
@@ -2015,6 +2307,8 @@ private:
xtlm::xtlm_aximm_initiator_stub * M02_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M03_AXI_transactor_initiator_rd_socket_stub;
xtlm::xtlm_aximm_initiator_stub * M03_AXI_transactor_initiator_wr_socket_stub;
+ xtlm::xtlm_aximm_initiator_stub * M04_AXI_transactor_initiator_rd_socket_stub;
+ xtlm::xtlm_aximm_initiator_stub * M04_AXI_transactor_initiator_wr_socket_stub;
xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_rd_socket_stub;
xtlm::xtlm_aximm_target_stub * S00_AXI_transactor_target_wr_socket_stub;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.v
index 768f63ee892b29c7cd9ccee6a1b86bb2c3beaadc..92429c695ab18ee1400612293316ac4e52f74d9c 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.v
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0.v
@@ -142,61 +142,62 @@ output wire [0 : 0] s_axi_rvalid;
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
-output wire [127 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
-output wire [11 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
-output wire [127 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
-output wire [15 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
-input wire [7 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
-output wire [127 : 0] m_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
-output wire [11 : 0] m_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
-input wire [127 : 0] m_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
-input wire [7 : 0] m_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_rvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128]" *)
+output wire [159 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12]" *)
+output wire [14 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128]" *)
+output wire [159 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16]" *)
+output wire [19 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8]" *)
+input wire [9 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128]" *)
+output wire [159 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12]" *)
+output wire [14 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128]" *)
+input wire [159 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8]" *)
+input wire [9 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS\
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_D\
OMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING \
2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRES\
-P 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_rready;
+P 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PRO\
+T 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_rready;
axi_crossbar_v2_1_33_axi_crossbar #(
.C_FAMILY("artix7"),
.C_NUM_SLAVE_SLOTS(1),
- .C_NUM_MASTER_SLOTS(4),
+ .C_NUM_MASTER_SLOTS(5),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
- .C_M_AXI_BASE_ADDR(256'Hffffffffffffffff000000004120000000000000400000000000000041400000),
- .C_M_AXI_ADDR_WIDTH(128'H0000000000000010000000100000000c),
+ .C_M_AXI_BASE_ADDR(320'H000000008000000000000000412000000000000041c0000000000000400000000000000041400000),
+ .C_M_AXI_ADDR_WIDTH(160'H000000070000001000000010000000100000000c),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
@@ -205,16 +206,16 @@ output wire [3 : 0] m_axi_rready;
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
- .C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
- .C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
+ .C_M_AXI_WRITE_CONNECTIVITY(160'H0000000100000001000000010000000100000001),
+ .C_M_AXI_READ_CONNECTIVITY(160'H0000000100000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
- .C_M_AXI_WRITE_ISSUING(128'H00000001000000010000000100000001),
- .C_M_AXI_READ_ISSUING(128'H00000001000000010000000100000001),
+ .C_M_AXI_WRITE_ISSUING(160'H0000000100000001000000010000000100000001),
+ .C_M_AXI_READ_ISSUING(160'H0000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
- .C_M_AXI_SECURE(128'H00000000000000000000000000000000),
+ .C_M_AXI_SECURE(160'H0000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
@@ -282,9 +283,9 @@ output wire [3 : 0] m_axi_rready;
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
- .m_axi_bid(4'H0),
+ .m_axi_bid(5'H00),
.m_axi_bresp(m_axi_bresp),
- .m_axi_buser(4'H0),
+ .m_axi_buser(5'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
@@ -300,11 +301,11 @@ output wire [3 : 0] m_axi_rready;
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
- .m_axi_rid(4'H0),
+ .m_axi_rid(5'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
- .m_axi_rlast(4'HF),
- .m_axi_ruser(4'H0),
+ .m_axi_rlast(5'H1F),
+ .m_axi_ruser(5'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.cpp b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.cpp
index 2bc07b9bc0bb63dbddc12a0ab1cfb12f20c956ab..02ed93feffe4f0d13f82069ef0eb43f5084b723f 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.cpp
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.cpp
@@ -62,7 +62,7 @@ mb_design_1_xbar_0_sc::mb_design_1_xbar_0_sc(const sc_core::sc_module_name& nm)
// initialize module
xsc::common_cpp::properties model_param_props;
model_param_props.addLong("C_NUM_SLAVE_SLOTS", "1");
- model_param_props.addLong("C_NUM_MASTER_SLOTS", "4");
+ model_param_props.addLong("C_NUM_MASTER_SLOTS", "5");
model_param_props.addLong("C_AXI_ID_WIDTH", "1");
model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
@@ -77,19 +77,19 @@ mb_design_1_xbar_0_sc::mb_design_1_xbar_0_sc(const sc_core::sc_module_name& nm)
model_param_props.addLong("C_R_REGISTER", "1");
model_param_props.addLong("C_CONNECTIVITY_MODE", "0");
model_param_props.addString("C_FAMILY", "artix7");
- model_param_props.addBitString("C_M_AXI_BASE_ADDR", "1111111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000100000100100000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000", 256);
- model_param_props.addBitString("C_M_AXI_ADDR_WIDTH", "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100", 128);
+ model_param_props.addBitString("C_M_AXI_BASE_ADDR", "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001010000000000000000000000", 320);
+ model_param_props.addBitString("C_M_AXI_ADDR_WIDTH", "0000000000000000000000000000011100000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100", 160);
model_param_props.addBitString("C_S_AXI_BASE_ID", "00000000000000000000000000000000", 32);
model_param_props.addBitString("C_S_AXI_THREAD_ID_WIDTH", "00000000000000000000000000000000", 32);
- model_param_props.addBitString("C_M_AXI_WRITE_CONNECTIVITY", "00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 128);
- model_param_props.addBitString("C_M_AXI_READ_CONNECTIVITY", "00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 128);
+ model_param_props.addBitString("C_M_AXI_WRITE_CONNECTIVITY", "0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 160);
+ model_param_props.addBitString("C_M_AXI_READ_CONNECTIVITY", "0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 160);
model_param_props.addBitString("C_S_AXI_SINGLE_THREAD", "00000000000000000000000000000001", 32);
model_param_props.addBitString("C_S_AXI_WRITE_ACCEPTANCE", "00000000000000000000000000000001", 32);
model_param_props.addBitString("C_S_AXI_READ_ACCEPTANCE", "00000000000000000000000000000001", 32);
- model_param_props.addBitString("C_M_AXI_WRITE_ISSUING", "00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 128);
- model_param_props.addBitString("C_M_AXI_READ_ISSUING", "00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 128);
+ model_param_props.addBitString("C_M_AXI_WRITE_ISSUING", "0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 160);
+ model_param_props.addBitString("C_M_AXI_READ_ISSUING", "0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001", 160);
model_param_props.addBitString("C_S_AXI_ARB_PRIORITY", "00000000000000000000000000000000", 32);
- model_param_props.addBitString("C_M_AXI_SECURE", "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 128);
+ model_param_props.addBitString("C_M_AXI_SECURE", "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 160);
model_param_props.addString("COMPONENT_NAME", "mb_design_1_xbar_0");
mp_impl = new axi_crossbar("inst", model_param_props);
@@ -105,6 +105,8 @@ mb_design_1_xbar_0_sc::mb_design_1_xbar_0_sc(const sc_core::sc_module_name& nm)
initiator_2_wr_socket = mp_impl->initiator_2_wr_socket;
initiator_3_rd_socket = mp_impl->initiator_3_rd_socket;
initiator_3_wr_socket = mp_impl->initiator_3_wr_socket;
+ initiator_4_rd_socket = mp_impl->initiator_4_rd_socket;
+ initiator_4_wr_socket = mp_impl->initiator_4_wr_socket;
}
mb_design_1_xbar_0_sc::~mb_design_1_xbar_0_sc()
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.h b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.h
index 3ff68872d7d839b0b253a9633d635ad93bb5d118..9e01a2398475b5f6aa66b162aa623e0126283f34 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.h
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_sc.h
@@ -86,6 +86,8 @@ public:
xtlm::xtlm_aximm_initiator_socket* initiator_2_wr_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_3_rd_socket;
xtlm::xtlm_aximm_initiator_socket* initiator_3_wr_socket;
+ xtlm::xtlm_aximm_initiator_socket* initiator_4_rd_socket;
+ xtlm::xtlm_aximm_initiator_socket* initiator_4_wr_socket;
// module socket-to-socket TLM interfaces
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_stub.sv b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_stub.sv
index 80ba9c90b4a7b11653a4bfee3152a6b92457ed50..d2d02df7bdf0eec1ad7a2eefa9a14ecae5794181 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_stub.sv
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/sim/mb_design_1_xbar_0_stub.sv
@@ -87,25 +87,25 @@ module mb_design_1_xbar_0 (
output bit [1 : 0] s_axi_rresp,
output bit [0 : 0] s_axi_rvalid,
input bit [0 : 0] s_axi_rready,
- output bit [127 : 0] m_axi_awaddr,
- output bit [11 : 0] m_axi_awprot,
- output bit [3 : 0] m_axi_awvalid,
- input bit [3 : 0] m_axi_awready,
- output bit [127 : 0] m_axi_wdata,
- output bit [15 : 0] m_axi_wstrb,
- output bit [3 : 0] m_axi_wvalid,
- input bit [3 : 0] m_axi_wready,
- input bit [7 : 0] m_axi_bresp,
- input bit [3 : 0] m_axi_bvalid,
- output bit [3 : 0] m_axi_bready,
- output bit [127 : 0] m_axi_araddr,
- output bit [11 : 0] m_axi_arprot,
- output bit [3 : 0] m_axi_arvalid,
- input bit [3 : 0] m_axi_arready,
- input bit [127 : 0] m_axi_rdata,
- input bit [7 : 0] m_axi_rresp,
- input bit [3 : 0] m_axi_rvalid,
- output bit [3 : 0] m_axi_rready
+ output bit [159 : 0] m_axi_awaddr,
+ output bit [14 : 0] m_axi_awprot,
+ output bit [4 : 0] m_axi_awvalid,
+ input bit [4 : 0] m_axi_awready,
+ output bit [159 : 0] m_axi_wdata,
+ output bit [19 : 0] m_axi_wstrb,
+ output bit [4 : 0] m_axi_wvalid,
+ input bit [4 : 0] m_axi_wready,
+ input bit [9 : 0] m_axi_bresp,
+ input bit [4 : 0] m_axi_bvalid,
+ output bit [4 : 0] m_axi_bready,
+ output bit [159 : 0] m_axi_araddr,
+ output bit [14 : 0] m_axi_arprot,
+ output bit [4 : 0] m_axi_arvalid,
+ input bit [4 : 0] m_axi_arready,
+ input bit [159 : 0] m_axi_rdata,
+ input bit [9 : 0] m_axi_rresp,
+ input bit [4 : 0] m_axi_rvalid,
+ output bit [4 : 0] m_axi_rready
);
endmodule
`endif
@@ -136,24 +136,24 @@ module mb_design_1_xbar_0 (aclk,aresetn,s_axi_awaddr,s_axi_awprot,s_axi_awvalid,
output wire [1 : 0] s_axi_rresp;
output wire [0 : 0] s_axi_rvalid;
input bit [0 : 0] s_axi_rready;
- output wire [127 : 0] m_axi_awaddr;
- output wire [11 : 0] m_axi_awprot;
- output wire [3 : 0] m_axi_awvalid;
- input bit [3 : 0] m_axi_awready;
- output wire [127 : 0] m_axi_wdata;
- output wire [15 : 0] m_axi_wstrb;
- output wire [3 : 0] m_axi_wvalid;
- input bit [3 : 0] m_axi_wready;
- input bit [7 : 0] m_axi_bresp;
- input bit [3 : 0] m_axi_bvalid;
- output wire [3 : 0] m_axi_bready;
- output wire [127 : 0] m_axi_araddr;
- output wire [11 : 0] m_axi_arprot;
- output wire [3 : 0] m_axi_arvalid;
- input bit [3 : 0] m_axi_arready;
- input bit [127 : 0] m_axi_rdata;
- input bit [7 : 0] m_axi_rresp;
- input bit [3 : 0] m_axi_rvalid;
- output wire [3 : 0] m_axi_rready;
+ output wire [159 : 0] m_axi_awaddr;
+ output wire [14 : 0] m_axi_awprot;
+ output wire [4 : 0] m_axi_awvalid;
+ input bit [4 : 0] m_axi_awready;
+ output wire [159 : 0] m_axi_wdata;
+ output wire [19 : 0] m_axi_wstrb;
+ output wire [4 : 0] m_axi_wvalid;
+ input bit [4 : 0] m_axi_wready;
+ input bit [9 : 0] m_axi_bresp;
+ input bit [4 : 0] m_axi_bvalid;
+ output wire [4 : 0] m_axi_bready;
+ output wire [159 : 0] m_axi_araddr;
+ output wire [14 : 0] m_axi_arprot;
+ output wire [4 : 0] m_axi_arvalid;
+ input bit [4 : 0] m_axi_arready;
+ input bit [159 : 0] m_axi_rdata;
+ input bit [9 : 0] m_axi_rresp;
+ input bit [4 : 0] m_axi_rvalid;
+ output wire [4 : 0] m_axi_rready;
endmodule
`endif
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/synth/mb_design_1_xbar_0.v b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/synth/mb_design_1_xbar_0.v
index 5fdf27c98bfde9777131e980dbe60c119180cd71..e02014bef517512eca72a130ffbd5a22e11b33ad 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/synth/mb_design_1_xbar_0.v
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/synth/mb_design_1_xbar_0.v
@@ -52,9 +52,9 @@
(* X_CORE_INFO = "axi_crossbar_v2_1_33_axi_crossbar,Vivado 2024.1.2" *)
(* CHECK_LICENSE_TYPE = "mb_design_1_xbar_0,axi_crossbar_v2_1_33_axi_crossbar,{}" *)
-(* CORE_GENERATION_INFO = "mb_design_1_xbar_0,axi_crossbar_v2_1_33_axi_crossbar,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=33,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=4,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0xffffffffffffffff000000004120000000000000400000000000000041400000,C_M_AXI_ADDR_WIDTH=0x00000000000000100000001000\
-00000c,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x00000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001,\
-C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
+(* CORE_GENERATION_INFO = "mb_design_1_xbar_0,axi_crossbar_v2_1_33_axi_crossbar,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=33,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=5,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x000000008000000000000000412000000000000041c0000000000000400000000000000041400000,C_M_AXI_ADDR_WIDTH=0x0000000700\
+00001000000010000000100000000c,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x0000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x0000000100000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISS\
+UING=0x0000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x0000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x0000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module mb_design_1_xbar_0 (
aclk,
@@ -145,61 +145,62 @@ output wire [0 : 0] s_axi_rvalid;
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
-output wire [127 : 0] m_axi_awaddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
-output wire [11 : 0] m_axi_awprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_awvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_awready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
-output wire [127 : 0] m_axi_wdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
-output wire [15 : 0] m_axi_wstrb;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_wvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_wready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
-input wire [7 : 0] m_axi_bresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_bvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_bready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
-output wire [127 : 0] m_axi_araddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
-output wire [11 : 0] m_axi_arprot;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_arvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_arready;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
-input wire [127 : 0] m_axi_rdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
-input wire [7 : 0] m_axi_rresp;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
-input wire [3 : 0] m_axi_rvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128]" *)
+output wire [159 : 0] m_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12]" *)
+output wire [14 : 0] m_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128]" *)
+output wire [159 : 0] m_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16]" *)
+output wire [19 : 0] m_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8]" *)
+input wire [9 : 0] m_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128]" *)
+output wire [159 : 0] m_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12]" *)
+output wire [14 : 0] m_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128]" *)
+input wire [159 : 0] m_axi_rdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8]" *)
+input wire [9 : 0] m_axi_rresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4]" *)
+input wire [4 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS\
1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_D\
OMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING \
2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRES\
-P 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
-output wire [3 : 0] m_axi_rready;
+P 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PRO\
+T 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4]" *)
+output wire [4 : 0] m_axi_rready;
axi_crossbar_v2_1_33_axi_crossbar #(
.C_FAMILY("artix7"),
.C_NUM_SLAVE_SLOTS(1),
- .C_NUM_MASTER_SLOTS(4),
+ .C_NUM_MASTER_SLOTS(5),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
- .C_M_AXI_BASE_ADDR(256'Hffffffffffffffff000000004120000000000000400000000000000041400000),
- .C_M_AXI_ADDR_WIDTH(128'H0000000000000010000000100000000c),
+ .C_M_AXI_BASE_ADDR(320'H000000008000000000000000412000000000000041c0000000000000400000000000000041400000),
+ .C_M_AXI_ADDR_WIDTH(160'H000000070000001000000010000000100000000c),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
@@ -208,16 +209,16 @@ output wire [3 : 0] m_axi_rready;
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
- .C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
- .C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
+ .C_M_AXI_WRITE_CONNECTIVITY(160'H0000000100000001000000010000000100000001),
+ .C_M_AXI_READ_CONNECTIVITY(160'H0000000100000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
- .C_M_AXI_WRITE_ISSUING(128'H00000001000000010000000100000001),
- .C_M_AXI_READ_ISSUING(128'H00000001000000010000000100000001),
+ .C_M_AXI_WRITE_ISSUING(160'H0000000100000001000000010000000100000001),
+ .C_M_AXI_READ_ISSUING(160'H0000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
- .C_M_AXI_SECURE(128'H00000000000000000000000000000000),
+ .C_M_AXI_SECURE(160'H0000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
@@ -285,9 +286,9 @@ output wire [3 : 0] m_axi_rready;
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
- .m_axi_bid(4'H0),
+ .m_axi_bid(5'H00),
.m_axi_bresp(m_axi_bresp),
- .m_axi_buser(4'H0),
+ .m_axi_buser(5'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
@@ -303,11 +304,11 @@ output wire [3 : 0] m_axi_rready;
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
- .m_axi_rid(4'H0),
+ .m_axi_rid(5'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
- .m_axi_rlast(4'HF),
- .m_axi_ruser(4'H0),
+ .m_axi_rlast(5'H1F),
+ .m_axi_ruser(5'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
index f4217e021dfa8a881e7b16ef73d3bf306d786f55..d4a556ff86b5d20cb98a15b760b4eaa083ff8297 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
@@ -1,11 +1,11 @@
WORKFLOW_OPERATION simulation,dialog;
-DEFINE_MEMORY_TYPE blk_mem_gen_0_MEM_DEVICE [0x00008000] 32;
+DEFINE_MEMORY_TYPE blk_mem_gen_0_32K_1_MEM_DEVICE [0x00008000] 32;
ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 microblaze_0
- ADDRESS_SPACE blk_mem_gen_0_ADDR_SPACE blk_mem_gen_0_MEM_DEVICE [0x00000000:0x00007FFF] dlmb_bram_if_cntlr_0
+ ADDRESS_SPACE blk_mem_gen_0_32K_1_ADDR_SPACE blk_mem_gen_0_32K_1_MEM_DEVICE [0x00000000:0x00007FFF] dlmb_bram_if_cntlr_0
BUS_BLOCK
- blk_mem_gen_0_BUS_BLK [31:0] INPUT = "mb_design_1_blk_mem_gen_0_0.mem";
+ blk_mem_gen_0_32K_1_BUS_BLK [31:0] INPUT = "mb_design_1_blk_mem_gen_0_0.mem";
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
index 8aa7f486ff223621d23ec3f7b38d5eeb5a5e6c9a..368f766c22ed5f6a58290b7b7696f3714545f8d7 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="43">
<CompositeFile CompositeFileTopName="mb_design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="STALE" Timestamp="1742483375"/>
- <Generation Name="SIMULATION" State="STALE" Timestamp="1742483375"/>
- <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1742483375"/>
- <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1742483375"/>
+ <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1742491469"/>
+ <Generation Name="SIMULATION" State="GENERATED" Timestamp="1742491469"/>
+ <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1742491469"/>
+ <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1742491469"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth/mb_design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst
index 13f188b862fdc24452945b2f81e51858f4c39b44..5b4f6ae7dd564ff9c4d3dae95eb86bd5c2e6eb29 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst
@@ -3,6 +3,30 @@
"modules": {
"mb_design_1": {
"proto_instances": {
+ "/axi4lite_hog_build_i_0/s_axi": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "s_axi_aclk"},
+ "ARADDR": { "actual": "s_axi_araddr[31:0]"},
+ "ARESETN": { "actual": "s_axi_aresetn"},
+ "ARREADY": { "actual": "s_axi_arready"},
+ "ARVALID": { "actual": "s_axi_arvalid"},
+ "AWADDR": { "actual": "s_axi_awaddr[31:0]"},
+ "AWREADY": { "actual": "s_axi_awready"},
+ "AWVALID": { "actual": "s_axi_awvalid"},
+ "BREADY": { "actual": "s_axi_bready"},
+ "BRESP": { "actual": "s_axi_bresp[1:0]"},
+ "BVALID": { "actual": "s_axi_bvalid"},
+ "RDATA": { "actual": "s_axi_rdata[31:0]"},
+ "RREADY": { "actual": "s_axi_rready"},
+ "RRESP": { "actual": "s_axi_rresp[1:0]"},
+ "RVALID": { "actual": "s_axi_rvalid"},
+ "WDATA": { "actual": "s_axi_wdata[31:0]"},
+ "WREADY": { "actual": "s_axi_wready"},
+ "WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+ "WVALID": { "actual": "s_axi_wvalid"}
+ }
+ },
"/axi_gpio_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
@@ -123,6 +147,54 @@
"WVALID": { "actual": "M02_AXI_wvalid"}
}
},
+ "/axi_interconnect_0/M03_AXI": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "M03_ACLK"},
+ "ARADDR": { "actual": "M03_AXI_araddr[127:96]"},
+ "ARESETN": { "actual": "ARESETN"},
+ "ARREADY": { "actual": "M03_AXI_arready"},
+ "ARVALID": { "actual": "M03_AXI_arvalid"},
+ "AWADDR": { "actual": "M03_AXI_awaddr[127:96]"},
+ "AWREADY": { "actual": "M03_AXI_awready"},
+ "AWVALID": { "actual": "M03_AXI_awvalid"},
+ "BREADY": { "actual": "M03_AXI_bready"},
+ "BRESP": { "actual": "M03_AXI_bresp[7:6]"},
+ "BVALID": { "actual": "M03_AXI_bvalid"},
+ "RDATA": { "actual": "M03_AXI_rdata[127:96]"},
+ "RREADY": { "actual": "M03_AXI_rready"},
+ "RRESP": { "actual": "M03_AXI_rresp[7:6]"},
+ "RVALID": { "actual": "M03_AXI_rvalid"},
+ "WDATA": { "actual": "M03_AXI_wdata[127:96]"},
+ "WREADY": { "actual": "M03_AXI_wready"},
+ "WSTRB": { "actual": "M03_AXI_wstrb[15:12]"},
+ "WVALID": { "actual": "M03_AXI_wvalid"}
+ }
+ },
+ "/axi_interconnect_0/M04_AXI": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "M04_ACLK"},
+ "ARADDR": { "actual": "M04_AXI_araddr[159:128]"},
+ "ARESETN": { "actual": "ARESETN"},
+ "ARREADY": { "actual": "M04_AXI_arready"},
+ "ARVALID": { "actual": "M04_AXI_arvalid"},
+ "AWADDR": { "actual": "M04_AXI_awaddr[159:128]"},
+ "AWREADY": { "actual": "M04_AXI_awready"},
+ "AWVALID": { "actual": "M04_AXI_awvalid"},
+ "BREADY": { "actual": "M04_AXI_bready"},
+ "BRESP": { "actual": "M04_AXI_bresp[9:8]"},
+ "BVALID": { "actual": "M04_AXI_bvalid"},
+ "RDATA": { "actual": "M04_AXI_rdata[159:128]"},
+ "RREADY": { "actual": "M04_AXI_rready"},
+ "RRESP": { "actual": "M04_AXI_rresp[9:8]"},
+ "RVALID": { "actual": "M04_AXI_rvalid"},
+ "WDATA": { "actual": "M04_AXI_wdata[159:128]"},
+ "WREADY": { "actual": "M04_AXI_wready"},
+ "WSTRB": { "actual": "M04_AXI_wstrb[19:16]"},
+ "WVALID": { "actual": "M04_AXI_wvalid"}
+ }
+ },
"/axi_interconnect_0/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
@@ -297,41 +369,23 @@
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
- "ARADDR": { "actual": "M_AXI_araddr"},
- "ARBURST": { "actual": "M_AXI_arburst"},
- "ARCACHE": { "actual": "M_AXI_arcache"},
+ "ARADDR": { "actual": "M_AXI_araddr[127:96]"},
"ARESETN": { "actual": "M_ARESETN"},
- "ARLEN": { "actual": "M_AXI_arlen"},
- "ARLOCK": { "actual": "M_AXI_arlock"},
- "ARPROT": { "actual": "M_AXI_arprot"},
- "ARQOS": { "actual": "M_AXI_arqos"},
"ARREADY": { "actual": "M_AXI_arready"},
- "ARREGION": { "actual": "M_AXI_arregion"},
- "ARSIZE": { "actual": "M_AXI_arsize"},
"ARVALID": { "actual": "M_AXI_arvalid"},
- "AWADDR": { "actual": "M_AXI_awaddr"},
- "AWBURST": { "actual": "M_AXI_awburst"},
- "AWCACHE": { "actual": "M_AXI_awcache"},
- "AWLEN": { "actual": "M_AXI_awlen"},
- "AWLOCK": { "actual": "M_AXI_awlock"},
- "AWPROT": { "actual": "M_AXI_awprot"},
- "AWQOS": { "actual": "M_AXI_awqos"},
+ "AWADDR": { "actual": "M_AXI_awaddr[127:96]"},
"AWREADY": { "actual": "M_AXI_awready"},
- "AWREGION": { "actual": "M_AXI_awregion"},
- "AWSIZE": { "actual": "M_AXI_awsize"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
- "BRESP": { "actual": "M_AXI_bresp"},
+ "BRESP": { "actual": "M_AXI_bresp[7:6]"},
"BVALID": { "actual": "M_AXI_bvalid"},
- "RDATA": { "actual": "M_AXI_rdata"},
- "RLAST": { "actual": "M_AXI_rlast"},
+ "RDATA": { "actual": "M_AXI_rdata[127:96]"},
"RREADY": { "actual": "M_AXI_rready"},
- "RRESP": { "actual": "M_AXI_rresp"},
+ "RRESP": { "actual": "M_AXI_rresp[7:6]"},
"RVALID": { "actual": "M_AXI_rvalid"},
- "WDATA": { "actual": "M_AXI_wdata"},
- "WLAST": { "actual": "M_AXI_wlast"},
+ "WDATA": { "actual": "M_AXI_wdata[127:96]"},
"WREADY": { "actual": "M_AXI_wready"},
- "WSTRB": { "actual": "M_AXI_wstrb"},
+ "WSTRB": { "actual": "M_AXI_wstrb[15:12]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
@@ -339,41 +393,71 @@
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
- "ARADDR": { "actual": "S_AXI_araddr"},
- "ARBURST": { "actual": "S_AXI_arburst"},
- "ARCACHE": { "actual": "S_AXI_arcache"},
+ "ARADDR": { "actual": "S_AXI_araddr[127:96]"},
+ "ARESETN": { "actual": "S_ARESETN"},
+ "ARREADY": { "actual": "S_AXI_arready"},
+ "ARVALID": { "actual": "S_AXI_arvalid"},
+ "AWADDR": { "actual": "S_AXI_awaddr[127:96]"},
+ "AWREADY": { "actual": "S_AXI_awready"},
+ "AWVALID": { "actual": "S_AXI_awvalid"},
+ "BREADY": { "actual": "S_AXI_bready"},
+ "BRESP": { "actual": "S_AXI_bresp[7:6]"},
+ "BVALID": { "actual": "S_AXI_bvalid"},
+ "RDATA": { "actual": "S_AXI_rdata[127:96]"},
+ "RREADY": { "actual": "S_AXI_rready"},
+ "RRESP": { "actual": "S_AXI_rresp[7:6]"},
+ "RVALID": { "actual": "S_AXI_rvalid"},
+ "WDATA": { "actual": "S_AXI_wdata[127:96]"},
+ "WREADY": { "actual": "S_AXI_wready"},
+ "WSTRB": { "actual": "S_AXI_wstrb[15:12]"},
+ "WVALID": { "actual": "S_AXI_wvalid"}
+ }
+ },
+ "/axi_interconnect_0/m04_couplers/M_AXI": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "M_ACLK"},
+ "ARADDR": { "actual": "M_AXI_araddr[159:128]"},
+ "ARESETN": { "actual": "M_ARESETN"},
+ "ARREADY": { "actual": "M_AXI_arready"},
+ "ARVALID": { "actual": "M_AXI_arvalid"},
+ "AWADDR": { "actual": "M_AXI_awaddr[159:128]"},
+ "AWREADY": { "actual": "M_AXI_awready"},
+ "AWVALID": { "actual": "M_AXI_awvalid"},
+ "BREADY": { "actual": "M_AXI_bready"},
+ "BRESP": { "actual": "M_AXI_bresp[9:8]"},
+ "BVALID": { "actual": "M_AXI_bvalid"},
+ "RDATA": { "actual": "M_AXI_rdata[159:128]"},
+ "RREADY": { "actual": "M_AXI_rready"},
+ "RRESP": { "actual": "M_AXI_rresp[9:8]"},
+ "RVALID": { "actual": "M_AXI_rvalid"},
+ "WDATA": { "actual": "M_AXI_wdata[159:128]"},
+ "WREADY": { "actual": "M_AXI_wready"},
+ "WSTRB": { "actual": "M_AXI_wstrb[19:16]"},
+ "WVALID": { "actual": "M_AXI_wvalid"}
+ }
+ },
+ "/axi_interconnect_0/m04_couplers/S_AXI": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "S_ACLK"},
+ "ARADDR": { "actual": "S_AXI_araddr[159:128]"},
"ARESETN": { "actual": "S_ARESETN"},
- "ARLEN": { "actual": "S_AXI_arlen"},
- "ARLOCK": { "actual": "S_AXI_arlock"},
- "ARPROT": { "actual": "S_AXI_arprot"},
- "ARQOS": { "actual": "S_AXI_arqos"},
"ARREADY": { "actual": "S_AXI_arready"},
- "ARREGION": { "actual": "S_AXI_arregion"},
- "ARSIZE": { "actual": "S_AXI_arsize"},
"ARVALID": { "actual": "S_AXI_arvalid"},
- "AWADDR": { "actual": "S_AXI_awaddr"},
- "AWBURST": { "actual": "S_AXI_awburst"},
- "AWCACHE": { "actual": "S_AXI_awcache"},
- "AWLEN": { "actual": "S_AXI_awlen"},
- "AWLOCK": { "actual": "S_AXI_awlock"},
- "AWPROT": { "actual": "S_AXI_awprot"},
- "AWQOS": { "actual": "S_AXI_awqos"},
+ "AWADDR": { "actual": "S_AXI_awaddr[159:128]"},
"AWREADY": { "actual": "S_AXI_awready"},
- "AWREGION": { "actual": "S_AXI_awregion"},
- "AWSIZE": { "actual": "S_AXI_awsize"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
- "BRESP": { "actual": "S_AXI_bresp"},
+ "BRESP": { "actual": "S_AXI_bresp[9:8]"},
"BVALID": { "actual": "S_AXI_bvalid"},
- "RDATA": { "actual": "S_AXI_rdata"},
- "RLAST": { "actual": "S_AXI_rlast"},
+ "RDATA": { "actual": "S_AXI_rdata[159:128]"},
"RREADY": { "actual": "S_AXI_rready"},
- "RRESP": { "actual": "S_AXI_rresp"},
+ "RRESP": { "actual": "S_AXI_rresp[9:8]"},
"RVALID": { "actual": "S_AXI_rvalid"},
- "WDATA": { "actual": "S_AXI_wdata"},
- "WLAST": { "actual": "S_AXI_wlast"},
+ "WDATA": { "actual": "S_AXI_wdata[159:128]"},
"WREADY": { "actual": "S_AXI_wready"},
- "WSTRB": { "actual": "S_AXI_wstrb"},
+ "WSTRB": { "actual": "S_AXI_wstrb[19:16]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
@@ -533,6 +617,32 @@
"WVALID": { "actual": "m_axi_wvalid[3:3]"}
}
},
+ "/axi_interconnect_0/xbar/M04_AXI": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "aclk"},
+ "ARADDR": { "actual": "m_axi_araddr[159:128]"},
+ "ARESETN": { "actual": "aresetn"},
+ "ARPROT": { "actual": "m_axi_arprot[14:12]"},
+ "ARREADY": { "actual": "m_axi_arready[4:4]"},
+ "ARVALID": { "actual": "m_axi_arvalid[4:4]"},
+ "AWADDR": { "actual": "m_axi_awaddr[159:128]"},
+ "AWPROT": { "actual": "m_axi_awprot[14:12]"},
+ "AWREADY": { "actual": "m_axi_awready[4:4]"},
+ "AWVALID": { "actual": "m_axi_awvalid[4:4]"},
+ "BREADY": { "actual": "m_axi_bready[4:4]"},
+ "BRESP": { "actual": "m_axi_bresp[9:8]"},
+ "BVALID": { "actual": "m_axi_bvalid[4:4]"},
+ "RDATA": { "actual": "m_axi_rdata[159:128]"},
+ "RREADY": { "actual": "m_axi_rready[4:4]"},
+ "RRESP": { "actual": "m_axi_rresp[9:8]"},
+ "RVALID": { "actual": "m_axi_rvalid[4:4]"},
+ "WDATA": { "actual": "m_axi_wdata[159:128]"},
+ "WREADY": { "actual": "m_axi_wready[4:4]"},
+ "WSTRB": { "actual": "m_axi_wstrb[19:16]"},
+ "WVALID": { "actual": "m_axi_wvalid[4:4]"}
+ }
+ },
"/axi_interconnect_0/xbar/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
@@ -559,6 +669,30 @@
"WVALID": { "actual": "s_axi_wvalid[0:0]"}
}
},
+ "/axi_timer_0/S_AXI": {
+ "interface": "xilinx.com:interface:aximm:1.0",
+ "ports": {
+ "ACLK": { "actual": "s_axi_aclk"},
+ "ARADDR": { "actual": "s_axi_araddr[4:0]"},
+ "ARESETN": { "actual": "s_axi_aresetn"},
+ "ARREADY": { "actual": "s_axi_arready"},
+ "ARVALID": { "actual": "s_axi_arvalid"},
+ "AWADDR": { "actual": "s_axi_awaddr[4:0]"},
+ "AWREADY": { "actual": "s_axi_awready"},
+ "AWVALID": { "actual": "s_axi_awvalid"},
+ "BREADY": { "actual": "s_axi_bready"},
+ "BRESP": { "actual": "s_axi_bresp[1:0]"},
+ "BVALID": { "actual": "s_axi_bvalid"},
+ "RDATA": { "actual": "s_axi_rdata[31:0]"},
+ "RREADY": { "actual": "s_axi_rready"},
+ "RRESP": { "actual": "s_axi_rresp[1:0]"},
+ "RVALID": { "actual": "s_axi_rvalid"},
+ "WDATA": { "actual": "s_axi_wdata[31:0]"},
+ "WREADY": { "actual": "s_axi_wready"},
+ "WSTRB": { "actual": "s_axi_wstrb[3:0]"},
+ "WVALID": { "actual": "s_axi_wvalid"}
+ }
+ },
"/mdm_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
index 0dd7f56ac3047c33fcae4003b781f6084ff10a13..31ee449f7230acf0288333a5305b127d450eccaf 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
---Date : Thu Mar 20 16:44:45 2025
+--Date : Thu Mar 20 18:24:28 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1.bd
--Design : mb_design_1
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef
index 728308e3ffe4ef9e91bb2c2bc638488b7366925f..e2b07d69b04d568db76b18f84c1b865f8910f723 100644
Binary files a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef and b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.hwdef differ
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
index 0dd7f56ac3047c33fcae4003b781f6084ff10a13..31ee449f7230acf0288333a5305b127d450eccaf 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
---Date : Thu Mar 20 16:44:45 2025
+--Date : Thu Mar 20 18:24:28 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1.bd
--Design : mb_design_1
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
index 15b940b54cf99b4fee5b799e4dcc585c2299e340..91c8936222d0ce06607c59b4e00ff5fdee265894 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
@@ -72,26 +72,26 @@
"mode": "slave",
"memory_map_ref": "s_axi",
"parameters": {
- "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd b/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd
index d5059da2086d4a1494d108995ddfe128f9deab87..425d4c22ed755dd5e64f62c807161ef5c522af03 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd
@@ -18,7 +18,7 @@ entity mb_design_1_wrapper is
GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_VER : std_logic_vector(31 downto 0) := (others => '0');
- GLOBAL_SHA : std_logic_vector(31 downto 0) := (others => '0');
+ GLOBAL_SHA : std_logic_vector(31 downto 0) := (others => '0')
);
port (
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );