Adding the scalp_node folder containing the board definition.

README.md

 # scalp_board_files
 
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-cd existing_repo
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+### Vivado board files for SCALP boards
 
-## Project status
-If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers.
+In order to add the ```Scalp board``` support to Vivado, the ```scalp_node``` folder must be copied to the ```<Vivado directory>/<version>/data/xhub/boards/XilinxBoardStore/boards/``` folder. To create a new project targeting the ```Scalp``` board, the ```"hepia-cores.ch:scalp_node:part0:0.2"``` board tag must be used. In addition, this board definition doesn't provide a fully accurate definition of the board and must evolve in the future.

scalp_node/0.1/board.xml

+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.1" vendor="hepia-cores.ch" name="scalp_node" display_name="SCALP node" url="https://gitedu.hesge.ch/soma/scalp_board/-/wikis/pcb/scalp_mainboard">
+  <images>
+    <image name="SCALP_board.jpg" display_name="SCALP BOARD" sub_type="board">
+      <description>SCALP Board File Image</description>
+    </image>
+  </images>
+  <compatible_board_revisions>
+    <revision id="1">B</revision>
+  </compatible_board_revisions>
+  <file_version>0.1</file_version>
+  <description>SCALP: Self-configurable 3-D Cellular multi-FPGA Adaptive Platform</description>
+  <components>
+    <component name="part0" display_name="SCALP Zynq7015 FPGA" type="fpga" part_name="xc7z015clg485-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://gitedu.hesge.ch/soma/scalp_board/-/wikis/home">
+      <interfaces>
+        <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+        </interface>
+      </interfaces>
+    </component>
+    <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  </components>
+  <jtag_chains>
+    <jtag_chain name="chain1">
+      <position name="0" component="part0"/>
+    </jtag_chain>
+  </jtag_chains>
+  <connections>
+  </connections>
+</board>

scalp_node/0.1/changelog.txt

+0.1
+Initial public release
+

scalp_node/0.1/part0_pins.xml

+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<part_info part_name="xc7z015clg485-2">
+<pins>
+</pins>
+</part_info>

scalp_node/0.2/board.xml

+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<board schema_version="2.1" vendor="hepia-cores.ch" name="scalp_node" display_name="SCALP node" url="https://gitedu.hesge.ch/soma/scalp_board/-/wikis/pcb/scalp_mainboard">
+  <images>
+    <image name="SCALP_board.png" display_name="SCALP BOARD" sub_type="board">
+      <description>SCALP Board File Image</description>
+    </image>
+  </images>
+  <compatible_board_revisions>
+    <revision id="1">C</revision>
+  </compatible_board_revisions>
+  <file_version>0.2</file_version>
+  <description>SCALP: Self-configurable 3-D Cellular multi-FPGA Adaptive Platform</description>
+  <components>
+    <component name="part0" display_name="SCALP Zynq7015 FPGA" type="fpga" part_name="xc7z015clg485-2" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://gitedu.hesge.ch/soma/scalp_board/-/wikis/home">
+      <interfaces>
+        <interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
+        </interface>
+      </interfaces>
+    </component>
+    <component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
+  </components>
+  <jtag_chains>
+    <jtag_chain name="chain1">
+      <position name="0" component="part0"/>
+    </jtag_chain>
+  </jtag_chains>
+  <connections>
+  </connections>
+</board>

scalp_node/0.2/changelog.txt

+0.2
+Initial public release

scalp_node/0.2/part0_pins.xml

+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<part_info part_name="xc7z015clg485-2">
+<pins>
+</pins>
+</part_info>