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Finished Bachelor's thesis report

Summary

The final version of the Bachelor's thesis report has been completed (as much as possible) and submitted. Current thesis status and respective files are being pushed to the main documentation branch.

Type

  • FPGA: VHDL/testbenches/constraints
  • Thesis: content/structure
  • Presentation: slides/assets
  • Personal Notes: documents/diagrams
  • Fix: bug/typo
  • Documentation
  • Other: ___

Changes

  • Completed the Bachelor thesis as much as possible before final submission
  • Changed thesis' internal structure
  • Added more figures
  • Added missing "administrative" parts from June's draft

Testing

  • Code compiles/builds
  • Documents render correctly
  • No broken links/references

Branch: docs-devel/thesis-final-augustdocs
Author: @Alejandro.Escribano

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