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pl-user.dtsi 5.58 KiB
/*
* Scalp Board PL User DTS
*
* Copyright (c) 2018-2021 Hepia
* Orphee Antoniadis <orphee.antoniadis@hesge.ch>
*
*/
/ {
amba_pl: amba_pl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges ;
scalp_safe_firmware_0: scalp_safe_firmware_reg_bank@43c10000 {
//clock-names = "SAxiClkxCI";
//clocks = <&clkc 15>;
compatible = "generic-uio";
reg = <0x43c10000 0x1000>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <200000000>;
compatible = "fixed-clock";
};
mipi_csi2_rx_subsyst_0: mipi_csi2_rx_subsystem@43c20000 {
clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
clocks = <&clkc 15>, <&misc_clk_0>, <&clkc 15>;
compatible = "xlnx,mipi-csi2-rx-subsystem-5.1";
reg = <0x43c20000 0x1000>;
interrupt-names = "csirxss_csi_irq";
interrupt-parent = <&intc>;
interrupts = <0 30 4>;
xlnx,axis-tdata-width = <32>;
xlnx,cal-mode = "NONE";
xlnx,clk-io-swap = "false";
xlnx,clk-lane-io-position = <0x0>;
xlnx,clk-lp-io-swap = "false";
xlnx,csi-en-activelanes = "false";
xlnx,csi-en-crc = "true";
xlnx,csi-filter-userdatatype = "false";
xlnx,csi-opt1-regs = "false";
xlnx,csi-pxl-format = "YUV422_8bit";
xlnx,csi2rx-dbg = <0x0>;
xlnx,data-lane0-io-position = <0x2>;
xlnx,data-lane1-io-position = <0x4>;
xlnx,data-lane2-io-position = <0x6>;
xlnx,data-lane3-io-position = <0x8>;
xlnx,dl0-io-swap = "false";
xlnx,dl0-lp-io-swap = "false";
xlnx,dl1-io-swap = "false";
xlnx,dl1-lp-io-swap = "false";
xlnx,dl2-io-swap = "false";
xlnx,dl2-lp-io-swap = "false";
xlnx,dl3-io-swap = "false";
xlnx,dl3-lp-io-swap = "false";
xlnx,dphy-lanes = <0x2>;
xlnx,dphy-mode = "SLAVE";
xlnx,en-7s-linerate-check = "false";
xlnx,en-bg0-pin0 = "false";
xlnx,en-bg0-pin6 = "false";
xlnx,en-bg1-pin0 = "false";
xlnx,en-bg1-pin6 = "false";
xlnx,en-bg2-pin0 = "false";
xlnx,en-bg2-pin6 = "false";
xlnx,en-bg3-pin0 = "false";
xlnx,en-bg3-pin6 = "false"; xlnx,en-clk300m = "false";
xlnx,en-cnts-byte-clk = "false";
xlnx,en-csi-v2-0 = "false";
xlnx,en-exdesigns = "false";
xlnx,en-ext-tap = "false";
xlnx,en-timeout-regs = "false";
xlnx,en-vcx = "false";
xlnx,esc-timeout = <0x6400>;
xlnx,exdes-board = "ZCU102";
xlnx,exdes-config = "MIPI_Video_Pipe_Camera_to_Display";
xlnx,exdes-fmc = "LI-IMX274MIPI-FMC V1.0 Single Sensor";
xlnx,exdesboard-version = "xilinx.com:vck190:part0:2.0";
xlnx,fifo-rd-en-control = "true";
xlnx,hs-line-rate = <0x320>;
xlnx,hs-settle-ns = <0x93>;
xlnx,hs-timeout = <0x10005>;
xlnx,idly-group-name = "mipi_csi2rx_idly_group";
xlnx,idly-tap = <0x1>;
xlnx,init = <0x186a0>;
xlnx,int-qor-check = <0x0>;
xlnx,is-7series = "true";
xlnx,is-versal = "false";
xlnx,lprx-disable-extport = <0x0>;
xlnx,max-lanes = <2>;
xlnx,mipi-slv-int = <0x0>;
xlnx,ooc-vid-clk = "6.666";
xlnx,ppc = <1>;
xlnx,rcve-alt-deskew-seq = "false";
xlnx,rcve-deskew-seq = "false";
xlnx,share-idlyctrl = "false";
xlnx,stretch-line-rate = <0xdac>;
xlnx,vc = <4>;
xlnx,vfb ;
mipi_csi_portsmipi_csi2_rx_subsyst_0: ports {
#address-cells = <1>;
#size-cells = <0>;
mipi_csi_port0mipi_csi2_rx_subsyst_0: port@0 {
reg = <0>;
xlnx,cfa-pattern = "rggb";
xlnx,video-format = <12>;
xlnx,video-width = <8>;
mipi_csirx_outmipi_csi2_rx_subsyst_0: endpoint {
remote-endpoint = <&v_frmbuf_wr_0mipi_csi2_rx_subsyst_0>;
};
};
mipi_csi_port1mipi_csi2_rx_subsyst_0: port@1 {
reg = <1>;
xlnx,cfa-pattern = "rggb";
xlnx,video-format = <12>;
xlnx,video-width = <8>;
mipi_csi_inmipi_csi2_rx_subsyst_0: endpoint {
};
};
};
};
v_frmbuf_wr_0: v_frmbuf_wr@43c30000 {
#dma-cells = <1>;
clock-names = "ap_clk";
clocks = <&clkc 15>;
compatible = "xlnx,v-frmbuf-wr-2.2", "xlnx,axi-frmbuf-wr-v2.1";
reg = <0x43c30000 0x10000>;
interrupt-names = "interrupt";
interrupt-parent = <&intc>;
interrupts = <0 31 4>;
xlnx,dma-addr-width = <32>;
xlnx,dma-align = <8>;
xlnx,max-height = <480>;
xlnx,max-width = <640>;
xlnx,pixels-per-clock = <1>; xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,s-axi-ctrl-data-width = <0x20>;
xlnx,vid-formats = "rgb888", "uyvy";
xlnx,video-width = <8>;
};
vcap_mipi_csi2_rx_subsyst_0 {
compatible = "xlnx,video";
dma-names = "port0";
dmas = <&v_frmbuf_wr_0 0>;
vcap_portsmipi_csi2_rx_subsyst_0: ports {
#address-cells = <1>;
#size-cells = <0>;
vcap_portmipi_csi2_rx_subsyst_0: port@0 {
direction = "input";
reg = <0>;
v_frmbuf_wr_0mipi_csi2_rx_subsyst_0: endpoint {
remote-endpoint = <&mipi_csirx_outmipi_csi2_rx_subsyst_0>;
};
};
};
};
};
};