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Commit 86f7995d authored by joachim.schmidt's avatar joachim.schmidt
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Addition of Zynq SoC.

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soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hdl/scalp_zynqps_wrapper.vhd deleted 100644 → 0
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--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
--Date : Mon Sep 7 11:52:31 2020
--Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
--Command : generate_target scalp_zynqps_wrapper.bd
--Design : scalp_zynqps_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scalp_zynqps_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FclkClk0xCO : out STD_LOGIC;
FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
Spi1MOSIxSO : out STD_LOGIC;
Spi1SSxSO : out STD_LOGIC;
Spi1SclkxCO : out STD_LOGIC;
Usb0VBusPwrFaultxSI : in STD_LOGIC
);
end scalp_zynqps_wrapper;
architecture STRUCTURE of scalp_zynqps_wrapper is
component scalp_zynqps is
port (
FclkClk0xCO : out STD_LOGIC;
FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
Spi1MOSIxSO : out STD_LOGIC;
Spi1SSxSO : out STD_LOGIC;
Spi1SclkxCO : out STD_LOGIC;
Usb0VBusPwrFaultxSI : in STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component scalp_zynqps;
begin
scalp_zynqps_i: component scalp_zynqps
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
FclkClk0xCO => FclkClk0xCO,
FclkReset0xRO(0) => FclkReset0xRO(0),
Spi1MOSIxSO => Spi1MOSIxSO,
Spi1SSxSO => Spi1SSxSO,
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI
);
end STRUCTURE;
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci deleted 100644 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>scalp_zynqps_gnd_constant_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">scalp_zynqps_gnd_constant_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xml deleted 100644 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>scalp_zynqps_gnd_constant_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_verilogsynthesis</spirit:name>
<spirit:displayName>Verilog Synthesis</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>xlconstant_v1_1_6_xlconstant</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 07 09:52:31 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9de780d2</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9de780d2</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>scalp_zynqps_gnd_constant_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 07 09:52:31 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9de780d2</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
<spirit:displayName>Verilog Simulation</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>xlconstant_v1_1_6_xlconstant</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 07 09:52:31 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9c0e4d15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_systemcsimulation</spirit:name>
<spirit:displayName>SystemC Simulation</spirit:displayName>
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:language>systemc</spirit:language>
<spirit:modelName>xlconstant_v1_1_6</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_systemcsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 07 09:52:31 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9c0e4d15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>tlm</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>scalp_zynqps_gnd_constant_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 07 09:52:31 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9c0e4d15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_systemcsimulationwrapper</spirit:name>
<spirit:displayName>SystemC Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>systemCSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>systemc</spirit:language>
<spirit:modelName>scalp_zynqps_gnd_constant_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_systemcsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 07 09:52:31 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:9c0e4d15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>sim_type</spirit:name>
<spirit:value>tlm</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>dout</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>CONST_WIDTH</spirit:name>
<spirit:displayName>Const Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>CONST_VAL</spirit:name>
<spirit:displayName>Const Val</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x0</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xlconstant_v1_1_6</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/scalp_zynqps_gnd_constant_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>../../ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xlconstant_v1_1_6</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_systemcsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/xlconstant_v1_1_6.h</spirit:name>
<spirit:fileType>systemCSource</spirit:fileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/scalp_zynqps_gnd_constant_0.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_systemcsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/scalp_zynqps_gnd_constant_0.h</spirit:name>
<spirit:fileType>systemCSource</spirit:fileType>
<spirit:isIncludeFile>true</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>Gives a constant signed value.</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">scalp_zynqps_gnd_constant_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CONST_WIDTH</spirit:name>
<spirit:displayName>Const Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CONST_VAL</spirit:name>
<spirit:displayName>Const Val</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>Constant</xilinx:displayName>
<xilinx:coreRevision>6</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CONST_VAL" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2c73a505"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.h deleted 100644 → 0
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// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _scalp_zynqps_gnd_constant_0_H_
#define _scalp_zynqps_gnd_constant_0_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class scalp_zynqps_gnd_constant_0 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v deleted 100644 → 0
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// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module scalp_zynqps_gnd_constant_0 (
dout
);
output wire [0 : 0] dout;
xlconstant_v1_1_6_xlconstant #(
.CONST_WIDTH(1),
.CONST_VAL('H0)
) inst (
.dout(dout)
);
endmodule
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/xlconstant_v1_1_6.h deleted 100644 → 0
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// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _xlconstant_v1_1_6_H_
#define _xlconstant_v1_1_6_H_
#include "systemc.h"
template<int CONST_WIDTH,int CONST_VAL>
SC_MODULE(xlconstant_v1_1_6) {
public:
sc_out< sc_bv<CONST_WIDTH> > dout;
void init() {
dout.write(CONST_VAL);
}
SC_CTOR(xlconstant_v1_1_6) {
SC_METHOD(init);
}
};
#endif
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v deleted 100644 → 0
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// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 6
(* X_CORE_INFO = "xlconstant_v1_1_6_xlconstant,Vivado 2019.2" *)
(* CHECK_LICENSE_TYPE = "scalp_zynqps_gnd_constant_0,xlconstant_v1_1_6_xlconstant,{}" *)
(* CORE_GENERATION_INFO = "scalp_zynqps_gnd_constant_0,xlconstant_v1_1_6_xlconstant,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module scalp_zynqps_gnd_constant_0 (
dout
);
output wire [0 : 0] dout;
xlconstant_v1_1_6_xlconstant #(
.CONST_WIDTH(1),
.CONST_VAL('H0)
) inst (
.dout(dout)
);
endmodule
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.h deleted 100644 → 0
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/******************************************************************************
*
* Copyright (C) 2010-2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 750000000
#define DDR_FREQ 500000000
#define DCI_FREQ 10204082
#define QSPI_FREQ 134615387
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 97222221
#define UART_FREQ 97222221
#define SPI_FREQ 159090912
#define I2C_FREQ 125000000
#define WDT_FREQ 125000000
#define TTC_FREQ 50000000
#define CAN_FREQ 97222221
#define PCAP_FREQ 194444443
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 125000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.h deleted 100644 → 0
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/******************************************************************************
*
* Copyright (C) 2010-2019 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 750000000
#define DDR_FREQ 500000000
#define DCI_FREQ 10204082
#define QSPI_FREQ 134615387
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 97222221
#define UART_FREQ 97222221
#define SPI_FREQ 159090912
#define I2C_FREQ 125000000
#define WDT_FREQ 125000000
#define TTC_FREQ 50000000
#define CAN_FREQ 97222221
#define PCAP_FREQ 194444443
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 125000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
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