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 #MCUXpresso IDE
-#Wed Mar 19 10:42:48 CET 2025
+#Wed Mar 19 11:08:44 CET 2025
 product.name=MCUXpresso IDE v11.10.0 [Build 3148] [2024-07-03]
 product.version=11.10.0
 product.build=3148

CMSISv2p00_LPC17xx/docs/cmsis_readme.txt

+CMSIS : Cortex Microcontroller Software Interface Standard
+==========================================================
+
+Introduction
+~~~~~~~~~~~~
+CMSIS defines for a Cortex-M Microcontroller System:
+
+    * A common way to access peripheral registers and a 
+      common way to define exception vectors.
+    * The register names of the Core Peripherals and the 
+      names of the Core Exception Vectors.
+    * An device independent interface for RTOS Kernels 
+      including a debug channel.
+
+By using CMSIS compliant software components, the user can 
+easier re-use template code. CMSIS is intended to enable the
+combination of software components from multiple middleware 
+vendors. 
+
+This project contains appropriate files for this MCU family 
+taken from CMSIS. A full copy of the CMSIS files, together
+with additional information on CMSIS can be found at:
+
+  http://www.onarm.com/
+  http://www.arm.com/
+
+Documentation
+~~~~~~~~~~~~~
+The standard CMSIS documentation can be found within the
+Code Red IDE help system, via:
+
+Help -> Help Contents -> Code Red Product Documentation -> CMSIS
+
+More information on the use of CMSIS within the Code Red IDE
+can be found in the Support area of the Code Red website at
+
+  http://www.code-red-tech.com/
+
+At the time of writing, the CMSIS FAQ can be found directly
+at:
+
+  http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS
+
+

CMSISv2p00_LPC17xx/history.txt

+History of updates to CMSISv2p00_LPC17xx
+========================================
+
+7 March 2011
+------------
+LPC17xx CMSIS 2.0 library project using ARM 
+Cortex-M3 CMSIS files as supplied in ARM's CMSIS 2.0
+December 2010 release, together with device/board 
+specific files from NXP (as previously supplied in
+CMSISv1p30_LPC17xx library project, dated 24 Aug 2010).
+
+Note files are built -Os for both Debug and Release
\ No newline at end of file

CMSISv2p00_LPC17xx/inc/system_LPC17xx.h

+/**************************************************************************//**
+ * @file     system_LPC17xx.h
+ * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ *           for the NXP LPC17xx Device Series
+ * @version  V1.02
+ * @date     08. September 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */

CMSISv2p00_LPC17xx/src/core_cm3.c

+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V2.00
+ * @date     13. September 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __CLREX(void)
+{
+  clrex
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_IPSR(void)
+{
+  mrs r0, ipsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_APSR(void)
+{
+  mrs r0, apsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_xPSR(void)
+{
+  mrs r0, xpsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask Register.
+
+    \return               Fault Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set the Fault Mask
+
+     This function assigns the given value to the Fault Mask Register.
+
+    \param [in]    faultMask  Fault Mask value value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif

FreeRTOSWithTraces/FreeRTOS_include/projdefs.h

+/*
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
+	
+
+	FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
+	Atollic AB - Atollic provides professional embedded systems development 
+	tools for C/C++ development, code analysis and test automation.  
+	See http://www.atollic.com
+	
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+    >>>NOTE<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+    more details. You should have received a copy of the GNU General Public
+    License and the FreeRTOS license exception along with FreeRTOS; if not it
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained
+    by writing to Richard Barry, contact details for whom are available on the
+    FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    http://www.FreeRTOS.org - Documentation, latest information, license and
+    contact details.
+
+    http://www.SafeRTOS.com - A version that is certified for use in safety
+    critical systems.
+
+    http://www.OpenRTOS.com - Commercial support, development, porting,
+    licensing and training services.
+*/
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/* Defines the prototype to which task functions must conform. */
+typedef void (*pdTASK_CODE)( void * );
+
+#define pdTRUE		( 1 )
+#define pdFALSE		( 0 )
+
+#define pdPASS									( 1 )
+#define pdFAIL									( 0 )
+#define errQUEUE_EMPTY							( 0 )
+#define errQUEUE_FULL							( 0 )
+
+/* Error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errNO_TASK_TO_RUN						( -2 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+#endif /* PROJDEFS_H */
+
+
+