Parallel computation has appeared as the most promising technique to circumvent the limitations imposed by power consumption in order to continue increasing computation power, making thus manycore architectures a promising computer organization approach. Interconnecting and coordinating such high amount of computation nodes in an efficient manner is a hot research topic, several approaches to Network-on-chip architectures propose solutions for this. SCALP is a 3D multi-FPGA hardware platform permitting to prototype 3D NoC architectures with dynamic topologies.
We intend to use it to prototype self-adaptive and self-organizing hardware architectures in which the computation performed by a node and the interconnections between these nodes can be dynamically modified, being these modifications triggered by the platform itself. However, SCALP can be used as an implementation testbed in several domains. Routing algorithms, cellular computation, scalable neural architectures, distributed computation, asynchonous systems, are just a few examples. Some of the features to be tackled by the systems implemented with SCALP are scalability, enhanced reconfigurability and distributedness.
The SCALP node
The SCALP node is mainly composed of a Xilinx Zynq SoC( dual-core ARM Cortex-A9 @866~MHz + Artix-7 programmable logic with 74,000~cells), 2~Gb DDR3 SDRAM, a 5-port Ethernet switch, a PLL. For more information, please check SCALP node wiki page.
The SCALP base board
The base board provides power supply for a SCALP node or a stack of nodes. It also contains an Ethernet phy permitting to access the Ethernet switch on the SCALP board, a MIPI interface, and an USB OTG. For more information, please check SCALP base board wiki page.
Each SCALP node has been designed to communicate with its four neighbors in a two dimensional grid through 4~high-speed serial interfaces capable to sustain data rates up to 6.25~Gb/s. The architecture also foresees serial links to the top and bottom modules, implemented with differential pairs LVDS allowing to reach data rates up to 928~Mb/s in both directions.
NoC prototyping platform
The stacking architecture permits to build arbitrary 3D grid multi-FPGA topologies. A routing algorithm (implemented in the FPGA) permits to communicate between remote nodes thanks by means of unicast, broadacst and reduce mecanisms.
The SCALP platform has been developed by the CoRES team at Hepia in the framework of the SOMA project (Self-Organizing Machine Architecture) funded by the Swiss National Science Foundation (SNSF) and the French National Research Agency (ANR). For more information please contact Prof. Andres Upegui