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Commit 229786e3 authored by joachim.schmidt's avatar joachim.schmidt
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Update Scalp Register Editor

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{
"config" : {
"entity_name" : "scalp_fast_router_registers",
"entity_version" : "1.4",
"entity_reg_io_access" : true,
"block_name" : "ScalpFastRouterRegisters",
"bd_name" : "/scalp_axi4lite_0/SAXILitexDIO",
"bd_interface" : "SAXILitexDIO",
"bd_slave_segment" : "SAXILiteAddr",
"bd_master_base_address" : "0x43C00000",
"bd_range" : "4K"
},
"register_bank" : [
{
"register_status_active" : true,
"register_name" : "LocalNetAddr",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "rw",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "RGBLed0",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "rw",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "RGBLed1",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "rw",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "DMAFifoTXWrDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "DMAFifoTXRrDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "DMAFifoTXStatus",
"register_size" : "32",
"register_type" : "stat",
"register_access_mode" : "ro",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"TX_PROG_EMPTY" : 1,
"TX_PROG_FULL" : 1,
"RESERVED" : 30
}
},
{
"register_status_active" : true,
"register_name" : "DMAFifoRXWrDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "DMAFifoRXRrDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "DMAFifoRXStatus",
"register_size" : "32",
"register_type" : "stat",
"register_access_mode" : "ro",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"RX_PROG_EMPTY" : 1,
"RX_PROG_FULL" : 1,
"RESERVED" : 30
}
},
{
"register_status_active" : true,
"register_name" : "QoSPhyStatus",
"register_size" : "32",
"register_type" : "stat",
"register_access_mode" : "ro",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"NORTH" : 1,
"EAST" : 1,
"SOUTH" : 1,
"WEST" : 1,
"TOP" : 1,
"BOTTOM" : 1,
"LOCAL" : 1,
"RESERVED" : 25
}
},
{
"register_status_active" : true,
"register_name" : "QoSDMAInitOcpCtrl",
"register_size" : "32",
"register_type" : "ocp",
"register_access_mode" : "wo",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"NORTH" : 1,
"EAST" : 1,
"SOUTH" : 1,
"WEST" : 1,
"TOP" : 1,
"BOTTOM" : 1,
"LOCAL" : 1,
"RESERVED" : 25
}
},
{
"register_status_active" : true,
"register_name" : "QoSDMAInitStatus",
"register_size" : "32",
"register_type" : "stat",
"register_access_mode" : "ro",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"NORTH" : 1,
"EAST" : 1,
"SOUTH" : 1,
"WEST" : 1,
"TOP" : 1,
"BOTTOM" : 1,
"LOCAL" : 1,
"RESERVED" : 25
}
}
]
}
{
"config" : {
"entity_name" : "scalp_router_regbank",
"entity_version" : "0.1",
"entity_reg_io_access" : true,
"block_name" : "ScalpRouterRegBank",
"bd_name" : "/scalp_axi4lite_0/SAXILitexDIO",
"bd_interface" : "SAXILitexDIO",
"bd_slave_segment" : "SAXILiteAddr",
"bd_master_base_address" : "0x43C00000",
"bd_range" : "4K"
},
"register_bank" : [
{
"register_status_active" : true,
"register_name" : "ScalpPacketWriteData",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "rw",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "ScalpPacketReadData",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "ScalpPacketCtrl",
"register_size" : "32",
"register_type" : "ctrl",
"register_access_mode" : "wo",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"WRITE_VALID" : 1,
"WRITE_LAST" : 1,
"WRITE_READY" : 1,
"WRITE_NEXT" : 1,
"RESET_ALL_FIFO" : 1,
"WRITE_H0" : 1,
"WRITE_H1" : 1,
"WRITE_H2" : 1,
"WRITE_PLD" : 1,
"WRITE_NEW_PACKET" : 1,
"READ_NEXT" : 1,
"READ_NEW_PACKET" : 1,
"RESERVED" : 20
}
},
{
"register_status_active" : true,
"register_name" : "ScalpPacketStatus",
"register_size" : "32",
"register_type" : "stat",
"register_access_mode" : "ro",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"READ_VALID" : 1,
"READ_LAST" : 1,
"TX_PROG_FULL" : 1,
"RX_PROG_FULL" : 1,
"READ_WAIT_NEXT" : 1,
"RESERVED" : 27
}
},
{
"register_status_active" : true,
"register_name" : "TXWrDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "TXRdDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "RXWrDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "RXRdDataCnt",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "ro",
"register_multifield" : false,
"register_initial_value" : 0
},
{
"register_status_active" : true,
"register_name" : "LocNetAddr",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "rw",
"register_multifield" : false,
"register_initial_value" : 0,
"register_fields" : {
"SCALP_ADDR_X" : 8,
"SCALP_ADDR_Y" : 8,
"SCALP_ADDR_Z" : 8,
"RESERVED" : 8
}
}
]
}
{
"reg1" :
[
{
"bits" : 16,
"name" : "ScalpPacketWriteData",
"type" : 1,
"attr" : [
"reg_type : data",
"reg_access_mode : rw",
"reg_address: 0x43C00000"
]
},
{
"bits" : 16,
"name" : "ScalpPacketWriteData",
"type" : 1
}
],
"reg2" :
[
{
"bits" : 16,
"name" : "ScalpPacketReadData",
"type" : 1,
"attr" : [
"reg_type : data",
"reg_access_mode : ro",
"reg_address: 0x43C00004"
]
},
{
"bits" : 16,
"name" : "ScalpPacketReadData",
"type" : 1
}
]
}
{
"config" : {
"entity_name" : "scalp_safe_firmware_reg_bank",
"entity_version" : "0.2",
"entity_reg_io_access" : true,
"block_name" : "ScalpSafeFirmwareRegBank",
"bd_name" : "/scalp_axi4lite_0/SAXILitexDIO",
"bd_interface" : "SAXILitexDIO",
"bd_slave_segment" : "SAXILiteAddr",
"bd_master_base_address" : "0x43C10000",
"bd_range" : "4K"
},
"register_bank" : [
{
"register_status_active" : true,
"register_name" : "RgbLedsCtrl",
"register_size" : "32",
"register_type" : "ctrl",
"register_access_mode" : "rw",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"RgbLed1" : 3,
"RgbLed2" : 3,
"Unused" : 26
}
}
]
}
{
"config" : {
"entity_name" : "scalp_safe_firmware_reg_bank",
"entity_version" : "0.1",
"entity_reg_io_access" : true,
"block_name" : "ScalpSafeFirmwareRegBank",
"bd_name" : "/scalp_axi4lite_0/SAXILitexDIO",
"bd_interface" : "SAXILitexDIO",
"bd_slave_segment" : "SAXILiteAddr",
"bd_master_base_address" : "0x43C00000",
"bd_range" : "256"
},
"register_bank" : [
{
"register_status_active" : true,
"register_name" : "RgbLedsCtrl",
"register_size" : "32",
"register_type" : "ctrl",
"register_access_mode" : "rw",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"RgbLed1" : 3,
"RgbLed2" : 3,
"Unused" : 26
}
},
{
"register_status_active" : true,
"register_name" : "Ctrl1",
"register_size" : "32",
"register_type" : "ctrl",
"register_access_mode" : "wo",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"f0" : 1,
"f1" : 1,
"f2" : 30
}
},
{
"register_status_active" : true,
"register_name" : "Status",
"register_size" : "32",
"register_type" : "stat",
"register_access_mode" : "ro",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"f0" : 1,
"f1" : 31
}
},
{
"register_status_active" : true,
"register_name" : "Data1",
"register_size" : "32",
"register_type" : "data",
"register_access_mode" : "rw",
"register_multifield" : false,
"register_initial_value" : 255
}
]
}
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#!/usr/bin/python3
import os
import sys
import getopt
import json
from utils import display_title
from regedit import *
VERSION = "0.1"
# Default directories
def help() :
print("Usage : ")
print("$ python3 regedit_creator <opt>")
print("Option : ")
print("\t-h || --help\tDisplay help")
print("\t-c || --config_file <json_file>\tUse a JSON file for the register bank configuration")
if __name__ == "__main__" :
json_data = None
display_title(" Register Bank Creator v{} ".format(VERSION))
try :
opts, args = getopt.getopt(sys.argv[1:], "hc:", ["help", "config_file="])
except getopt.GetoptError :
help()
sys.exit(-1)
if not opts :
help()
sys.exit(-1)
for opt, arg in opts :
if opt in ("-h", "--help") :
help()
sys.exit()
elif opt in ("-c", "--config_file") :
print("> Load register bank information from " + arg)
with open(arg) as f :
json_data = json.load(f)
# Get config
#if "config" in json_data :
try :
config = json_data["config"]
except KeyError as e :
print("KeyError : {}".format(e))
sys.exit(-1)
try :
entity_name = config["entity_name"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
entity_version = config["entity_version"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
entity_reg_io_access = config["entity_reg_io_access"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
block_name = config["block_name"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
bd_name = config["bd_name"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
bd_interface = config["bd_interface"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
bd_slave_segment = config["bd_slave_segment"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
bd_master_base_address = config["bd_master_base_address"]
except KeyError as e :
print("KeyError : {}".format(e))
try :
bd_range = config["bd_range"]
except KeyError as e :
print("KeyError : {}".format(e))
# Get register bank
try :
register_bank = json_data["register_bank"]
except KeyError as e :
print("KeyError : {}".format(e))
print("#Error - __main__() : the register bank is not defined in the config file...")
sys.exit(-1)
if len(register_bank) == 0 :
print("Error : Empty register bank");
sys.exit(-1)
try :
regedit_prj = regedit_gen(entity_name, entity_version, entity_reg_io_access, block_name,
bd_name, bd_interface, bd_slave_segment, bd_master_base_address,
bd_range, register_bank)
except ValueError as e :
print(e)
else :
ret = regedit_prj.create_dir()
if ret == 0 :
print("\n> " + entity_name + " register bank directory tree successfully created")
ret = regedit_prj.copy_hdl_template_file(entity_name)
-- THIS IS AN AUTOGENERATED FILE. DO NOT EDIT THIS FILE DIRECTLY.
-- scalp_regedit v0.1 - 05.2021
-- Author : Joachim Schmidt <joachim.schmidt@hesge.ch>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity <entity_name> is
generic (
C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
C_AXI4_RDATA_SIZE : integer range 0 to 32 := <data_size>;
C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
C_AXI4_WDATA_SIZE : integer range 0 to 32 := <data_size>;
C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
C_AXI4_ADDR_SIZE : integer range 0 to 32 := <addr_size>;
C_AXI4_DATA_SIZE : integer range 0 to 32 := <data_size>);
port (
-- Clock and reset
SAxiClkxCI : in std_ulogic;
SAxiRstxRANI : in std_ulogic;
-- AXI4 Lite
-- Read Channel
-- Read Address Channel
SAxiARAddrxDI : in std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
SAxiARValidxSI : in std_ulogic;
SAxiARReadyxSO : out std_ulogic;
-- Read Data Channel
SAxiRDataxDO : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
SAxiRRespxDO : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
SAxiRValidxSO : out std_ulogic;
SAxiRReadyxSI : in std_ulogic;
-- Write Channel
-- Write Address Channel
SAxiAWAddrxDI : in std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
SAxiAWValidxSI : in std_ulogic;
SAxiAWReadyxSO : out std_ulogic;
-- Write Data Channel
SAxiWDataxDI : in std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
SAxiWStrbxDI : in std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
SAxiWValidxSI : in std_ulogic;
SAxiWReadyxSO : out std_ulogic;
-- Write Response Channel
SAxiBRespxDO : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
SAxiBValidxSO : out std_ulogic;
SAxiBReadyxSI : in std_ulogic<registers_list_entity_io>);
end <entity_name>;
architecture behavioral of <entity_name> is
-- Constants
constant C_AXI4_RRESP_OKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
constant C_AXI4_BRESP_OKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_BRESP_EXOKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_BRESP_SLVERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_BRESP_DECERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
-- Signals
-- Clock and reset
signal SAxiClkxC : std_ulogic := '0';
signal SAxiRstxRAN : std_ulogic := '0';
-- AXI4 Lite
signal SAxiARReadyxS : std_ulogic := '0';
signal SAxiRValidxS : std_ulogic := '0';
signal SAxiBValidxS : std_ulogic := '0';
signal SAxiWReadyxS : std_ulogic := '0';
signal SAxiAWReadyxS : std_ulogic := '0';
signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- Signals of access to the register bank
signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RdValidxS : std_ulogic := '0';
signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal WrValidxS : std_ulogic := '0';
-- Registers list
<registers_list>
-- Attributes
attribute mark_debug : string;
attribute keep : string;
--
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
begin
assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
report "RDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
report "ARADDR and ADDR vectors must be the same" severity failure;
assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
report "WDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
EntityIOxB : block is
begin -- block EntityIOxB
-- Clock and reset
SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
-- Read Channel
SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
RdValidxAS : RdValidxS <= SAxiARValidxSI;
RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
-- Write Channel
SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
WrValidxAS : WrValidxS <= SAxiWValidxSI;
WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
SAxiAWValidxSI = '1' else
WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
end block EntityIOxB;
AXI4LitexB : block is
begin -- block AXI4LitexB
ReadChannelxB : block is
begin -- block ReadChannelxB
ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
variable StateAfterResetxS : boolean := true;
begin -- process ReadAddrChanxP
if SAxiRstxRAN = '0' then
SAxiARReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxC) then
if StateAfterResetxS = true then
SAxiARReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiARReadyxS <= SAxiARReadyxS;
end if;
if SAxiARValidxSI = '1' then
SAxiARReadyxS <= '0';
end if;
if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
SAxiARReadyxS <= '1';
end if;
end if;
end process ReadAddrChanxP;
ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process ReadDataChanxP
if SAxiRstxRAN = '0' then
SAxiRValidxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiRValidxS <= SAxiRValidxS;
if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
SAxiRValidxS <= '1';
end if;
if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
SAxiRValidxS <= '0';
end if;
end if;
end process ReadDataChanxP;
end block ReadChannelxB;
WriteChannelxB : block is
begin --block WriteChannelxB
WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WrAddrRegxP
if SAxiRstxRAN = '0' then
WrAddrxDP <= (others => '0');
elsif rising_edge(SAxiClkxC) then
WrAddrxDP <= WrAddrxDN;
end if;
end process WrAddrRegxP;
WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
variable StateAfterResetxS : boolean := true;
begin -- process WriteAddrChanxP
if SAxiRstxRAN = '0' then
SAxiAWReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxC) then
if StateAfterResetxS = true then
SAxiAWReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiAWReadyxS <= SAxiAWReadyxS;
end if;
if SAxiAWValidxSI = '1' then
SAxiAWReadyxS <= '0';
end if;
if SAxiWValidxSI = '1' then
SAxiAWReadyxS <= '1';
end if;
end if;
end process WriteAddrChanxP;
WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WriteDataChanxP
if SAxiRstxRAN = '0' then
SAxiWReadyxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiWReadyxS <= SAxiWReadyxS;
if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
SAxiWReadyxS <= '1';
end if;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiWReadyxS <= '0';
end if;
end if;
end process WriteDataChanxP;
WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WriteRespChanxP
if SAxiRstxRAN = '0' then
SAxiBValidxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiBValidxS <= SAxiBValidxS;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiBValidxS <= '1';
end if;
if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
SAxiBValidxS <= '0';
end if;
end if;
end process WriteRespChanxP;
end block WriteChannelxB;
end block AXI4LitexB;
<block_name>xB : block is
begin -- block <block_name>xB
WriteRegPortxP : process (WrAddrxD, WrDataxD, WrValidxS,
<registers_list_current_value>) is
begin -- process WriteRegPortxP
<registers_list_current_to_next>
if WrValidxS = '1' then
case WrAddrxD is
<registers_list_write_access>
when others => null;
end case;
end if;
end process WriteRegPortxP;
ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process ReadRegPortxP
if SAxiRstxRAN = '0' then
RdDataxD <= (others => '0');
elsif rising_edge(SAxiClkxC) then
RdDataxD <= RdDataxD;
if RdValidxS = '1' then
case RdAddrxD is
<registers_list_read_access>
when others => RdDataxD <= (others => '0');
end case;
end if;
end if;
end process ReadRegPortxP;
UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process UpdateRegBankxP
if SAxiRstxRAN = '0' then
<registers_list_init_current_value>
elsif rising_edge(SAxiClkxC) then
<registers_list_next_to_current>
end if;
end process UpdateRegBankxP;
end block <block_name>xB;
end behavioral;
#!/usr/bin/python
import datetime
import re
import os
import shutil
import numpy as np
def display_title(title_str):
print("\n" + ("-" * (len(title_str) + 6)))
print("-- " + title_str + " --")
print(("-" * (len(title_str) + 6)) + "\n")
def get_time_str():
return datetime.datetime.now().strftime("%Y%m%d_%H%M%S")
def file_replace_pattern(file_path, pattern, replace_str):
# create the regex pattern
re_pattern = "(" + pattern + ")"
p = re.compile(re_pattern)
# create a temp file to apply the pattern
temp_file = file_path + "#"
fin = open(file_path, "r")
fout = open(temp_file, "w")
for line in fin.readlines():
# substitute the pattern
fout.write(p.sub(replace_str, line))
# replace the input file by the processed temp file
os.remove(file_path)
shutil.move(temp_file, file_path)
def hex32str(value):
return "{:08X}".format(value)
def hex32str2(value, bd_range):
size = int(np.ceil(int(np.trunc(np.log2(int(bd_range)))) / 4))
fstr = "{:0" + str(size) + "X}"
return fstr.format(value)
def check_key(dict, key) :
if key in dict.keys() :
return True
else :
return False
File added
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