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v0.0.4
188d24d3
·
[Makefile] Avoid ecpprog bug on first memory write
·
Aug 17, 2025
v0.0.3
39369225
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First ex in VHDL: Update README
·
Jun 15, 2025
v0.0.2
f86acb08
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First ex in Verilog: Makefile, add variables
·
Jun 15, 2025
v0.0.1
3fe2f47b
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First ex in Verilog: Complete the README
·
Jun 15, 2025