Bank registry tb: Adapt to new I/0 and test 2 new register

hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd

@@ -42,8 +42,13 @@ architecture Behavioral of tb_hog_build_info_regs is
       rd_valid_i        : in std_logic; -- AXI4-lite R interface, validation
       rd_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
       rd_data_o         : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
+      wr_valid_i        : in std_logic := '0'; -- AXI4-lite W interface, validation
+      wr_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- AXI4-lite W, address
+      wr_data_i         : in std_logic_vector(31 downto 0) := (others => '0'); -- AXI4-lite W, data
       hog_global_date_i : in std_logic_vector(31 downto 0); -- Hog build global date
-      hog_global_time_i : in std_logic_vector(31 downto 0) -- Hog build global time
+      hog_global_time_i : in std_logic_vector(31 downto 0); -- Hog build global time
+      Hog_global_ver_i  : in std_logic_vector(31 downto 0); -- Hog build global version
+      hog_global_sha_i  : in std_logic_vector(31 downto 0) -- Hog build global latest commit SHA
       );
   end component;
 
@@ -60,25 +65,37 @@ architecture Behavioral of tb_hog_build_info_regs is
   -- Registers addresses
   constant GDR_BASEADDR : integer := 0; -- Global date register
   constant GTR_BASEADDR : integer := 4; -- Global time register
+  constant GVR_BASEADDR : integer := 8; -- Global version register
+  constant GSR_BASEADDR : integer := 12; -- Global SHA register
   constant UNK_BASEADDR : integer := 100; -- Unknown register
 
   -- Fake Hog build info
   constant hog_global_date : std_logic_vector(31 downto 0) := X"13032025";
   constant hog_global_time : std_logic_vector(31 downto 0) := X"00123456";
+  constant hog_global_ver  : std_logic_vector(31 downto 0) := X"01020006";
+  constant hog_global_sha  : std_logic_vector(31 downto 0) := X"A98B90F0";
 
   -- AXI4-lite interface bus
   signal rd_valid_s : std_logic := '0';
   signal rd_addr_s  : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
   signal rd_data_s  : std_logic_vector(31 downto 0) := (others => '0');
+  signal wr_valid_s : std_logic := '0';
+  signal wr_addr_s  : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
+  signal wr_data_s  : std_logic_vector(31 downto 0) := (others => '0');
+
 
   -- Hog build info inputs
   signal hog_global_date_s : std_logic_vector(31 downto 0) := (others => '0');
   signal hog_global_time_s : std_logic_vector(31 downto 0) := (others => '0');
+  signal hog_global_ver_s  : std_logic_vector(31 downto 0) := (others => '0');
+  signal hog_global_sha_s  : std_logic_vector(31 downto 0) := (others => '0');
 
   -- Test bench steps
   signal reset_done_s: std_logic := '0';
   signal check_reg_0_data_s: std_logic := '0';
   signal check_reg_1_data_s: std_logic := '0';
+  signal check_reg_2_data_s: std_logic := '0';
+  signal check_reg_3_data_s: std_logic := '0';
   signal check_reg_unk_data_s: std_logic := '0';
 
   procedure request_access_to_reg(
@@ -111,19 +128,26 @@ begin
     generic map (
       C_ADDR_WIDTH => C_ADDR_WIDTH
       )
-  port map (
-    clk_i => clk_s,
-    resetn => resetn_s,
-    rd_valid_i => rd_valid_s,
-    rd_addr_i => rd_addr_s,
-    rd_data_o => rd_data_s,
-    hog_global_date_i => hog_global_date_s,
-    hog_global_time_i => hog_global_time_s
-    );
+    port map (
+      clk_i => clk_s,
+      resetn => resetn_s,
+      rd_valid_i => rd_valid_s,
+      rd_addr_i => rd_addr_s,
+      rd_data_o => rd_data_s,
+      wr_valid_i => wr_valid_s,
+      wr_addr_i => wr_addr_s,
+      wr_data_i => wr_data_s,
+      hog_global_date_i => hog_global_date_s,
+      hog_global_time_i => hog_global_time_s,
+      hog_global_ver_i => hog_global_ver_s,
+      hog_global_sha_i => hog_global_sha_s
+      );
 
   -- Feed the register bank with fake Hog build info
-  hog_global_date_s <=hog_global_date;
-  hog_global_time_s <=hog_global_time;
+  hog_global_date_s <= hog_global_date;
+  hog_global_time_s <= hog_global_time;
+  hog_global_ver_s <= hog_global_ver;
+  hog_global_sha_s <= hog_global_sha;
   
 
   -- Clock generator process
@@ -152,6 +176,12 @@ begin
     
     -- Write the addr of the reg 1, validate it and wait a bit
     request_access_to_reg(GTR_BASEADDR, rd_valid_s, rd_addr_s, check_reg_1_data_s);
+
+    -- Write the addr of the reg 2, validate it and wait a bit
+    request_access_to_reg(GVR_BASEADDR, rd_valid_s, rd_addr_s, check_reg_2_data_s);
+
+    -- Write the addr of the reg 3, validate it and wait a bit
+    request_access_to_reg(GSR_BASEADDR, rd_valid_s, rd_addr_s, check_reg_3_data_s);
     
     -- Write the addr of an unknown reg, validate it and wait a bit
     request_access_to_reg(UNK_BASEADDR, rd_valid_s, rd_addr_s, check_reg_unk_data_s);
@@ -182,6 +212,18 @@ begin
       report ">>> register 1 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
       severity failure;
 
+    -- Check we get register 2 value on data out
+    wait until check_reg_2_data_s = '1';
+    assert rd_data_s = hog_global_ver
+      report ">>> register 1 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+
+    -- Check we get register 3 value on data out
+    wait until check_reg_3_data_s = '1';
+    assert rd_data_s = hog_global_sha
+      report ">>> register 1 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+    
     -- Check we get 0x0 on data out because of unknown register requested
     wait until check_reg_unk_data_s = '1';
     assert rd_data_s = X"00000000"