Periph test-bench: Test if MSB address truncate work (see desc)

When address width is lower than 32 bits (set with generic
C_DATA_WIDTH):
The address transferred from AXI interface to registers bank is
truncated.
The AXI interface will remove MSB so the address received on AXI side
could correspond to an internal register of registers bank

hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd

@@ -83,8 +83,8 @@ architecture Behavioral of tb_axi4lite_hog_build_info is
   -- Resetn signal
   signal resetn_s : std_logic := '1';
 
-  -- Config
-  constant C_ADDR_WIDTH: integer := 32;
+  -- Config the address width
+  constant C_ADDR_WIDTH: integer := 8;
 
   -- Registers addresses
   constant GDR_BASEADDR : integer := 0; -- Global date register
@@ -92,6 +92,8 @@ architecture Behavioral of tb_axi4lite_hog_build_info is
   constant GVR_BASEADDR : integer := 8; -- Global version register
   constant GSR_BASEADDR : integer := 12; -- Global SHA register
   constant UNK_BASEADDR : integer := 14; -- Unknown register
+  constant OOB_BASEADDR: integer := 256; -- Register, 1 bit out of the max
+                                          -- address for 8 bits
 
   -- Fake Hog build info
   constant hog_global_date : std_logic_vector(31 downto 0) := X"13032025";
@@ -155,6 +157,7 @@ architecture Behavioral of tb_axi4lite_hog_build_info is
   signal check_reg_2_data_s   : std_logic := '0';
   signal check_reg_3_data_s   : std_logic := '0';
   signal check_reg_unk_data_s : std_logic := '0';
+  signal check_reg_oob_data_s : std_logic := '0';
   
 begin
 
@@ -239,6 +242,11 @@ begin
     axi4lite_read(UNK_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
     check_reg_unk_data_s <= '1';
 
+    -- Request to read a register 1 bit above the max permitted by address width
+    -- It should be truncated the MSB and read the register 0
+    axi4lite_read(OOB_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
+    check_reg_oob_data_s <= '1';
+
     -- Wait endlessly
     wait;
     
@@ -263,13 +271,13 @@ begin
     -- Check we get register 2 value on data out
     wait until check_reg_2_data_s = '1';
     assert rd_data_s = hog_global_ver
-      report ">>> register 1 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      report ">>> register 2 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
       severity failure;
 
     -- Check we get register 3 value on data out
     wait until check_reg_3_data_s = '1';
     assert rd_data_s = hog_global_sha
-      report ">>> register 1 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      report ">>> register 3 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
       severity failure;
     
     -- Check we get 0x0 on data out because of unknown register requested
@@ -278,6 +286,13 @@ begin
       report ">>> rd_data_s is not at 0x0 when unknown register is requested. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
       severity failure;
 
+    -- Check the MSB truncate work and by requesting 1 bit above max address,
+    -- we got the register 0 value
+    wait until check_reg_oob_data_s = '1';
+    assert rd_data_s = hog_global_date
+      report ">>> after truncate MSB in address to get 0x0, value get from registers bank do not correspond to the value of register 0. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+
     -- If arrive here, the simulation have completed successfully
     wait for CLK_PERIOD * 10;
     report ">>> Simulation completed successfully";