axi4lite_hog_build_info entity: Remove non-necessary registry I/O in ports

hog-build-info/hog-build-info.srcs/sources_1/new/axi4lite_hog_build_info.vhd

@@ -12,6 +12,8 @@
 -- 
 -- Dependencies:
 --   - axi4lite_if
+--     - axi4lite_wr_channel_if
+--     - axi4lite_rd_channel_if
 --   - hog_build_info_regs
 -- 
 -- Revision:
@@ -52,14 +54,6 @@ entity axi4lite_hog_build_info is
     s_axi_rresp   : out std_logic_vector(1 downto 0);
     s_axi_rvalid  : out std_logic;
     s_axi_rready  : in  std_logic;
-    -- Write register interface
-    wr_valid_o    : out std_logic;
-    wr_addr_o     : out std_logic_vector((C_ADDR_WIDTH - 1) downto 0);
-    wr_data_o     : out std_logic_vector(31 downto 0);
-    -- Read register interface
-    rd_valid_o    : out std_logic;
-    rd_addr_o     : out std_logic_vector((C_ADDR_WIDTH - 1) downto 0);
-    rd_data_i     : in  std_logic_vector(31 downto 0);
     -- Hog build info interface
     hog_global_date_i : in std_logic_vector(31 downto 0); -- Hog build global date
     hog_global_time_i : in std_logic_vector(31 downto 0); -- Hog build global time
@@ -158,7 +152,7 @@ begin
   -- AXI4Lite interface
   -----------------------------------------------------------------------------
 
-  axi4lite_if_inst : entity work.axi4lite_if
+  axi4lite_if_inst : axi4lite_if
     generic map (
       C_ADDR_WIDTH => C_ADDR_WIDTH,
       C_DATA_WIDTH => C_DATA_WIDTH
@@ -200,7 +194,7 @@ begin
   -- Register bank
   -----------------------------------------------------------------------------
 
-  hog_build_info_regs_inst : entity hog_build_info_regs
+  hog_build_info_regs_inst : hog_build_info_regs
     generic map (
       C_ADDR_WIDTH => C_ADDR_WIDTH
       )
@@ -227,6 +221,6 @@ begin
   -----------------------------------------------------------------------------
 
   clk_s <= s_axi_aclk;
-  resetn_i <= s_axi_aresetn;
+  resetn_s <= s_axi_aresetn;
   
 end Behavioral;