Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
hog-build-info-register
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Travail semestre SG
hog-build-info-register
Compare revisions
4a9267e120cfb7ea7fbd7e0fb9ceaa09ba5e9221 to 8c95253525f71733482e38baf466264119a4b120
Compare revisions
Changes are shown as if the
source
revision was being merged into the
target
revision.
Learn more about comparing revisions.
Source
travail-semestre-sg/hog-build-info-register
Select target project
No results found
8c95253525f71733482e38baf466264119a4b120
Select Git revision
Swap
Target
travail-semestre-sg/hog-build-info-register
Select target project
travail-semestre-sg/hog-build-info-register
1 result
4a9267e120cfb7ea7fbd7e0fb9ceaa09ba5e9221
Select Git revision
Show changes
Only incoming changes from source
Include changes to target since source was created
Compare
Commits on Source (2)
hog_build_info_regs: Small fixes and move code wrongly placed at first
· 771c9706
sebastie.gendre
authored
2 months ago
771c9706
Hog list files: hog_build_info_regs have been renamed
· 8c952535
sebastie.gendre
authored
2 months ago
8c952535
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
Top/hog-build-info/list/xil_defaultlib.src
+1
-1
1 addition, 1 deletion
Top/hog-build-info/list/xil_defaultlib.src
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
+12
-11
12 additions, 11 deletions
...hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
with
13 additions
and
12 deletions
Top/hog-build-info/list/xil_defaultlib.src
View file @
8c952535
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_reg.vhd top=hog_build_info_reg 93
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_reg
s
.vhd top=hog_build_info_reg 93
This diff is collapsed.
Click to expand it.
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
View file @
8c952535
...
...
@@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity
hog_build_info_reg
is
generic
(
C_ADDR_WIDTH
:
integer
:
=
32
;
-- Width of the addresses
C_ADDR_WIDTH
:
integer
:
=
32
-- Width of the addresses
);
port
(
...
...
@@ -38,28 +38,30 @@ entity hog_build_info_reg is
);
end
hog_build_info_reg
;
architecture
Behavioral
of
hog_build_info_reg
is
-- Register map
--
-- Global date register (GDR) @ 0x00 - R
-- Date of last commit when the project was modified.
-- [31 - 0] Date in hexa, with digits in format: ddmmyyyy
signal
global_date_reg
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
global_date_reg
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
-- Global time register (GTR) @ 0x00 - R
-- Time of last commit when the project was modified.
-- [31 - 0] Time in hexa, with digits in format: 00HHMMSS
signal
global_time_reg
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
signal
global_time_reg
:
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
-- Registers addresses
constant
GDR_BASEADDR
:
integer
:
=
0
;
-- Global date register
constant
GTR_BASEADDR
:
integer
:
=
0
;
-- Global time register
constant
GDR_BASEADDR
:
integer
:
=
0
;
-- Global date register
constant
GTR_BASEADDR
:
integer
:
=
0
;
-- Global time register
-- Read address integer
signal
rd_addr_s
:
integer
:
=
0
;
signal
rd_addr_s
:
integer
:
=
0
;
-- Read data
signal
rd_data_s
:
std_logic_vector
(
31
downto
0
);
architecture
Behavioral
of
hog_build_info_reg
is
signal
rd_data_s
:
std_logic_vector
(
31
downto
0
);
begin
-- Convert the read address to an integer
rd_addr_s
<=
to_integer
(
unsigned
(
rd_addr_i
));
...
...
@@ -104,6 +106,5 @@ architecture Behavioral of hog_build_info_reg is
-- Global Time register
global_time_reg
<=
hog_global_time_i
;
begin
end
Behavioral
;
This diff is collapsed.
Click to expand it.