Skip to content
Snippets Groups Projects

Compare revisions

Changes are shown as if the source revision was being merged into the target revision. Learn more about comparing revisions.

Source

Select target project
No results found
Select Git revision

Target

Select target project
  • travail-semestre-sg/hog-build-info-register
1 result
Select Git revision
Show changes
Commits on Source (2)
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_reg.vhd top=hog_build_info_reg 93
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd top=hog_build_info_reg 93
......@@ -24,7 +24,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity hog_build_info_reg is
generic (
C_ADDR_WIDTH: integer :=32; -- Width of the addresses
C_ADDR_WIDTH: integer := 32 -- Width of the addresses
);
port (
......@@ -38,28 +38,30 @@ entity hog_build_info_reg is
);
end hog_build_info_reg;
architecture Behavioral of hog_build_info_reg is
-- Register map
--
-- Global date register (GDR) @ 0x00 - R
-- Date of last commit when the project was modified.
-- [31 - 0] Date in hexa, with digits in format: ddmmyyyy
signal global_date_reg : std_logic_vector(31 downto 0) := (others => '0');
signal global_date_reg : std_logic_vector(31 downto 0) := (others => '0');
-- Global time register (GTR) @ 0x00 - R
-- Time of last commit when the project was modified.
-- [31 - 0] Time in hexa, with digits in format: 00HHMMSS
signal global_time_reg : std_logic_vector(31 downto 0) := (others => '0');
signal global_time_reg : std_logic_vector(31 downto 0) := (others => '0');
-- Registers addresses
constant GDR_BASEADDR : integer := 0; -- Global date register
constant GTR_BASEADDR : integer := 0; -- Global time register
constant GDR_BASEADDR : integer := 0; -- Global date register
constant GTR_BASEADDR : integer := 0; -- Global time register
-- Read address integer
signal rd_addr_s : integer :=0;
signal rd_addr_s : integer := 0;
-- Read data
signal rd_data_s : std_logic_vector(31 downto 0);
architecture Behavioral of hog_build_info_reg is
signal rd_data_s : std_logic_vector(31 downto 0);
begin
-- Convert the read address to an integer
rd_addr_s <= to_integer(unsigned(rd_addr_i));
......@@ -104,6 +106,5 @@ architecture Behavioral of hog_build_info_reg is
-- Global Time register
global_time_reg <= hog_global_time_i;
begin
end Behavioral;