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Travail semestre SG
hog-build-info-register
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93b8a638f0894f23b1a4635ae2daca3e7a3cd01b to 5b058ef3a17ec301974ba054753afad26542e8a7
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Commits on Source (2)
Register bank: Add input for write channel
· a1cfa2cc
sebastie.gendre
authored
1 month ago
a1cfa2cc
Update list file about top design entity
· 5b058ef3
sebastie.gendre
authored
1 month ago
5b058ef3
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Top/hog-build-info/list/xil_defaultlib.src
+1
-1
1 addition, 1 deletion
Top/hog-build-info/list/xil_defaultlib.src
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
+3
-0
3 additions, 0 deletions
...hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
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1 deletion
Top/hog-build-info/list/xil_defaultlib.src
View file @
5b058ef3
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd top=hog_build_info_reg 93
hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd top=hog_build_info_reg
s
93
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hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd
View file @
5b058ef3
...
...
@@ -34,6 +34,9 @@ entity hog_build_info_regs is
rd_valid_i
:
in
std_logic
;
-- AXI4-lite R interface, validation
rd_addr_i
:
in
std_logic_vector
(
C_ADDR_WIDTH
-1
downto
0
);
-- AXI4-lite R, address
rd_data_o
:
out
std_logic_vector
(
31
downto
0
);
-- AXI4-lite R, data
wr_valid_i
:
in
std_logic
:
=
'0'
;
-- AXI4-lite W interface, validation
wr_addr_i
:
in
std_logic_vector
(
C_ADDR_WIDTH
-1
downto
0
)
:
=
(
others
=>
'0'
);
-- AXI4-lite W, address
wr_data_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
-- AXI4-lite W, data
hog_global_date_i
:
in
std_logic_vector
(
31
downto
0
);
-- Hog build global date
hog_global_time_i
:
in
std_logic_vector
(
31
downto
0
)
-- Hog build global time
);
...
...
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