Top/hog-build-info/sim.conf

@@ -2,3 +2,6 @@
 ACTIVE=1
 TOP=explore_build_info
 
+[generics]
+BANANA=01234567
+

hog-build-info/hog-build-info.srcs/sim_1/new/explore_build_info.vhd

@@ -30,7 +30,8 @@ entity explore_build_info is
     GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
     GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
     GLOBAL_VER  : std_logic_vector(31 downto 0) := (others => '0');
-    GLOBAL_SHA  : std_logic_vector(31 downto 0) := (others => '0')
+    GLOBAL_SHA  : std_logic_vector(31 downto 0) := (others => '0');
+    BANANA      : integer := 0
     );
 end explore_build_info;
 
@@ -54,4 +55,8 @@ begin
     report "GLOBAL_SHA: " & to_hstring(to_bitvector(GLOBAL_SHA))
     severity note;
 
+  assert false
+    report "BANANA: " & integer'image(BANANA)
+    severity note;
+
 end Behavioral;

hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_reg.vhd

-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 03/10/2025 06:56:35 AM
--- Design Name: 
--- Module Name: hog_build_info_reg - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity hog_build_info_reg is
-  Generic (
-    -- Global Generic Variables
-    GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
-    GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
-    GLOBAL_VER  : std_logic_vector(31 downto 0) := (others => '0');
-    GLOBAL_SHA  : std_logic_vector(31 downto 0) := (others => '0')
-    );
---  Port ( );
-end hog_build_info_reg;
-
-architecture Behavioral of hog_build_info_reg is
-
-begin
-
-
-end Behavioral;

hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/10/2025 06:56:35 AM
+-- Design Name: 
+-- Module Name: hog_build_info_reg - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity hog_build_info_reg is
+  generic (
+    C_ADDR_WIDTH: integer :=32;   -- Width of the addresses
+    );
+  
+  port (
+    clk_i             : in std_logic; -- Clock in
+    resetn            : in std_logic; -- Reset in
+    rd_valid_i        : in std_logic; -- AXI4-lite R interface, validation
+    rd_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
+    rd_data_o         : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
+    hog_global_date_i : in std_logic_vector(31 downto 0); -- Hog build global date
+    hog_global_time_i : in std_logic_vector(31 downto 0) -- Hog build global time
+    );
+end hog_build_info_reg;
+
+-- Register map
+--
+-- Global date register (GDR) @ 0x00 - R
+--     Date of last commit when the project was modified.
+--     [31 - 0] Date in hexa, with digits in format: ddmmyyyy
+signal global_date_reg : std_logic_vector(31 downto 0) := (others => '0');
+
+-- Global time register (GTR) @ 0x00 - R
+--     Time of last commit when the project was modified.
+--     [31 - 0] Time in hexa, with digits in format: 00HHMMSS
+signal global_time_reg : std_logic_vector(31 downto 0) := (others => '0');
+
+-- Registers addresses
+constant GDR_BASEADDR : integer := 0; -- Global date register
+constant GTR_BASEADDR : integer := 0; -- Global time register
+
+-- Read address integer
+signal rd_addr_s : integer :=0;
+-- Read data
+signal rd_data_s : std_logic_vector(31 downto 0);
+
+architecture Behavioral of hog_build_info_reg is
+
+  -- Convert the read address to an integer
+  rd_addr_s <= to_integer(unsigned(rd_addr_i));
+
+  -- Read of register process
+  rd_regigters_proc: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if resetn = '0' then
+        -- If reset, set data read to 0x00
+        rd_data_s <= (others => '0');
+      else
+        rd_data_s <= rd_data_s;
+
+        if rd_valid_i = '1' then
+          -- If read address validated
+
+          -- Read the requested register
+          case rd_addr_s is
+            -- GDR requested
+            when GDR_BASEADDR =>
+              rd_data_s <= global_date_reg;
+            -- GDR requested
+            when GTR_BASEADDR =>
+              rd_data_s <= global_time_reg;
+            -- Unknown register, return 0x0
+            when others =>
+              rd_data_s <= (others => '0');
+          end case;
+        end if;
+      end if;
+    end if;
+  end process rd_regigters_proc;
+
+  -- Connect read data signal to output
+  rd_data_o <= rd_data_s;
+
+  -- Map I/0 to the registers
+  -- Global Date register
+  global_date_reg <= hog_global_date_i;
+
+  -- Global Time register
+  global_time_reg <= hog_global_time_i;
+
+begin
+
+end Behavioral;