Finishing the work on this repo

Hog @ 174bb0ee

-Subproject commit 219f277c25177b595e925e639bf63aacb72b1608
+Subproject commit 174bb0ee8a9689aacbb2e0f817d339a2a31e01a4

Labo1B/tb_test.vhd

@@ -19,8 +19,8 @@ begin
   monitor_process: process
   begin
     -- Uncomment the line you want to apply
-    assert false
-      report "Test of error"
+    assert true
+      report ">> Simulation SUCCESS:"
       severity failure;
 
     -- Wait endlessly

Top/labo1b/hog.conf

@@ -7,4 +7,3 @@ TARGET_LANGUAGE=Verilog
 
 [impl_1]
 STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1
-

Top/labo1b/list/sim_1.sim

+#Simulator xsim
+
 Labo1B/tb_test.vhd 93 lib=xil_defaultlib

Top/labo1b/sim.conf

@@ -2,3 +2,6 @@
 ACTIVE=1
 TOP=dummy_test
 
+[hog]
+HOG_SIMPASS_STR=">> Simulation SUCCESS:"
+