Add an ILA to debug Time and Date build info and AXI to my periph

....gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd

...o.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh

..._hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml

...mb_design_1/ip/mb_design_1_system_ila_0_0/bd_0/bd_477d.bd

..._design_1/ip/mb_design_1_system_ila_0_0/bd_0/bd_477d.bxml

...sign_1/ip/mb_design_1_system_ila_0_0/bd_0/bd_477d_ooc.xdc

...p/mb_design_1_system_ila_0_0/bd_0/hdl/bd_477d_wrapper.vhd

...em_ila_0_0/bd_0/hw_handoff/mb_design_1_system_ila_0_0.hwh

...esign_1_system_ila_0_0/bd_0/ip/ip_0/bd_477d_ila_lib_0.xci

...esign_1_system_ila_0_0/bd_0/ip/ip_0/bd_477d_ila_lib_0.xml

...n_1_system_ila_0_0/bd_0/ip/ip_0/bd_477d_ila_lib_0_ooc.xdc

..._system_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila.xdc

...em_ila_0_0/bd_0/ip/ip_0/ila_v6_2/constraints/ila_impl.xdc

...n_1_system_ila_0_0/bd_0/ip/ip_0/sim/bd_477d_ila_lib_0.vhd

...1_system_ila_0_0/bd_0/ip/ip_0/synth/bd_477d_ila_lib_0.vhd

...design_1_system_ila_0_0/bd_0/ip/ip_1/bd_477d_g_inst_0.xci

...design_1_system_ila_0_0/bd_0/ip/ip_1/bd_477d_g_inst_0.xml

...stem_ila_0_0/bd_0/ip/ip_1/bd_477d_g_inst_0_gigantic_mux.v

...sign_1_system_ila_0_0/bd_0/ip/ip_1/sim/bd_477d_g_inst_0.v

...gn_1_system_ila_0_0/bd_0/ip/ip_1/synth/bd_477d_g_inst_0.v