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  • travail-semestre-sg/microblaze-demo
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Top/microblaze-demo/list/sim_1.sim
View file @ c10d4808
Projects/microblaze-demo/microblaze-demo.srcs/sim_1/new/dummy_simu.vhd 93 lib=xil_defaultlib
Top/microblaze-demo/sim.conf
View file @ c10d4808
[sim_1]
ACTIVE=1
TOP=mb_design_1_wrapper
TOP=dummy_simu
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hw_handoff/mb_design_1.hwh deleted 100644 → 0
View file @ e55b3b4a
Source diff could not be displayed: it is too large. Options to address this: view the blob.
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
View file @ c10d4808
......@@ -378,7 +378,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
......@@ -516,7 +516,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
......@@ -559,101 +559,6 @@
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>axi4lite_hog_build_info</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:216bf9af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:modelName>axi4lite_hog_build_info</spirit:modelName>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:12918eb6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Mar 20 16:31:20 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:12918eb6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:12918eb6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsimulationwrapper</spirit:name>
<spirit:displayName>VHDL Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>mb_design_1_axi4lite_hog_build_i_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:216bf9af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>mb_design_1_axi4lite_hog_build_i_0_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Mar 20 17:24:29 UTC 2025</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:12918eb6</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>s_axi_aclk</spirit:name>
......@@ -662,8 +567,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -675,8 +579,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -692,8 +595,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -708,8 +610,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -724,8 +625,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -741,8 +641,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -761,8 +660,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -777,8 +675,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -793,8 +690,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -810,8 +706,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -823,8 +718,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -836,8 +730,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -856,8 +749,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -872,8 +764,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -888,8 +779,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -905,8 +795,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -922,8 +811,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -935,8 +823,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -948,8 +835,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
......@@ -968,8 +854,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -985,8 +870,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -1002,8 +886,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -1019,8 +902,7 @@
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
......@@ -1030,7 +912,7 @@
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>C_ADDR_WIDTH</spirit:name>
<spirit:displayName>C Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDR_WIDTH">32</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ADDR_WIDTH">8</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
......@@ -1041,66 +923,12 @@
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>mb_design_1_axi4lite_hog_build_i_0_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>xilinx.com:module_ref:axi4lite_hog_build_info:1.0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_ADDR_WIDTH</spirit:name>
<spirit:displayName>C Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_WIDTH">32</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ADDR_WIDTH">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
......
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v deleted 100644 → 0
View file @ e55b3b4a
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
// Date : Thu Mar 20 18:25:04 2025
// Host : hogtest running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.v
// Design : mb_design_1_axi4lite_hog_build_i_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_definition_source = "module_ref" *)
(* x_core_info = "axi4lite_hog_build_info,Vivado 2024.1.2" *)
(* NotValidForBitStream *)
module mb_design_1_axi4lite_hog_build_i_0_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
hog_global_date_i,
hog_global_time_i,
hog_global_ver_i,
hog_global_sha_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [31:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
input [31:0]hog_global_date_i;
input [31:0]hog_global_time_i;
input [31:0]hog_global_ver_i;
input [31:0]hog_global_sha_i;
wire \<const0> ;
wire [31:0]hog_global_date_i;
wire [31:0]hog_global_sha_i;
wire [31:0]hog_global_time_i;
wire [31:0]hog_global_ver_i;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info U0
(.hog_global_date_i(hog_global_date_i),
.hog_global_sha_i(hog_global_sha_i),
.hog_global_time_i(hog_global_time_i),
.hog_global_ver_i(hog_global_ver_i),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready_s_reg(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi4lite_hog_build_info" *)
module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info
(s_axi_wready,
s_axi_awready,
s_axi_rdata,
s_axi_arready_s_reg,
s_axi_bvalid,
s_axi_rvalid,
s_axi_aclk,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_aresetn,
s_axi_arvalid,
s_axi_araddr,
hog_global_ver_i,
hog_global_sha_i,
hog_global_date_i,
hog_global_time_i,
s_axi_bready);
output s_axi_wready;
output s_axi_awready;
output [31:0]s_axi_rdata;
output s_axi_arready_s_reg;
output s_axi_bvalid;
output s_axi_rvalid;
input s_axi_aclk;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_aresetn;
input s_axi_arvalid;
input [31:0]s_axi_araddr;
input [31:0]hog_global_ver_i;
input [31:0]hog_global_sha_i;
input [31:0]hog_global_date_i;
input [31:0]hog_global_time_i;
input s_axi_bready;
wire [31:0]hog_global_date_i;
wire [31:0]hog_global_sha_i;
wire [31:0]hog_global_time_i;
wire [31:0]hog_global_ver_i;
wire p_0_in;
wire [31:0]p_1_in;
wire rd_valid_s;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready_s_reg;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if axi4lite_if_inst
(.D(p_1_in),
.E(rd_valid_s),
.SR(p_0_in),
.hog_global_date_i(hog_global_date_i),
.hog_global_sha_i(hog_global_sha_i),
.hog_global_time_i(hog_global_time_i),
.hog_global_ver_i(hog_global_ver_i),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready_s_reg(s_axi_arready_s_reg),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs hog_build_info_regs_inst
(.D(p_1_in),
.E(rd_valid_s),
.SR(p_0_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_rdata(s_axi_rdata));
endmodule
(* ORIG_REF_NAME = "axi4lite_if" *)
module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if
(s_axi_wready,
SR,
s_axi_awready,
s_axi_bvalid,
s_axi_arready_s_reg,
s_axi_rvalid,
D,
E,
s_axi_aclk,
s_axi_wvalid,
s_axi_bready,
s_axi_awvalid,
s_axi_arvalid,
s_axi_rready,
s_axi_aresetn,
s_axi_araddr,
hog_global_ver_i,
hog_global_sha_i,
hog_global_date_i,
hog_global_time_i);
output s_axi_wready;
output [0:0]SR;
output s_axi_awready;
output s_axi_bvalid;
output s_axi_arready_s_reg;
output s_axi_rvalid;
output [31:0]D;
output [0:0]E;
input s_axi_aclk;
input s_axi_wvalid;
input s_axi_bready;
input s_axi_awvalid;
input s_axi_arvalid;
input s_axi_rready;
input s_axi_aresetn;
input [31:0]s_axi_araddr;
input [31:0]hog_global_ver_i;
input [31:0]hog_global_sha_i;
input [31:0]hog_global_date_i;
input [31:0]hog_global_time_i;
wire [31:0]D;
wire [0:0]E;
wire [0:0]SR;
wire [31:0]hog_global_date_i;
wire [31:0]hog_global_sha_i;
wire [31:0]hog_global_time_i;
wire [31:0]hog_global_ver_i;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready_s_reg;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if axi4lite_rd_channel_if_i
(.D(D),
.E(E),
.hog_global_date_i(hog_global_date_i),
.hog_global_sha_i(hog_global_sha_i),
.hog_global_time_i(hog_global_time_i),
.hog_global_ver_i(hog_global_ver_i),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(SR),
.s_axi_arready_s_reg_0(s_axi_arready_s_reg),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if axi4lite_wr_channel_if_i
(.s_axi_aclk(s_axi_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awready_s_reg_0(SR),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi4lite_rd_channel_if" *)
module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if
(s_axi_aresetn_0,
s_axi_arready_s_reg_0,
s_axi_rvalid,
D,
E,
s_axi_aclk,
s_axi_arvalid,
s_axi_rready,
s_axi_aresetn,
s_axi_araddr,
hog_global_ver_i,
hog_global_sha_i,
hog_global_date_i,
hog_global_time_i);
output s_axi_aresetn_0;
output s_axi_arready_s_reg_0;
output s_axi_rvalid;
output [31:0]D;
output [0:0]E;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_rready;
input s_axi_aresetn;
input [31:0]s_axi_araddr;
input [31:0]hog_global_ver_i;
input [31:0]hog_global_sha_i;
input [31:0]hog_global_date_i;
input [31:0]hog_global_time_i;
wire [31:0]D;
wire [0:0]E;
wire [31:0]addr_s;
wire \addr_s[0]_i_1_n_0 ;
wire \addr_s[10]_i_1_n_0 ;
wire \addr_s[11]_i_1_n_0 ;
wire \addr_s[12]_i_1_n_0 ;
wire \addr_s[13]_i_1_n_0 ;
wire \addr_s[14]_i_1_n_0 ;
wire \addr_s[15]_i_1_n_0 ;
wire \addr_s[16]_i_1_n_0 ;
wire \addr_s[17]_i_1_n_0 ;
wire \addr_s[18]_i_1_n_0 ;
wire \addr_s[19]_i_1_n_0 ;
wire \addr_s[1]_i_1_n_0 ;
wire \addr_s[20]_i_1_n_0 ;
wire \addr_s[21]_i_1_n_0 ;
wire \addr_s[22]_i_1_n_0 ;
wire \addr_s[23]_i_1_n_0 ;
wire \addr_s[24]_i_1_n_0 ;
wire \addr_s[25]_i_1_n_0 ;
wire \addr_s[26]_i_1_n_0 ;
wire \addr_s[27]_i_1_n_0 ;
wire \addr_s[28]_i_1_n_0 ;
wire \addr_s[29]_i_1_n_0 ;
wire \addr_s[2]_i_1_n_0 ;
wire \addr_s[30]_i_1_n_0 ;
wire \addr_s[31]_i_1_n_0 ;
wire \addr_s[3]_i_1_n_0 ;
wire \addr_s[4]_i_1_n_0 ;
wire \addr_s[5]_i_1_n_0 ;
wire \addr_s[6]_i_1_n_0 ;
wire \addr_s[7]_i_1_n_0 ;
wire \addr_s[8]_i_1_n_0 ;
wire \addr_s[9]_i_1_n_0 ;
wire [31:0]hog_global_date_i;
wire [31:0]hog_global_sha_i;
wire [31:0]hog_global_time_i;
wire [31:0]hog_global_ver_i;
wire rd_addr_latched;
wire rd_addr_latched_i_1_n_0;
wire \rd_data_s[0]_i_2_n_0 ;
wire \rd_data_s[10]_i_2_n_0 ;
wire \rd_data_s[11]_i_2_n_0 ;
wire \rd_data_s[12]_i_2_n_0 ;
wire \rd_data_s[13]_i_2_n_0 ;
wire \rd_data_s[14]_i_2_n_0 ;
wire \rd_data_s[15]_i_2_n_0 ;
wire \rd_data_s[16]_i_2_n_0 ;
wire \rd_data_s[17]_i_2_n_0 ;
wire \rd_data_s[18]_i_2_n_0 ;
wire \rd_data_s[19]_i_2_n_0 ;
wire \rd_data_s[1]_i_2_n_0 ;
wire \rd_data_s[20]_i_2_n_0 ;
wire \rd_data_s[21]_i_2_n_0 ;
wire \rd_data_s[22]_i_2_n_0 ;
wire \rd_data_s[23]_i_2_n_0 ;
wire \rd_data_s[24]_i_2_n_0 ;
wire \rd_data_s[25]_i_2_n_0 ;
wire \rd_data_s[26]_i_2_n_0 ;
wire \rd_data_s[27]_i_2_n_0 ;
wire \rd_data_s[28]_i_2_n_0 ;
wire \rd_data_s[29]_i_2_n_0 ;
wire \rd_data_s[2]_i_2_n_0 ;
wire \rd_data_s[30]_i_2_n_0 ;
wire \rd_data_s[31]_i_10_n_0 ;
wire \rd_data_s[31]_i_11_n_0 ;
wire \rd_data_s[31]_i_12_n_0 ;
wire \rd_data_s[31]_i_13_n_0 ;
wire \rd_data_s[31]_i_14_n_0 ;
wire \rd_data_s[31]_i_15_n_0 ;
wire \rd_data_s[31]_i_16_n_0 ;
wire \rd_data_s[31]_i_17_n_0 ;
wire \rd_data_s[31]_i_18_n_0 ;
wire \rd_data_s[31]_i_19_n_0 ;
wire \rd_data_s[31]_i_20_n_0 ;
wire \rd_data_s[31]_i_21_n_0 ;
wire \rd_data_s[31]_i_22_n_0 ;
wire \rd_data_s[31]_i_3_n_0 ;
wire \rd_data_s[31]_i_4_n_0 ;
wire \rd_data_s[31]_i_5_n_0 ;
wire \rd_data_s[31]_i_6_n_0 ;
wire \rd_data_s[31]_i_7_n_0 ;
wire \rd_data_s[31]_i_8_n_0 ;
wire \rd_data_s[31]_i_9_n_0 ;
wire \rd_data_s[3]_i_2_n_0 ;
wire \rd_data_s[4]_i_2_n_0 ;
wire \rd_data_s[5]_i_2_n_0 ;
wire \rd_data_s[6]_i_2_n_0 ;
wire \rd_data_s[7]_i_2_n_0 ;
wire \rd_data_s[8]_i_2_n_0 ;
wire \rd_data_s[9]_i_2_n_0 ;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire s_axi_arready_s_i_1_n_0;
wire s_axi_arready_s_reg_0;
wire s_axi_arvalid;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_s_i_1_n_0;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hEA2A))
\addr_s[0]_i_1
(.I0(addr_s[0]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[0]),
.O(\addr_s[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[10]_i_1
(.I0(addr_s[10]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[10]),
.O(\addr_s[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[11]_i_1
(.I0(addr_s[11]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[11]),
.O(\addr_s[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[12]_i_1
(.I0(addr_s[12]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[12]),
.O(\addr_s[12]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[13]_i_1
(.I0(addr_s[13]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[13]),
.O(\addr_s[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[14]_i_1
(.I0(addr_s[14]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[14]),
.O(\addr_s[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[15]_i_1
(.I0(addr_s[15]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[15]),
.O(\addr_s[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[16]_i_1
(.I0(addr_s[16]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[16]),
.O(\addr_s[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[17]_i_1
(.I0(addr_s[17]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[17]),
.O(\addr_s[17]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[18]_i_1
(.I0(addr_s[18]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[18]),
.O(\addr_s[18]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[19]_i_1
(.I0(addr_s[19]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[19]),
.O(\addr_s[19]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[1]_i_1
(.I0(addr_s[1]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[1]),
.O(\addr_s[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[20]_i_1
(.I0(addr_s[20]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[20]),
.O(\addr_s[20]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[21]_i_1
(.I0(addr_s[21]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[21]),
.O(\addr_s[21]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[22]_i_1
(.I0(addr_s[22]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[22]),
.O(\addr_s[22]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[23]_i_1
(.I0(addr_s[23]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[23]),
.O(\addr_s[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[24]_i_1
(.I0(addr_s[24]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[24]),
.O(\addr_s[24]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[25]_i_1
(.I0(addr_s[25]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[25]),
.O(\addr_s[25]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[26]_i_1
(.I0(addr_s[26]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[26]),
.O(\addr_s[26]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[27]_i_1
(.I0(addr_s[27]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[27]),
.O(\addr_s[27]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[28]_i_1
(.I0(addr_s[28]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[28]),
.O(\addr_s[28]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[29]_i_1
(.I0(addr_s[29]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[29]),
.O(\addr_s[29]_i_1_n_0 ));
LUT4 #(
.INIT(16'hBF80))
\addr_s[2]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(s_axi_arready_s_reg_0),
.I3(addr_s[2]),
.O(\addr_s[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'hBF80))
\addr_s[30]_i_1
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid),
.I2(s_axi_arready_s_reg_0),
.I3(addr_s[30]),
.O(\addr_s[30]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[31]_i_1
(.I0(addr_s[31]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[31]),
.O(\addr_s[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[3]_i_1
(.I0(addr_s[3]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[3]),
.O(\addr_s[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[4]_i_1
(.I0(addr_s[4]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[4]),
.O(\addr_s[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[5]_i_1
(.I0(addr_s[5]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[5]),
.O(\addr_s[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[6]_i_1
(.I0(addr_s[6]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[6]),
.O(\addr_s[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[7]_i_1
(.I0(addr_s[7]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[7]),
.O(\addr_s[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[8]_i_1
(.I0(addr_s[8]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[8]),
.O(\addr_s[8]_i_1_n_0 ));
LUT4 #(
.INIT(16'hEA2A))
\addr_s[9]_i_1
(.I0(addr_s[9]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[9]),
.O(\addr_s[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\addr_s_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[0]_i_1_n_0 ),
.Q(addr_s[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[10]_i_1_n_0 ),
.Q(addr_s[10]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[11]_i_1_n_0 ),
.Q(addr_s[11]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[12]_i_1_n_0 ),
.Q(addr_s[12]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[13]_i_1_n_0 ),
.Q(addr_s[13]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[14]_i_1_n_0 ),
.Q(addr_s[14]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[15]_i_1_n_0 ),
.Q(addr_s[15]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[16]_i_1_n_0 ),
.Q(addr_s[16]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[17]_i_1_n_0 ),
.Q(addr_s[17]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[18]_i_1_n_0 ),
.Q(addr_s[18]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[19]_i_1_n_0 ),
.Q(addr_s[19]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[1]_i_1_n_0 ),
.Q(addr_s[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[20]_i_1_n_0 ),
.Q(addr_s[20]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[21]_i_1_n_0 ),
.Q(addr_s[21]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[22]_i_1_n_0 ),
.Q(addr_s[22]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[23]_i_1_n_0 ),
.Q(addr_s[23]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[24]_i_1_n_0 ),
.Q(addr_s[24]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[25]_i_1_n_0 ),
.Q(addr_s[25]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[26]_i_1_n_0 ),
.Q(addr_s[26]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[27]_i_1_n_0 ),
.Q(addr_s[27]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[28]_i_1_n_0 ),
.Q(addr_s[28]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[29]_i_1_n_0 ),
.Q(addr_s[29]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[2]_i_1_n_0 ),
.Q(addr_s[2]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[30]_i_1_n_0 ),
.Q(addr_s[30]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[31]_i_1_n_0 ),
.Q(addr_s[31]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[3]_i_1_n_0 ),
.Q(addr_s[3]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[4]_i_1_n_0 ),
.Q(addr_s[4]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[5]_i_1_n_0 ),
.Q(addr_s[5]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[6]_i_1_n_0 ),
.Q(addr_s[6]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[7]_i_1_n_0 ),
.Q(addr_s[7]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[8]_i_1_n_0 ),
.Q(addr_s[8]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\addr_s_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\addr_s[9]_i_1_n_0 ),
.Q(addr_s[9]),
.R(s_axi_aresetn_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hEFAA))
rd_addr_latched_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_rready),
.I3(rd_addr_latched),
.O(rd_addr_latched_i_1_n_0));
FDRE #(
.INIT(1'b0))
rd_addr_latched_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_addr_latched_i_1_n_0),
.Q(rd_addr_latched),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[0]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[0]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[0]_i_2
(.I0(hog_global_ver_i[0]),
.I1(hog_global_sha_i[0]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[0]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[0]),
.O(\rd_data_s[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[10]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[10]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[10]_i_2
(.I0(hog_global_ver_i[10]),
.I1(hog_global_sha_i[10]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[10]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[10]),
.O(\rd_data_s[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[11]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[11]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[11]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[11]_i_2
(.I0(hog_global_ver_i[11]),
.I1(hog_global_sha_i[11]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[11]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[11]),
.O(\rd_data_s[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[12]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[12]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[12]_i_2
(.I0(hog_global_ver_i[12]),
.I1(hog_global_sha_i[12]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[12]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[12]),
.O(\rd_data_s[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[13]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[13]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[13]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[13]_i_2
(.I0(hog_global_ver_i[13]),
.I1(hog_global_sha_i[13]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[13]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[13]),
.O(\rd_data_s[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[14]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[14]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[14]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[14]_i_2
(.I0(hog_global_ver_i[14]),
.I1(hog_global_sha_i[14]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[14]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[14]),
.O(\rd_data_s[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[15]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[15]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[15]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[15]_i_2
(.I0(hog_global_ver_i[15]),
.I1(hog_global_sha_i[15]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[15]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[15]),
.O(\rd_data_s[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[16]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[16]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[16]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[16]_i_2
(.I0(hog_global_ver_i[16]),
.I1(hog_global_sha_i[16]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[16]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[16]),
.O(\rd_data_s[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[17]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[17]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[17]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[17]_i_2
(.I0(hog_global_ver_i[17]),
.I1(hog_global_sha_i[17]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[17]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[17]),
.O(\rd_data_s[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[18]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[18]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[18]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[18]_i_2
(.I0(hog_global_ver_i[18]),
.I1(hog_global_sha_i[18]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[18]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[18]),
.O(\rd_data_s[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[19]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[19]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[19]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[19]_i_2
(.I0(hog_global_ver_i[19]),
.I1(hog_global_sha_i[19]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[19]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[19]),
.O(\rd_data_s[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[1]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[1]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[1]_i_2
(.I0(hog_global_ver_i[1]),
.I1(hog_global_sha_i[1]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[1]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[1]),
.O(\rd_data_s[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[20]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[20]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[20]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[20]_i_2
(.I0(hog_global_ver_i[20]),
.I1(hog_global_sha_i[20]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[20]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[20]),
.O(\rd_data_s[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[21]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[21]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[21]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[21]_i_2
(.I0(hog_global_ver_i[21]),
.I1(hog_global_sha_i[21]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[21]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[21]),
.O(\rd_data_s[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[22]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[22]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[22]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[22]_i_2
(.I0(hog_global_ver_i[22]),
.I1(hog_global_sha_i[22]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[22]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[22]),
.O(\rd_data_s[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[23]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[23]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[23]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[23]_i_2
(.I0(hog_global_ver_i[23]),
.I1(hog_global_sha_i[23]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[23]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[23]),
.O(\rd_data_s[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[24]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[24]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[24]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[24]_i_2
(.I0(hog_global_ver_i[24]),
.I1(hog_global_sha_i[24]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[24]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[24]),
.O(\rd_data_s[24]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[25]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[25]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[25]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[25]_i_2
(.I0(hog_global_ver_i[25]),
.I1(hog_global_sha_i[25]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[25]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[25]),
.O(\rd_data_s[25]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[26]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[26]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[26]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[26]_i_2
(.I0(hog_global_ver_i[26]),
.I1(hog_global_sha_i[26]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[26]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[26]),
.O(\rd_data_s[26]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[27]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[27]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[27]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[27]_i_2
(.I0(hog_global_ver_i[27]),
.I1(hog_global_sha_i[27]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[27]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[27]),
.O(\rd_data_s[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[28]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[28]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[28]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[28]_i_2
(.I0(hog_global_ver_i[28]),
.I1(hog_global_sha_i[28]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[28]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[28]),
.O(\rd_data_s[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[29]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[29]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[29]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[29]_i_2
(.I0(hog_global_ver_i[29]),
.I1(hog_global_sha_i[29]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[29]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[29]),
.O(\rd_data_s[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[2]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[2]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[2]_i_2
(.I0(hog_global_ver_i[2]),
.I1(hog_global_sha_i[2]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[2]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[2]),
.O(\rd_data_s[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[30]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[30]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[30]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[30]_i_2
(.I0(hog_global_ver_i[30]),
.I1(hog_global_sha_i[30]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[30]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[30]),
.O(\rd_data_s[30]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
\rd_data_s[31]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_arready_s_reg_0),
.O(E));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_10
(.I0(s_axi_araddr[18]),
.I1(addr_s[18]),
.I2(s_axi_araddr[17]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[17]),
.O(\rd_data_s[31]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_11
(.I0(s_axi_araddr[14]),
.I1(addr_s[14]),
.I2(s_axi_araddr[13]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[13]),
.O(\rd_data_s[31]_i_11_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_12
(.I0(s_axi_araddr[27]),
.I1(addr_s[27]),
.I2(s_axi_araddr[24]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[24]),
.O(\rd_data_s[31]_i_12_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_13
(.I0(s_axi_araddr[7]),
.I1(addr_s[7]),
.I2(s_axi_araddr[6]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[6]),
.O(\rd_data_s[31]_i_13_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_14
(.I0(s_axi_araddr[23]),
.I1(addr_s[23]),
.I2(s_axi_araddr[5]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[5]),
.O(\rd_data_s[31]_i_14_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_15
(.I0(s_axi_araddr[22]),
.I1(addr_s[22]),
.I2(s_axi_araddr[4]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[4]),
.O(\rd_data_s[31]_i_15_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_16
(.I0(s_axi_araddr[31]),
.I1(addr_s[31]),
.I2(s_axi_araddr[20]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[20]),
.O(\rd_data_s[31]_i_16_n_0 ));
LUT6 #(
.INIT(64'h0500000005333333))
\rd_data_s[31]_i_17
(.I0(s_axi_araddr[30]),
.I1(addr_s[30]),
.I2(s_axi_araddr[21]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[21]),
.O(\rd_data_s[31]_i_17_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_18
(.I0(s_axi_araddr[26]),
.I1(addr_s[26]),
.I2(s_axi_araddr[25]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[25]),
.O(\rd_data_s[31]_i_18_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_19
(.I0(s_axi_araddr[11]),
.I1(addr_s[11]),
.I2(s_axi_araddr[8]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[8]),
.O(\rd_data_s[31]_i_19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[31]_i_2
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[31]_i_7_n_0 ),
.I5(\rd_data_s[31]_i_8_n_0 ),
.O(D[31]));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_20
(.I0(s_axi_araddr[10]),
.I1(addr_s[10]),
.I2(s_axi_araddr[9]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[9]),
.O(\rd_data_s[31]_i_20_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_21
(.I0(s_axi_araddr[29]),
.I1(addr_s[29]),
.I2(s_axi_araddr[28]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[28]),
.O(\rd_data_s[31]_i_21_n_0 ));
LUT4 #(
.INIT(16'h15D5))
\rd_data_s[31]_i_22
(.I0(addr_s[2]),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_arvalid),
.I3(s_axi_araddr[2]),
.O(\rd_data_s[31]_i_22_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFBBFCB8))
\rd_data_s[31]_i_3
(.I0(addr_s[16]),
.I1(\rd_data_s[31]_i_9_n_0 ),
.I2(s_axi_araddr[16]),
.I3(addr_s[19]),
.I4(s_axi_araddr[19]),
.I5(\rd_data_s[31]_i_10_n_0 ),
.O(\rd_data_s[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFBBFCB8))
\rd_data_s[31]_i_4
(.I0(addr_s[12]),
.I1(\rd_data_s[31]_i_9_n_0 ),
.I2(s_axi_araddr[12]),
.I3(addr_s[15]),
.I4(s_axi_araddr[15]),
.I5(\rd_data_s[31]_i_11_n_0 ),
.O(\rd_data_s[31]_i_4_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\rd_data_s[31]_i_5
(.I0(\rd_data_s[31]_i_12_n_0 ),
.I1(\rd_data_s[31]_i_13_n_0 ),
.I2(\rd_data_s[31]_i_14_n_0 ),
.I3(\rd_data_s[31]_i_15_n_0 ),
.O(\rd_data_s[31]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\rd_data_s[31]_i_6
(.I0(\rd_data_s[31]_i_16_n_0 ),
.I1(\rd_data_s[31]_i_17_n_0 ),
.I2(\rd_data_s[31]_i_18_n_0 ),
.I3(\rd_data_s[31]_i_19_n_0 ),
.I4(\rd_data_s[31]_i_20_n_0 ),
.I5(\rd_data_s[31]_i_21_n_0 ),
.O(\rd_data_s[31]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFAFFFFFFFACCCCCC))
\rd_data_s[31]_i_7
(.I0(s_axi_araddr[1]),
.I1(addr_s[1]),
.I2(s_axi_araddr[0]),
.I3(s_axi_arvalid),
.I4(s_axi_arready_s_reg_0),
.I5(addr_s[0]),
.O(\rd_data_s[31]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[31]_i_8
(.I0(hog_global_ver_i[31]),
.I1(hog_global_sha_i[31]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[31]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[31]),
.O(\rd_data_s[31]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h7))
\rd_data_s[31]_i_9
(.I0(s_axi_arready_s_reg_0),
.I1(s_axi_arvalid),
.O(\rd_data_s[31]_i_9_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[3]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[3]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[3]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[3]_i_2
(.I0(hog_global_ver_i[3]),
.I1(hog_global_sha_i[3]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[3]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[3]),
.O(\rd_data_s[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[4]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[4]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[4]_i_2
(.I0(hog_global_ver_i[4]),
.I1(hog_global_sha_i[4]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[4]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[4]),
.O(\rd_data_s[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[5]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[5]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[5]_i_2
(.I0(hog_global_ver_i[5]),
.I1(hog_global_sha_i[5]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[5]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[5]),
.O(\rd_data_s[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[6]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[6]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[6]_i_2
(.I0(hog_global_ver_i[6]),
.I1(hog_global_sha_i[6]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[6]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[6]),
.O(\rd_data_s[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[7]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[7]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[7]_i_2
(.I0(hog_global_ver_i[7]),
.I1(hog_global_sha_i[7]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[7]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[7]),
.O(\rd_data_s[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[8]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[8]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[8]_i_2
(.I0(hog_global_ver_i[8]),
.I1(hog_global_sha_i[8]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[8]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[8]),
.O(\rd_data_s[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\rd_data_s[9]_i_1
(.I0(\rd_data_s[31]_i_3_n_0 ),
.I1(\rd_data_s[31]_i_4_n_0 ),
.I2(\rd_data_s[31]_i_5_n_0 ),
.I3(\rd_data_s[31]_i_6_n_0 ),
.I4(\rd_data_s[9]_i_2_n_0 ),
.I5(\rd_data_s[31]_i_7_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\rd_data_s[9]_i_2
(.I0(hog_global_ver_i[9]),
.I1(hog_global_sha_i[9]),
.I2(\addr_s[3]_i_1_n_0 ),
.I3(hog_global_date_i[9]),
.I4(\rd_data_s[31]_i_22_n_0 ),
.I5(hog_global_time_i[9]),
.O(\rd_data_s[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00004F00))
s_axi_arready_s_i_1
(.I0(s_axi_arready_s_reg_0),
.I1(s_axi_rready),
.I2(rd_addr_latched),
.I3(s_axi_aresetn),
.I4(s_axi_arvalid),
.O(s_axi_arready_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_arready_s_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_arready_s_i_1_n_0),
.Q(s_axi_arready_s_reg_0),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
s_axi_awready_s_i_1
(.I0(s_axi_aresetn),
.O(s_axi_aresetn_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h88F8))
s_axi_rvalid_s_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_arready_s_reg_0),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.O(s_axi_rvalid_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_s_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_s_i_1_n_0),
.Q(s_axi_rvalid),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "axi4lite_wr_channel_if" *)
module mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if
(s_axi_wready,
s_axi_awready,
s_axi_bvalid,
s_axi_awready_s_reg_0,
s_axi_aclk,
s_axi_wvalid,
s_axi_bready,
s_axi_awvalid);
output s_axi_wready;
output s_axi_awready;
output s_axi_bvalid;
input s_axi_awready_s_reg_0;
input s_axi_aclk;
input s_axi_wvalid;
input s_axi_bready;
input s_axi_awvalid;
wire aw_en_i_1_n_0;
wire aw_en_reg_n_0;
wire s_axi_aclk;
wire s_axi_awready;
wire s_axi_awready_s0__0;
wire s_axi_awready_s_reg_0;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_s_i_1_n_0;
wire s_axi_wready;
wire s_axi_wready_s0;
wire s_axi_wvalid;
LUT5 #(
.INIT(32'h7F2A2A2A))
aw_en_i_1
(.I0(aw_en_reg_n_0),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(aw_en_i_1_n_0));
FDSE #(
.INIT(1'b0))
aw_en_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(aw_en_i_1_n_0),
.Q(aw_en_reg_n_0),
.S(s_axi_awready_s_reg_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
s_axi_awready_s0
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(aw_en_reg_n_0),
.O(s_axi_awready_s0__0));
FDRE #(
.INIT(1'b0))
s_axi_awready_s_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_awready_s0__0),
.Q(s_axi_awready),
.R(s_axi_awready_s_reg_0));
LUT4 #(
.INIT(16'h8F88))
s_axi_bvalid_s_i_1
(.I0(s_axi_wready),
.I1(s_axi_wvalid),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_axi_bvalid_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_s_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_s_i_1_n_0),
.Q(s_axi_bvalid),
.R(s_axi_awready_s_reg_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0080))
s_axi_wready_s_i_1
(.I0(aw_en_reg_n_0),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(s_axi_wready),
.O(s_axi_wready_s0));
FDRE #(
.INIT(1'b0))
s_axi_wready_s_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_wready_s0),
.Q(s_axi_wready),
.R(s_axi_awready_s_reg_0));
endmodule
(* ORIG_REF_NAME = "hog_build_info_regs" *)
module mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs
(s_axi_rdata,
SR,
E,
D,
s_axi_aclk);
output [31:0]s_axi_rdata;
input [0:0]SR;
input [0:0]E;
input [31:0]D;
input s_axi_aclk;
wire [31:0]D;
wire [0:0]E;
wire [0:0]SR;
wire s_axi_aclk;
wire [31:0]s_axi_rdata;
FDRE \rd_data_s_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE \rd_data_s_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(D[10]),
.Q(s_axi_rdata[10]),
.R(SR));
FDRE \rd_data_s_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(D[11]),
.Q(s_axi_rdata[11]),
.R(SR));
FDRE \rd_data_s_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(D[12]),
.Q(s_axi_rdata[12]),
.R(SR));
FDRE \rd_data_s_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(D[13]),
.Q(s_axi_rdata[13]),
.R(SR));
FDRE \rd_data_s_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(D[14]),
.Q(s_axi_rdata[14]),
.R(SR));
FDRE \rd_data_s_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(D[15]),
.Q(s_axi_rdata[15]),
.R(SR));
FDRE \rd_data_s_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(D[16]),
.Q(s_axi_rdata[16]),
.R(SR));
FDRE \rd_data_s_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(D[17]),
.Q(s_axi_rdata[17]),
.R(SR));
FDRE \rd_data_s_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(D[18]),
.Q(s_axi_rdata[18]),
.R(SR));
FDRE \rd_data_s_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(D[19]),
.Q(s_axi_rdata[19]),
.R(SR));
FDRE \rd_data_s_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE \rd_data_s_reg[20]
(.C(s_axi_aclk),
.CE(E),
.D(D[20]),
.Q(s_axi_rdata[20]),
.R(SR));
FDRE \rd_data_s_reg[21]
(.C(s_axi_aclk),
.CE(E),
.D(D[21]),
.Q(s_axi_rdata[21]),
.R(SR));
FDRE \rd_data_s_reg[22]
(.C(s_axi_aclk),
.CE(E),
.D(D[22]),
.Q(s_axi_rdata[22]),
.R(SR));
FDRE \rd_data_s_reg[23]
(.C(s_axi_aclk),
.CE(E),
.D(D[23]),
.Q(s_axi_rdata[23]),
.R(SR));
FDRE \rd_data_s_reg[24]
(.C(s_axi_aclk),
.CE(E),
.D(D[24]),
.Q(s_axi_rdata[24]),
.R(SR));
FDRE \rd_data_s_reg[25]
(.C(s_axi_aclk),
.CE(E),
.D(D[25]),
.Q(s_axi_rdata[25]),
.R(SR));
FDRE \rd_data_s_reg[26]
(.C(s_axi_aclk),
.CE(E),
.D(D[26]),
.Q(s_axi_rdata[26]),
.R(SR));
FDRE \rd_data_s_reg[27]
(.C(s_axi_aclk),
.CE(E),
.D(D[27]),
.Q(s_axi_rdata[27]),
.R(SR));
FDRE \rd_data_s_reg[28]
(.C(s_axi_aclk),
.CE(E),
.D(D[28]),
.Q(s_axi_rdata[28]),
.R(SR));
FDRE \rd_data_s_reg[29]
(.C(s_axi_aclk),
.CE(E),
.D(D[29]),
.Q(s_axi_rdata[29]),
.R(SR));
FDRE \rd_data_s_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE \rd_data_s_reg[30]
(.C(s_axi_aclk),
.CE(E),
.D(D[30]),
.Q(s_axi_rdata[30]),
.R(SR));
FDRE \rd_data_s_reg[31]
(.C(s_axi_aclk),
.CE(E),
.D(D[31]),
.Q(s_axi_rdata[31]),
.R(SR));
FDRE \rd_data_s_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE \rd_data_s_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE \rd_data_s_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(D[5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE \rd_data_s_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(D[6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE \rd_data_s_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(D[7]),
.Q(s_axi_rdata[7]),
.R(SR));
FDRE \rd_data_s_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(D[8]),
.Q(s_axi_rdata[8]),
.R(SR));
FDRE \rd_data_s_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(D[9]),
.Q(s_axi_rdata[9]),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl deleted 100644 → 0
View file @ e55b3b4a
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-- Date : Thu Mar 20 18:25:04 2025
-- Host : hogtest running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_sim_netlist.vhdl
-- Design : mb_design_1_axi4lite_hog_build_i_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if is
port (
s_axi_aresetn_0 : out STD_LOGIC;
s_axi_arready_s_reg_0 : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if : entity is "axi4lite_rd_channel_if";
end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if;
architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if is
signal addr_s : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \addr_s[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[13]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[14]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[15]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[16]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[17]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[18]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[19]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[20]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[21]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[22]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[23]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[24]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[25]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[26]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[27]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[28]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[29]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[30]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[31]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_s[9]_i_1_n_0\ : STD_LOGIC;
signal rd_addr_latched : STD_LOGIC;
signal rd_addr_latched_i_1_n_0 : STD_LOGIC;
signal \rd_data_s[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[10]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[11]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[12]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[13]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[14]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[15]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[16]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[17]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[18]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[19]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[1]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[20]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[21]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[22]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[23]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[24]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[25]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[26]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[27]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[28]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[29]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[30]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_10_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_11_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_12_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_13_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_14_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_15_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_16_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_17_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_18_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_19_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_20_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_21_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_22_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_7_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_8_n_0\ : STD_LOGIC;
signal \rd_data_s[31]_i_9_n_0\ : STD_LOGIC;
signal \rd_data_s[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[4]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[5]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[6]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[8]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_s[9]_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_aresetn_0\ : STD_LOGIC;
signal s_axi_arready_s_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready_s_reg_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_s_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \addr_s[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of rd_addr_latched_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rd_data_s[31]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rd_data_s[31]_i_9\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_axi_arready_s_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_rvalid_s_i_1 : label is "soft_lutpair1";
begin
s_axi_aresetn_0 <= \^s_axi_aresetn_0\;
s_axi_arready_s_reg_0 <= \^s_axi_arready_s_reg_0\;
s_axi_rvalid <= \^s_axi_rvalid\;
\addr_s[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(0),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(0),
O => \addr_s[0]_i_1_n_0\
);
\addr_s[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(10),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(10),
O => \addr_s[10]_i_1_n_0\
);
\addr_s[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(11),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(11),
O => \addr_s[11]_i_1_n_0\
);
\addr_s[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(12),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(12),
O => \addr_s[12]_i_1_n_0\
);
\addr_s[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(13),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(13),
O => \addr_s[13]_i_1_n_0\
);
\addr_s[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(14),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(14),
O => \addr_s[14]_i_1_n_0\
);
\addr_s[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(15),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(15),
O => \addr_s[15]_i_1_n_0\
);
\addr_s[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(16),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(16),
O => \addr_s[16]_i_1_n_0\
);
\addr_s[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(17),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(17),
O => \addr_s[17]_i_1_n_0\
);
\addr_s[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(18),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(18),
O => \addr_s[18]_i_1_n_0\
);
\addr_s[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(19),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(19),
O => \addr_s[19]_i_1_n_0\
);
\addr_s[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(1),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(1),
O => \addr_s[1]_i_1_n_0\
);
\addr_s[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(20),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(20),
O => \addr_s[20]_i_1_n_0\
);
\addr_s[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(21),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(21),
O => \addr_s[21]_i_1_n_0\
);
\addr_s[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(22),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(22),
O => \addr_s[22]_i_1_n_0\
);
\addr_s[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(23),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(23),
O => \addr_s[23]_i_1_n_0\
);
\addr_s[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(24),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(24),
O => \addr_s[24]_i_1_n_0\
);
\addr_s[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(25),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(25),
O => \addr_s[25]_i_1_n_0\
);
\addr_s[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(26),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(26),
O => \addr_s[26]_i_1_n_0\
);
\addr_s[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(27),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(27),
O => \addr_s[27]_i_1_n_0\
);
\addr_s[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(28),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(28),
O => \addr_s[28]_i_1_n_0\
);
\addr_s[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(29),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(29),
O => \addr_s[29]_i_1_n_0\
);
\addr_s[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => \^s_axi_arready_s_reg_0\,
I3 => addr_s(2),
O => \addr_s[2]_i_1_n_0\
);
\addr_s[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid,
I2 => \^s_axi_arready_s_reg_0\,
I3 => addr_s(30),
O => \addr_s[30]_i_1_n_0\
);
\addr_s[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(31),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(31),
O => \addr_s[31]_i_1_n_0\
);
\addr_s[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(3),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(3),
O => \addr_s[3]_i_1_n_0\
);
\addr_s[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(4),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(4),
O => \addr_s[4]_i_1_n_0\
);
\addr_s[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(5),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(5),
O => \addr_s[5]_i_1_n_0\
);
\addr_s[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(6),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(6),
O => \addr_s[6]_i_1_n_0\
);
\addr_s[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(7),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(7),
O => \addr_s[7]_i_1_n_0\
);
\addr_s[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(8),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(8),
O => \addr_s[8]_i_1_n_0\
);
\addr_s[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA2A"
)
port map (
I0 => addr_s(9),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(9),
O => \addr_s[9]_i_1_n_0\
);
\addr_s_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[0]_i_1_n_0\,
Q => addr_s(0),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[10]_i_1_n_0\,
Q => addr_s(10),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[11]_i_1_n_0\,
Q => addr_s(11),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[12]_i_1_n_0\,
Q => addr_s(12),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[13]_i_1_n_0\,
Q => addr_s(13),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[14]_i_1_n_0\,
Q => addr_s(14),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[15]_i_1_n_0\,
Q => addr_s(15),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[16]_i_1_n_0\,
Q => addr_s(16),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[17]_i_1_n_0\,
Q => addr_s(17),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[18]_i_1_n_0\,
Q => addr_s(18),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[19]_i_1_n_0\,
Q => addr_s(19),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[1]_i_1_n_0\,
Q => addr_s(1),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[20]_i_1_n_0\,
Q => addr_s(20),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[21]_i_1_n_0\,
Q => addr_s(21),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[22]_i_1_n_0\,
Q => addr_s(22),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[23]_i_1_n_0\,
Q => addr_s(23),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[24]_i_1_n_0\,
Q => addr_s(24),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[25]_i_1_n_0\,
Q => addr_s(25),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[26]_i_1_n_0\,
Q => addr_s(26),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[27]_i_1_n_0\,
Q => addr_s(27),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[28]_i_1_n_0\,
Q => addr_s(28),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[29]_i_1_n_0\,
Q => addr_s(29),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[2]_i_1_n_0\,
Q => addr_s(2),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[30]_i_1_n_0\,
Q => addr_s(30),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[31]_i_1_n_0\,
Q => addr_s(31),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[3]_i_1_n_0\,
Q => addr_s(3),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[4]_i_1_n_0\,
Q => addr_s(4),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[5]_i_1_n_0\,
Q => addr_s(5),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[6]_i_1_n_0\,
Q => addr_s(6),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[7]_i_1_n_0\,
Q => addr_s(7),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[8]_i_1_n_0\,
Q => addr_s(8),
R => \^s_axi_aresetn_0\
);
\addr_s_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \addr_s[9]_i_1_n_0\,
Q => addr_s(9),
R => \^s_axi_aresetn_0\
);
rd_addr_latched_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFAA"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_rready,
I3 => rd_addr_latched,
O => rd_addr_latched_i_1_n_0
);
rd_addr_latched_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_addr_latched_i_1_n_0,
Q => rd_addr_latched,
R => \^s_axi_aresetn_0\
);
\rd_data_s[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[0]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(0)
);
\rd_data_s[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(0),
I1 => hog_global_sha_i(0),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(0),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(0),
O => \rd_data_s[0]_i_2_n_0\
);
\rd_data_s[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[10]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(10)
);
\rd_data_s[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(10),
I1 => hog_global_sha_i(10),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(10),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(10),
O => \rd_data_s[10]_i_2_n_0\
);
\rd_data_s[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[11]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(11)
);
\rd_data_s[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(11),
I1 => hog_global_sha_i(11),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(11),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(11),
O => \rd_data_s[11]_i_2_n_0\
);
\rd_data_s[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[12]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(12)
);
\rd_data_s[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(12),
I1 => hog_global_sha_i(12),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(12),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(12),
O => \rd_data_s[12]_i_2_n_0\
);
\rd_data_s[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[13]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(13)
);
\rd_data_s[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(13),
I1 => hog_global_sha_i(13),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(13),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(13),
O => \rd_data_s[13]_i_2_n_0\
);
\rd_data_s[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[14]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(14)
);
\rd_data_s[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(14),
I1 => hog_global_sha_i(14),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(14),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(14),
O => \rd_data_s[14]_i_2_n_0\
);
\rd_data_s[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[15]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(15)
);
\rd_data_s[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(15),
I1 => hog_global_sha_i(15),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(15),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(15),
O => \rd_data_s[15]_i_2_n_0\
);
\rd_data_s[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[16]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(16)
);
\rd_data_s[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(16),
I1 => hog_global_sha_i(16),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(16),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(16),
O => \rd_data_s[16]_i_2_n_0\
);
\rd_data_s[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[17]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(17)
);
\rd_data_s[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(17),
I1 => hog_global_sha_i(17),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(17),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(17),
O => \rd_data_s[17]_i_2_n_0\
);
\rd_data_s[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[18]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(18)
);
\rd_data_s[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(18),
I1 => hog_global_sha_i(18),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(18),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(18),
O => \rd_data_s[18]_i_2_n_0\
);
\rd_data_s[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[19]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(19)
);
\rd_data_s[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(19),
I1 => hog_global_sha_i(19),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(19),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(19),
O => \rd_data_s[19]_i_2_n_0\
);
\rd_data_s[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[1]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(1)
);
\rd_data_s[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(1),
I1 => hog_global_sha_i(1),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(1),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(1),
O => \rd_data_s[1]_i_2_n_0\
);
\rd_data_s[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[20]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(20)
);
\rd_data_s[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(20),
I1 => hog_global_sha_i(20),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(20),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(20),
O => \rd_data_s[20]_i_2_n_0\
);
\rd_data_s[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[21]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(21)
);
\rd_data_s[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(21),
I1 => hog_global_sha_i(21),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(21),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(21),
O => \rd_data_s[21]_i_2_n_0\
);
\rd_data_s[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[22]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(22)
);
\rd_data_s[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(22),
I1 => hog_global_sha_i(22),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(22),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(22),
O => \rd_data_s[22]_i_2_n_0\
);
\rd_data_s[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[23]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(23)
);
\rd_data_s[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(23),
I1 => hog_global_sha_i(23),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(23),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(23),
O => \rd_data_s[23]_i_2_n_0\
);
\rd_data_s[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[24]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(24)
);
\rd_data_s[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(24),
I1 => hog_global_sha_i(24),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(24),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(24),
O => \rd_data_s[24]_i_2_n_0\
);
\rd_data_s[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[25]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(25)
);
\rd_data_s[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(25),
I1 => hog_global_sha_i(25),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(25),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(25),
O => \rd_data_s[25]_i_2_n_0\
);
\rd_data_s[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[26]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(26)
);
\rd_data_s[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(26),
I1 => hog_global_sha_i(26),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(26),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(26),
O => \rd_data_s[26]_i_2_n_0\
);
\rd_data_s[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[27]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(27)
);
\rd_data_s[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(27),
I1 => hog_global_sha_i(27),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(27),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(27),
O => \rd_data_s[27]_i_2_n_0\
);
\rd_data_s[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[28]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(28)
);
\rd_data_s[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(28),
I1 => hog_global_sha_i(28),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(28),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(28),
O => \rd_data_s[28]_i_2_n_0\
);
\rd_data_s[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[29]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(29)
);
\rd_data_s[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(29),
I1 => hog_global_sha_i(29),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(29),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(29),
O => \rd_data_s[29]_i_2_n_0\
);
\rd_data_s[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[2]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(2)
);
\rd_data_s[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(2),
I1 => hog_global_sha_i(2),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(2),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(2),
O => \rd_data_s[2]_i_2_n_0\
);
\rd_data_s[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[30]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(30)
);
\rd_data_s[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(30),
I1 => hog_global_sha_i(30),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(30),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(30),
O => \rd_data_s[30]_i_2_n_0\
);
\rd_data_s[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready_s_reg_0\,
O => E(0)
);
\rd_data_s[31]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(18),
I1 => addr_s(18),
I2 => s_axi_araddr(17),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(17),
O => \rd_data_s[31]_i_10_n_0\
);
\rd_data_s[31]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(14),
I1 => addr_s(14),
I2 => s_axi_araddr(13),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(13),
O => \rd_data_s[31]_i_11_n_0\
);
\rd_data_s[31]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(27),
I1 => addr_s(27),
I2 => s_axi_araddr(24),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(24),
O => \rd_data_s[31]_i_12_n_0\
);
\rd_data_s[31]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(7),
I1 => addr_s(7),
I2 => s_axi_araddr(6),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(6),
O => \rd_data_s[31]_i_13_n_0\
);
\rd_data_s[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(23),
I1 => addr_s(23),
I2 => s_axi_araddr(5),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(5),
O => \rd_data_s[31]_i_14_n_0\
);
\rd_data_s[31]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(22),
I1 => addr_s(22),
I2 => s_axi_araddr(4),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(4),
O => \rd_data_s[31]_i_15_n_0\
);
\rd_data_s[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(31),
I1 => addr_s(31),
I2 => s_axi_araddr(20),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(20),
O => \rd_data_s[31]_i_16_n_0\
);
\rd_data_s[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0500000005333333"
)
port map (
I0 => s_axi_araddr(30),
I1 => addr_s(30),
I2 => s_axi_araddr(21),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(21),
O => \rd_data_s[31]_i_17_n_0\
);
\rd_data_s[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(26),
I1 => addr_s(26),
I2 => s_axi_araddr(25),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(25),
O => \rd_data_s[31]_i_18_n_0\
);
\rd_data_s[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(11),
I1 => addr_s(11),
I2 => s_axi_araddr(8),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(8),
O => \rd_data_s[31]_i_19_n_0\
);
\rd_data_s[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[31]_i_7_n_0\,
I5 => \rd_data_s[31]_i_8_n_0\,
O => D(31)
);
\rd_data_s[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(10),
I1 => addr_s(10),
I2 => s_axi_araddr(9),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(9),
O => \rd_data_s[31]_i_20_n_0\
);
\rd_data_s[31]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(29),
I1 => addr_s(29),
I2 => s_axi_araddr(28),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(28),
O => \rd_data_s[31]_i_21_n_0\
);
\rd_data_s[31]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"15D5"
)
port map (
I0 => addr_s(2),
I1 => \^s_axi_arready_s_reg_0\,
I2 => s_axi_arvalid,
I3 => s_axi_araddr(2),
O => \rd_data_s[31]_i_22_n_0\
);
\rd_data_s[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => addr_s(16),
I1 => \rd_data_s[31]_i_9_n_0\,
I2 => s_axi_araddr(16),
I3 => addr_s(19),
I4 => s_axi_araddr(19),
I5 => \rd_data_s[31]_i_10_n_0\,
O => \rd_data_s[31]_i_3_n_0\
);
\rd_data_s[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => addr_s(12),
I1 => \rd_data_s[31]_i_9_n_0\,
I2 => s_axi_araddr(12),
I3 => addr_s(15),
I4 => s_axi_araddr(15),
I5 => \rd_data_s[31]_i_11_n_0\,
O => \rd_data_s[31]_i_4_n_0\
);
\rd_data_s[31]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \rd_data_s[31]_i_12_n_0\,
I1 => \rd_data_s[31]_i_13_n_0\,
I2 => \rd_data_s[31]_i_14_n_0\,
I3 => \rd_data_s[31]_i_15_n_0\,
O => \rd_data_s[31]_i_5_n_0\
);
\rd_data_s[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \rd_data_s[31]_i_16_n_0\,
I1 => \rd_data_s[31]_i_17_n_0\,
I2 => \rd_data_s[31]_i_18_n_0\,
I3 => \rd_data_s[31]_i_19_n_0\,
I4 => \rd_data_s[31]_i_20_n_0\,
I5 => \rd_data_s[31]_i_21_n_0\,
O => \rd_data_s[31]_i_6_n_0\
);
\rd_data_s[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFACCCCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => addr_s(1),
I2 => s_axi_araddr(0),
I3 => s_axi_arvalid,
I4 => \^s_axi_arready_s_reg_0\,
I5 => addr_s(0),
O => \rd_data_s[31]_i_7_n_0\
);
\rd_data_s[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(31),
I1 => hog_global_sha_i(31),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(31),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(31),
O => \rd_data_s[31]_i_8_n_0\
);
\rd_data_s[31]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^s_axi_arready_s_reg_0\,
I1 => s_axi_arvalid,
O => \rd_data_s[31]_i_9_n_0\
);
\rd_data_s[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[3]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(3)
);
\rd_data_s[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(3),
I1 => hog_global_sha_i(3),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(3),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(3),
O => \rd_data_s[3]_i_2_n_0\
);
\rd_data_s[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[4]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(4)
);
\rd_data_s[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(4),
I1 => hog_global_sha_i(4),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(4),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(4),
O => \rd_data_s[4]_i_2_n_0\
);
\rd_data_s[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[5]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(5)
);
\rd_data_s[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(5),
I1 => hog_global_sha_i(5),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(5),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(5),
O => \rd_data_s[5]_i_2_n_0\
);
\rd_data_s[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[6]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(6)
);
\rd_data_s[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(6),
I1 => hog_global_sha_i(6),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(6),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(6),
O => \rd_data_s[6]_i_2_n_0\
);
\rd_data_s[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[7]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(7)
);
\rd_data_s[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(7),
I1 => hog_global_sha_i(7),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(7),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(7),
O => \rd_data_s[7]_i_2_n_0\
);
\rd_data_s[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[8]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(8)
);
\rd_data_s[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(8),
I1 => hog_global_sha_i(8),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(8),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(8),
O => \rd_data_s[8]_i_2_n_0\
);
\rd_data_s[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \rd_data_s[31]_i_3_n_0\,
I1 => \rd_data_s[31]_i_4_n_0\,
I2 => \rd_data_s[31]_i_5_n_0\,
I3 => \rd_data_s[31]_i_6_n_0\,
I4 => \rd_data_s[9]_i_2_n_0\,
I5 => \rd_data_s[31]_i_7_n_0\,
O => D(9)
);
\rd_data_s[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => hog_global_ver_i(9),
I1 => hog_global_sha_i(9),
I2 => \addr_s[3]_i_1_n_0\,
I3 => hog_global_date_i(9),
I4 => \rd_data_s[31]_i_22_n_0\,
I5 => hog_global_time_i(9),
O => \rd_data_s[9]_i_2_n_0\
);
s_axi_arready_s_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00004F00"
)
port map (
I0 => \^s_axi_arready_s_reg_0\,
I1 => s_axi_rready,
I2 => rd_addr_latched,
I3 => s_axi_aresetn,
I4 => s_axi_arvalid,
O => s_axi_arready_s_i_1_n_0
);
s_axi_arready_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_arready_s_i_1_n_0,
Q => \^s_axi_arready_s_reg_0\,
R => '0'
);
s_axi_awready_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^s_axi_aresetn_0\
);
s_axi_rvalid_s_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88F8"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready_s_reg_0\,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
O => s_axi_rvalid_s_i_1_n_0
);
s_axi_rvalid_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_s_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^s_axi_aresetn_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if is
port (
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready_s_reg_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if : entity is "axi4lite_wr_channel_if";
end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if;
architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if is
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal \s_axi_awready_s0__0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_s_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_s0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of s_axi_awready_s0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_wready_s_i_1 : label is "soft_lutpair3";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
aw_en_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"7F2A2A2A"
)
port map (
I0 => aw_en_reg_n_0,
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => s_axi_awready_s_reg_0
);
s_axi_awready_s0: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => aw_en_reg_n_0,
O => \s_axi_awready_s0__0\
);
s_axi_awready_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_awready_s0__0\,
Q => s_axi_awready,
R => s_axi_awready_s_reg_0
);
s_axi_bvalid_s_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wvalid,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_axi_bvalid_s_i_1_n_0
);
s_axi_bvalid_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_s_i_1_n_0,
Q => \^s_axi_bvalid\,
R => s_axi_awready_s_reg_0
);
s_axi_wready_s_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => aw_en_reg_n_0,
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => \^s_axi_wready\,
O => s_axi_wready_s0
);
s_axi_wready_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_wready_s0,
Q => \^s_axi_wready\,
R => s_axi_awready_s_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs is
port (
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs : entity is "hog_build_info_regs";
end mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs;
architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs is
begin
\rd_data_s_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => s_axi_rdata(0),
R => SR(0)
);
\rd_data_s_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => s_axi_rdata(10),
R => SR(0)
);
\rd_data_s_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => s_axi_rdata(11),
R => SR(0)
);
\rd_data_s_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(12),
Q => s_axi_rdata(12),
R => SR(0)
);
\rd_data_s_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(13),
Q => s_axi_rdata(13),
R => SR(0)
);
\rd_data_s_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(14),
Q => s_axi_rdata(14),
R => SR(0)
);
\rd_data_s_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(15),
Q => s_axi_rdata(15),
R => SR(0)
);
\rd_data_s_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(16),
Q => s_axi_rdata(16),
R => SR(0)
);
\rd_data_s_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(17),
Q => s_axi_rdata(17),
R => SR(0)
);
\rd_data_s_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(18),
Q => s_axi_rdata(18),
R => SR(0)
);
\rd_data_s_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(19),
Q => s_axi_rdata(19),
R => SR(0)
);
\rd_data_s_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => s_axi_rdata(1),
R => SR(0)
);
\rd_data_s_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(20),
Q => s_axi_rdata(20),
R => SR(0)
);
\rd_data_s_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(21),
Q => s_axi_rdata(21),
R => SR(0)
);
\rd_data_s_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(22),
Q => s_axi_rdata(22),
R => SR(0)
);
\rd_data_s_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(23),
Q => s_axi_rdata(23),
R => SR(0)
);
\rd_data_s_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(24),
Q => s_axi_rdata(24),
R => SR(0)
);
\rd_data_s_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(25),
Q => s_axi_rdata(25),
R => SR(0)
);
\rd_data_s_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(26),
Q => s_axi_rdata(26),
R => SR(0)
);
\rd_data_s_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(27),
Q => s_axi_rdata(27),
R => SR(0)
);
\rd_data_s_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(28),
Q => s_axi_rdata(28),
R => SR(0)
);
\rd_data_s_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(29),
Q => s_axi_rdata(29),
R => SR(0)
);
\rd_data_s_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => s_axi_rdata(2),
R => SR(0)
);
\rd_data_s_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(30),
Q => s_axi_rdata(30),
R => SR(0)
);
\rd_data_s_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(31),
Q => s_axi_rdata(31),
R => SR(0)
);
\rd_data_s_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => s_axi_rdata(3),
R => SR(0)
);
\rd_data_s_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => s_axi_rdata(4),
R => SR(0)
);
\rd_data_s_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => s_axi_rdata(5),
R => SR(0)
);
\rd_data_s_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => s_axi_rdata(6),
R => SR(0)
);
\rd_data_s_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => s_axi_rdata(7),
R => SR(0)
);
\rd_data_s_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => s_axi_rdata(8),
R => SR(0)
);
\rd_data_s_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => s_axi_rdata(9),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if is
port (
s_axi_wready : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready_s_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if : entity is "axi4lite_if";
end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if;
architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
SR(0) <= \^sr\(0);
axi4lite_rd_channel_if_i: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_rd_channel_if
port map (
D(31 downto 0) => D(31 downto 0),
E(0) => E(0),
hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^sr\(0),
s_axi_arready_s_reg_0 => s_axi_arready_s_reg,
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
axi4lite_wr_channel_if_i: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_wr_channel_if
port map (
s_axi_aclk => s_axi_aclk,
s_axi_awready => s_axi_awready,
s_axi_awready_s_reg_0 => \^sr\(0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info is
port (
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arready_s_reg : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info : entity is "axi4lite_hog_build_info";
end mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info;
architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info is
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_valid_s : STD_LOGIC;
begin
axi4lite_if_inst: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_if
port map (
D(31 downto 0) => p_1_in(31 downto 0),
E(0) => rd_valid_s,
SR(0) => p_0_in,
hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready_s_reg => s_axi_arready_s_reg,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
hog_build_info_regs_inst: entity work.mb_design_1_axi4lite_hog_build_i_0_0_hog_build_info_regs
port map (
D(31 downto 0) => p_1_in(31 downto 0),
E(0) => rd_valid_s,
SR(0) => p_0_in,
s_axi_aclk => s_axi_aclk,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mb_design_1_axi4lite_hog_build_i_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "yes";
attribute ip_definition_source : string;
attribute ip_definition_source of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "module_ref";
attribute x_core_info : string;
attribute x_core_info of mb_design_1_axi4lite_hog_build_i_0_0 : entity is "axi4lite_hog_build_info,Vivado 2024.1.2";
end mb_design_1_axi4lite_hog_build_i_0_0;
architecture STRUCTURE of mb_design_1_axi4lite_hog_build_i_0_0 is
signal \<const0>\ : STD_LOGIC;
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 s_axi BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 s_axi RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 s_axi WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 s_axi WVALID";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 s_axi BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 s_axi RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 s_axi RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 s_axi WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
begin
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.mb_design_1_axi4lite_hog_build_i_0_0_axi4lite_hog_build_info
port map (
hog_global_date_i(31 downto 0) => hog_global_date_i(31 downto 0),
hog_global_sha_i(31 downto 0) => hog_global_sha_i(31 downto 0),
hog_global_time_i(31 downto 0) => hog_global_time_i(31 downto 0),
hog_global_ver_i(31 downto 0) => hog_global_ver_i(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready_s_reg => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v deleted 100644 → 0
View file @ e55b3b4a
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
// Date : Thu Mar 20 18:25:04 2025
// Host : hogtest running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.v
// Design : mb_design_1_axi4lite_hog_build_i_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi4lite_hog_build_info,Vivado 2024.1.2" *)
module mb_design_1_axi4lite_hog_build_i_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, hog_global_date_i, hog_global_time_i,
hog_global_ver_i, hog_global_sha_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,hog_global_date_i[31:0],hog_global_time_i[31:0],hog_global_ver_i[31:0],hog_global_sha_i[31:0]" */
/* synthesis syn_force_seq_prim="s_axi_aclk" */;
input s_axi_aclk /* synthesis syn_isclock = 1 */;
input s_axi_aresetn;
input [31:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [31:0]hog_global_date_i;
input [31:0]hog_global_time_i;
input [31:0]hog_global_ver_i;
input [31:0]hog_global_sha_i;
endmodule
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl deleted 100644 → 0
View file @ e55b3b4a
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
-- Date : Thu Mar 20 18:25:04 2025
-- Host : hogtest running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/hogtest/Projets/hog-microblaze-demo/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0_stub.vhdl
-- Design : mb_design_1_axi4lite_hog_build_i_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a200tsbg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mb_design_1_axi4lite_hog_build_i_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end mb_design_1_axi4lite_hog_build_i_0_0;
architecture stub of mb_design_1_axi4lite_hog_build_i_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,hog_global_date_i[31:0],hog_global_time_i[31:0],hog_global_ver_i[31:0],hog_global_sha_i[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi4lite_hog_build_info,Vivado 2024.1.2";
begin
end;
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/sim/mb_design_1_axi4lite_hog_build_i_0_0.vhd deleted 100644 → 0
View file @ e55b3b4a
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axi4lite_hog_build_info:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mb_design_1_axi4lite_hog_build_i_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END mb_design_1_axi4lite_hog_build_i_0_0;
ARCHITECTURE mb_design_1_axi4lite_hog_build_i_0_0_arch OF mb_design_1_axi4lite_hog_build_i_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi4lite_hog_build_info IS
GENERIC (
C_ADDR_WIDTH : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi4lite_hog_build_info;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" &
", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
BEGIN
U0 : axi4lite_hog_build_info
GENERIC MAP (
C_ADDR_WIDTH => 32
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
hog_global_date_i => hog_global_date_i,
hog_global_time_i => hog_global_time_i,
hog_global_ver_i => hog_global_ver_i,
hog_global_sha_i => hog_global_sha_i
);
END mb_design_1_axi4lite_hog_build_i_0_0_arch;
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/synth/mb_design_1_axi4lite_hog_build_i_0_0.vhd deleted 100644 → 0
View file @ e55b3b4a
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- (c) Copyright 2022-2025 Advanced Micro Devices, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of AMD and is protected under U.S. and international copyright
-- and other intellectual property laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- AMD, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) AMD shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or AMD had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- AMD products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of AMD products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:axi4lite_hog_build_info:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mb_design_1_axi4lite_hog_build_i_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END mb_design_1_axi4lite_hog_build_i_0_0;
ARCHITECTURE mb_design_1_axi4lite_hog_build_i_0_0_arch OF mb_design_1_axi4lite_hog_build_i_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi4lite_hog_build_info IS
GENERIC (
C_ADDR_WIDTH : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hog_global_date_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_time_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_ver_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
hog_global_sha_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi4lite_hog_build_info;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "axi4lite_hog_build_info,Vivado 2024.1.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mb_design_1_axi4lite_hog_build_i_0_0_arch : ARCHITECTURE IS "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "mb_design_1_axi4lite_hog_build_i_0_0,axi4lite_hog_build_info,{x_ipProduct=Vivado 2024.1.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=axi4lite_hog_build_info,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ADDR_WIDTH=32}";
ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
ATTRIBUTE IP_DEFINITION_SOURCE OF mb_design_1_axi4lite_hog_build_i_0_0_arch: ARCHITECTURE IS "module_ref";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" &
", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
BEGIN
U0 : axi4lite_hog_build_info
GENERIC MAP (
C_ADDR_WIDTH => 32
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
hog_global_date_i => hog_global_date_i,
hog_global_time_i => hog_global_time_i,
hog_global_ver_i => hog_global_ver_i,
hog_global_sha_i => hog_global_sha_i
);
END mb_design_1_axi4lite_hog_build_i_0_0_arch;
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm deleted 100644 → 0
View file @ e55b3b4a
WORKFLOW_OPERATION simulation,dialog;
DEFINE_MEMORY_TYPE blk_mem_gen_0_32K_1_MEM_DEVICE [0x00008000] 32;
ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 microblaze_0
ADDRESS_SPACE blk_mem_gen_0_32K_1_ADDR_SPACE blk_mem_gen_0_32K_1_MEM_DEVICE [0x00000000:0x00007FFF] dlmb_bram_if_cntlr_0
BUS_BLOCK
blk_mem_gen_0_32K_1_BUS_BLK [31:0] INPUT = "mb_design_1_blk_mem_gen_0_0.mem";
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bxml
View file @ c10d4808
......@@ -2,62 +2,10 @@
<Root MajorVersion="0" MinorVersion="43">
<CompositeFile CompositeFileTopName="mb_design_1" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1742491469"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1742491469"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1742491469"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1742491469"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="synth/mb_design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim/mb_design_1.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="mb_design_1.bmm" Type="BMM">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="mb_design_1_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="hw_handoff/mb_design_1.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="mb_design_1.bda">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="synth/mb_design_1.hwdef">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
<ProcessingOrder Val="NORMAL"/>
</File>
<File Name="sim/mb_design_1.protoinst">
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
<ProcessingOrder Val="NORMAL"/>
</File>
</FileCollection>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1742768614"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1742768614"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1742768614"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1742768614"/>
<FileCollection Name="SOURCES" Type="SOURCES"/>
</CompositeFile>
</Root>
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1_ooc.xdc deleted 100644 → 0
View file @ e55b3b4a
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# This constraints file is not used in normal top-down synthesis (default flow
# of Vivado)
################################################################################
create_clock -name clk_in1 -period 10 [get_ports clk_in1]
################################################################################
\ No newline at end of file
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.protoinst deleted 100644 → 0
View file @ e55b3b4a
{
"version": "1.0",
"modules": {
"mb_design_1": {
"proto_instances": {
"/axi4lite_hog_build_i_0/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_gpio_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr[8:0]"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr[8:0]"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_intc_0/s_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr[8:0]"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr[8:0]"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/axi_interconnect_0/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M00_ACLK"},
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARREADY": { "actual": "M00_AXI_arready"},
"ARVALID": { "actual": "M00_AXI_arvalid"},
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
"AWREADY": { "actual": "M00_AXI_awready"},
"AWVALID": { "actual": "M00_AXI_awvalid"},
"BREADY": { "actual": "M00_AXI_bready"},
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
"BVALID": { "actual": "M00_AXI_bvalid"},
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
"RREADY": { "actual": "M00_AXI_rready"},
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
"RVALID": { "actual": "M00_AXI_rvalid"},
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
"WREADY": { "actual": "M00_AXI_wready"},
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M00_AXI_wvalid"}
}
},
"/axi_interconnect_0/M01_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M01_ACLK"},
"ARADDR": { "actual": "M01_AXI_araddr[63:32]"},
"ARESETN": { "actual": "ARESETN"},
"ARREADY": { "actual": "M01_AXI_arready"},
"ARVALID": { "actual": "M01_AXI_arvalid"},
"AWADDR": { "actual": "M01_AXI_awaddr[63:32]"},
"AWREADY": { "actual": "M01_AXI_awready"},
"AWVALID": { "actual": "M01_AXI_awvalid"},
"BREADY": { "actual": "M01_AXI_bready"},
"BRESP": { "actual": "M01_AXI_bresp[3:2]"},
"BVALID": { "actual": "M01_AXI_bvalid"},
"RDATA": { "actual": "M01_AXI_rdata[63:32]"},
"RREADY": { "actual": "M01_AXI_rready"},
"RRESP": { "actual": "M01_AXI_rresp[3:2]"},
"RVALID": { "actual": "M01_AXI_rvalid"},
"WDATA": { "actual": "M01_AXI_wdata[63:32]"},
"WREADY": { "actual": "M01_AXI_wready"},
"WSTRB": { "actual": "M01_AXI_wstrb[7:4]"},
"WVALID": { "actual": "M01_AXI_wvalid"}
}
},
"/axi_interconnect_0/M02_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M02_ACLK"},
"ARADDR": { "actual": "M02_AXI_araddr[95:64]"},
"ARESETN": { "actual": "ARESETN"},
"ARREADY": { "actual": "M02_AXI_arready"},
"ARVALID": { "actual": "M02_AXI_arvalid"},
"AWADDR": { "actual": "M02_AXI_awaddr[95:64]"},
"AWREADY": { "actual": "M02_AXI_awready"},
"AWVALID": { "actual": "M02_AXI_awvalid"},
"BREADY": { "actual": "M02_AXI_bready"},
"BRESP": { "actual": "M02_AXI_bresp[5:4]"},
"BVALID": { "actual": "M02_AXI_bvalid"},
"RDATA": { "actual": "M02_AXI_rdata[95:64]"},
"RREADY": { "actual": "M02_AXI_rready"},
"RRESP": { "actual": "M02_AXI_rresp[5:4]"},
"RVALID": { "actual": "M02_AXI_rvalid"},
"WDATA": { "actual": "M02_AXI_wdata[95:64]"},
"WREADY": { "actual": "M02_AXI_wready"},
"WSTRB": { "actual": "M02_AXI_wstrb[11:8]"},
"WVALID": { "actual": "M02_AXI_wvalid"}
}
},
"/axi_interconnect_0/M03_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M03_ACLK"},
"ARADDR": { "actual": "M03_AXI_araddr[127:96]"},
"ARESETN": { "actual": "ARESETN"},
"ARREADY": { "actual": "M03_AXI_arready"},
"ARVALID": { "actual": "M03_AXI_arvalid"},
"AWADDR": { "actual": "M03_AXI_awaddr[127:96]"},
"AWREADY": { "actual": "M03_AXI_awready"},
"AWVALID": { "actual": "M03_AXI_awvalid"},
"BREADY": { "actual": "M03_AXI_bready"},
"BRESP": { "actual": "M03_AXI_bresp[7:6]"},
"BVALID": { "actual": "M03_AXI_bvalid"},
"RDATA": { "actual": "M03_AXI_rdata[127:96]"},
"RREADY": { "actual": "M03_AXI_rready"},
"RRESP": { "actual": "M03_AXI_rresp[7:6]"},
"RVALID": { "actual": "M03_AXI_rvalid"},
"WDATA": { "actual": "M03_AXI_wdata[127:96]"},
"WREADY": { "actual": "M03_AXI_wready"},
"WSTRB": { "actual": "M03_AXI_wstrb[15:12]"},
"WVALID": { "actual": "M03_AXI_wvalid"}
}
},
"/axi_interconnect_0/M04_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M04_ACLK"},
"ARADDR": { "actual": "M04_AXI_araddr[159:128]"},
"ARESETN": { "actual": "ARESETN"},
"ARREADY": { "actual": "M04_AXI_arready"},
"ARVALID": { "actual": "M04_AXI_arvalid"},
"AWADDR": { "actual": "M04_AXI_awaddr[159:128]"},
"AWREADY": { "actual": "M04_AXI_awready"},
"AWVALID": { "actual": "M04_AXI_awvalid"},
"BREADY": { "actual": "M04_AXI_bready"},
"BRESP": { "actual": "M04_AXI_bresp[9:8]"},
"BVALID": { "actual": "M04_AXI_bvalid"},
"RDATA": { "actual": "M04_AXI_rdata[159:128]"},
"RREADY": { "actual": "M04_AXI_rready"},
"RRESP": { "actual": "M04_AXI_rresp[9:8]"},
"RVALID": { "actual": "M04_AXI_rvalid"},
"WDATA": { "actual": "M04_AXI_wdata[159:128]"},
"WREADY": { "actual": "M04_AXI_wready"},
"WSTRB": { "actual": "M04_AXI_wstrb[19:16]"},
"WVALID": { "actual": "M04_AXI_wvalid"}
}
},
"/axi_interconnect_0/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S00_ACLK"},
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
"ARREADY": { "actual": "S00_AXI_arready[0:0]"},
"ARVALID": { "actual": "S00_AXI_arvalid[0:0]"},
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
"AWREADY": { "actual": "S00_AXI_awready[0:0]"},
"AWVALID": { "actual": "S00_AXI_awvalid[0:0]"},
"BREADY": { "actual": "S00_AXI_bready[0:0]"},
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
"BVALID": { "actual": "S00_AXI_bvalid[0:0]"},
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
"RREADY": { "actual": "S00_AXI_rready[0:0]"},
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
"RVALID": { "actual": "S00_AXI_rvalid[0:0]"},
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
"WREADY": { "actual": "S00_AXI_wready[0:0]"},
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S00_AXI_wvalid[0:0]"}
}
},
"/axi_interconnect_0/m00_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/axi_interconnect_0/m00_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/axi_interconnect_0/m01_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[63:32]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[63:32]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[3:2]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[63:32]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[3:2]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[63:32]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[7:4]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/axi_interconnect_0/m01_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[63:32]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[63:32]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[3:2]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[63:32]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[3:2]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[63:32]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[7:4]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/axi_interconnect_0/m02_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[95:64]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[95:64]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[5:4]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[95:64]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[5:4]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[95:64]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[11:8]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/axi_interconnect_0/m02_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[95:64]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[95:64]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[5:4]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[95:64]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[5:4]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[95:64]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[11:8]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/axi_interconnect_0/m03_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[127:96]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[127:96]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[7:6]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[127:96]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[7:6]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[127:96]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[15:12]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/axi_interconnect_0/m03_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[127:96]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[127:96]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[7:6]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[127:96]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[7:6]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[127:96]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[15:12]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/axi_interconnect_0/m04_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[159:128]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[159:128]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[9:8]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[159:128]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[9:8]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[159:128]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[19:16]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/axi_interconnect_0/m04_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[159:128]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[159:128]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[9:8]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[159:128]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[9:8]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[159:128]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[19:16]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/axi_interconnect_0/s00_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
"ARREADY": { "actual": "M_AXI_arready[0:0]"},
"ARVALID": { "actual": "M_AXI_arvalid[0:0]"},
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
"AWREADY": { "actual": "M_AXI_awready[0:0]"},
"AWVALID": { "actual": "M_AXI_awvalid[0:0]"},
"BREADY": { "actual": "M_AXI_bready[0:0]"},
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
"BVALID": { "actual": "M_AXI_bvalid[0:0]"},
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
"RREADY": { "actual": "M_AXI_rready[0:0]"},
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
"RVALID": { "actual": "M_AXI_rvalid[0:0]"},
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
"WREADY": { "actual": "M_AXI_wready[0:0]"},
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M_AXI_wvalid[0:0]"}
}
},
"/axi_interconnect_0/s00_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
"ARREADY": { "actual": "S_AXI_arready[0:0]"},
"ARVALID": { "actual": "S_AXI_arvalid[0:0]"},
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
"AWREADY": { "actual": "S_AXI_awready[0:0]"},
"AWVALID": { "actual": "S_AXI_awvalid[0:0]"},
"BREADY": { "actual": "S_AXI_bready[0:0]"},
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
"BVALID": { "actual": "S_AXI_bvalid[0:0]"},
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
"RREADY": { "actual": "S_AXI_rready[0:0]"},
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
"RVALID": { "actual": "S_AXI_rvalid[0:0]"},
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
"WREADY": { "actual": "S_AXI_wready[0:0]"},
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S_AXI_wvalid[0:0]"}
}
},
"/axi_interconnect_0/xbar/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
"ARREADY": { "actual": "m_axi_arready[0:0]"},
"ARVALID": { "actual": "m_axi_arvalid[0:0]"},
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
"AWREADY": { "actual": "m_axi_awready[0:0]"},
"AWVALID": { "actual": "m_axi_awvalid[0:0]"},
"BREADY": { "actual": "m_axi_bready[0:0]"},
"BRESP": { "actual": "m_axi_bresp[1:0]"},
"BVALID": { "actual": "m_axi_bvalid[0:0]"},
"RDATA": { "actual": "m_axi_rdata[31:0]"},
"RREADY": { "actual": "m_axi_rready[0:0]"},
"RRESP": { "actual": "m_axi_rresp[1:0]"},
"RVALID": { "actual": "m_axi_rvalid[0:0]"},
"WDATA": { "actual": "m_axi_wdata[31:0]"},
"WREADY": { "actual": "m_axi_wready[0:0]"},
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
"WVALID": { "actual": "m_axi_wvalid[0:0]"}
}
},
"/axi_interconnect_0/xbar/M01_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[63:32]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[5:3]"},
"ARREADY": { "actual": "m_axi_arready[1:1]"},
"ARVALID": { "actual": "m_axi_arvalid[1:1]"},
"AWADDR": { "actual": "m_axi_awaddr[63:32]"},
"AWPROT": { "actual": "m_axi_awprot[5:3]"},
"AWREADY": { "actual": "m_axi_awready[1:1]"},
"AWVALID": { "actual": "m_axi_awvalid[1:1]"},
"BREADY": { "actual": "m_axi_bready[1:1]"},
"BRESP": { "actual": "m_axi_bresp[3:2]"},
"BVALID": { "actual": "m_axi_bvalid[1:1]"},
"RDATA": { "actual": "m_axi_rdata[63:32]"},
"RREADY": { "actual": "m_axi_rready[1:1]"},
"RRESP": { "actual": "m_axi_rresp[3:2]"},
"RVALID": { "actual": "m_axi_rvalid[1:1]"},
"WDATA": { "actual": "m_axi_wdata[63:32]"},
"WREADY": { "actual": "m_axi_wready[1:1]"},
"WSTRB": { "actual": "m_axi_wstrb[7:4]"},
"WVALID": { "actual": "m_axi_wvalid[1:1]"}
}
},
"/axi_interconnect_0/xbar/M02_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[95:64]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[8:6]"},
"ARREADY": { "actual": "m_axi_arready[2:2]"},
"ARVALID": { "actual": "m_axi_arvalid[2:2]"},
"AWADDR": { "actual": "m_axi_awaddr[95:64]"},
"AWPROT": { "actual": "m_axi_awprot[8:6]"},
"AWREADY": { "actual": "m_axi_awready[2:2]"},
"AWVALID": { "actual": "m_axi_awvalid[2:2]"},
"BREADY": { "actual": "m_axi_bready[2:2]"},
"BRESP": { "actual": "m_axi_bresp[5:4]"},
"BVALID": { "actual": "m_axi_bvalid[2:2]"},
"RDATA": { "actual": "m_axi_rdata[95:64]"},
"RREADY": { "actual": "m_axi_rready[2:2]"},
"RRESP": { "actual": "m_axi_rresp[5:4]"},
"RVALID": { "actual": "m_axi_rvalid[2:2]"},
"WDATA": { "actual": "m_axi_wdata[95:64]"},
"WREADY": { "actual": "m_axi_wready[2:2]"},
"WSTRB": { "actual": "m_axi_wstrb[11:8]"},
"WVALID": { "actual": "m_axi_wvalid[2:2]"}
}
},
"/axi_interconnect_0/xbar/M03_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[127:96]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[11:9]"},
"ARREADY": { "actual": "m_axi_arready[3:3]"},
"ARVALID": { "actual": "m_axi_arvalid[3:3]"},
"AWADDR": { "actual": "m_axi_awaddr[127:96]"},
"AWPROT": { "actual": "m_axi_awprot[11:9]"},
"AWREADY": { "actual": "m_axi_awready[3:3]"},
"AWVALID": { "actual": "m_axi_awvalid[3:3]"},
"BREADY": { "actual": "m_axi_bready[3:3]"},
"BRESP": { "actual": "m_axi_bresp[7:6]"},
"BVALID": { "actual": "m_axi_bvalid[3:3]"},
"RDATA": { "actual": "m_axi_rdata[127:96]"},
"RREADY": { "actual": "m_axi_rready[3:3]"},
"RRESP": { "actual": "m_axi_rresp[7:6]"},
"RVALID": { "actual": "m_axi_rvalid[3:3]"},
"WDATA": { "actual": "m_axi_wdata[127:96]"},
"WREADY": { "actual": "m_axi_wready[3:3]"},
"WSTRB": { "actual": "m_axi_wstrb[15:12]"},
"WVALID": { "actual": "m_axi_wvalid[3:3]"}
}
},
"/axi_interconnect_0/xbar/M04_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[159:128]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[14:12]"},
"ARREADY": { "actual": "m_axi_arready[4:4]"},
"ARVALID": { "actual": "m_axi_arvalid[4:4]"},
"AWADDR": { "actual": "m_axi_awaddr[159:128]"},
"AWPROT": { "actual": "m_axi_awprot[14:12]"},
"AWREADY": { "actual": "m_axi_awready[4:4]"},
"AWVALID": { "actual": "m_axi_awvalid[4:4]"},
"BREADY": { "actual": "m_axi_bready[4:4]"},
"BRESP": { "actual": "m_axi_bresp[9:8]"},
"BVALID": { "actual": "m_axi_bvalid[4:4]"},
"RDATA": { "actual": "m_axi_rdata[159:128]"},
"RREADY": { "actual": "m_axi_rready[4:4]"},
"RRESP": { "actual": "m_axi_rresp[9:8]"},
"RVALID": { "actual": "m_axi_rvalid[4:4]"},
"WDATA": { "actual": "m_axi_wdata[159:128]"},
"WREADY": { "actual": "m_axi_wready[4:4]"},
"WSTRB": { "actual": "m_axi_wstrb[19:16]"},
"WVALID": { "actual": "m_axi_wvalid[4:4]"}
}
},
"/axi_interconnect_0/xbar/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
"ARREADY": { "actual": "s_axi_arready[0:0]"},
"ARVALID": { "actual": "s_axi_arvalid[0:0]"},
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
"AWREADY": { "actual": "s_axi_awready[0:0]"},
"AWVALID": { "actual": "s_axi_awvalid[0:0]"},
"BREADY": { "actual": "s_axi_bready[0:0]"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid[0:0]"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RREADY": { "actual": "s_axi_rready[0:0]"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid[0:0]"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WREADY": { "actual": "s_axi_wready[0:0]"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid[0:0]"}
}
},
"/axi_timer_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr[4:0]"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr[4:0]"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/mdm_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_AXI_ACLK"},
"ARADDR": { "actual": "S_AXI_ARADDR[3:0]"},
"ARESETN": { "actual": "S_AXI_ARESETN"},
"ARREADY": { "actual": "S_AXI_ARREADY"},
"ARVALID": { "actual": "S_AXI_ARVALID"},
"AWADDR": { "actual": "S_AXI_AWADDR[3:0]"},
"AWREADY": { "actual": "S_AXI_AWREADY"},
"AWVALID": { "actual": "S_AXI_AWVALID"},
"BREADY": { "actual": "S_AXI_BREADY"},
"BRESP": { "actual": "S_AXI_BRESP[1:0]"},
"BVALID": { "actual": "S_AXI_BVALID"},
"RDATA": { "actual": "S_AXI_RDATA[31:0]"},
"RREADY": { "actual": "S_AXI_RREADY"},
"RRESP": { "actual": "S_AXI_RRESP[1:0]"},
"RVALID": { "actual": "S_AXI_RVALID"},
"WDATA": { "actual": "S_AXI_WDATA[31:0]"},
"WREADY": { "actual": "S_AXI_WREADY"},
"WSTRB": { "actual": "S_AXI_WSTRB[3:0]"},
"WVALID": { "actual": "S_AXI_WVALID"}
}
},
"/microblaze_0/M_AXI_DP": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "Clk"},
"ARADDR": { "actual": "M_AXI_DP_ARADDR[31:0]"},
"ARESET": { "actual": "Reset"},
"ARPROT": { "actual": "M_AXI_DP_ARPROT[2:0]"},
"ARREADY": { "actual": "M_AXI_DP_ARREADY"},
"ARVALID": { "actual": "M_AXI_DP_ARVALID"},
"AWADDR": { "actual": "M_AXI_DP_AWADDR[31:0]"},
"AWPROT": { "actual": "M_AXI_DP_AWPROT[2:0]"},
"AWREADY": { "actual": "M_AXI_DP_AWREADY"},
"AWVALID": { "actual": "M_AXI_DP_AWVALID"},
"BREADY": { "actual": "M_AXI_DP_BREADY"},
"BRESP": { "actual": "M_AXI_DP_BRESP[1:0]"},
"BVALID": { "actual": "M_AXI_DP_BVALID"},
"RDATA": { "actual": "M_AXI_DP_RDATA[31:0]"},
"RREADY": { "actual": "M_AXI_DP_RREADY"},
"RRESP": { "actual": "M_AXI_DP_RRESP[1:0]"},
"RVALID": { "actual": "M_AXI_DP_RVALID"},
"WDATA": { "actual": "M_AXI_DP_WDATA[31:0]"},
"WREADY": { "actual": "M_AXI_DP_WREADY"},
"WSTRB": { "actual": "M_AXI_DP_WSTRB[3:0]"},
"WVALID": { "actual": "M_AXI_DP_WVALID"}
}
}
}
}
}
}
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd deleted 100644 → 0
View file @ e55b3b4a
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--Date : Thu Mar 20 18:24:28 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1.bd
--Design : mb_design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_L30N86 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_L30N86;
architecture STRUCTURE of m00_couplers_imp_L30N86 is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1MV3QBS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1MV3QBS;
architecture STRUCTURE of m01_couplers_imp_1MV3QBS is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1CM8QGB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1CM8QGB;
architecture STRUCTURE of m02_couplers_imp_1CM8QGB is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_DKAE7P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_DKAE7P;
architecture STRUCTURE of m03_couplers_imp_DKAE7P is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_OP7ZFX is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_OP7ZFX;
architecture STRUCTURE of m04_couplers_imp_OP7ZFX is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1AM08ZQ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_1AM08ZQ;
architecture STRUCTURE of s00_couplers_imp_1AM08ZQ is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mb_design_1_axi_interconnect_0_0;
architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
component mb_design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component mb_design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_axi_interconnect_0_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_axi_interconnect_0_AWVALID;
M02_AXI_bready <= m02_couplers_to_axi_interconnect_0_BREADY;
M02_AXI_rready <= m02_couplers_to_axi_interconnect_0_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_axi_interconnect_0_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_axi_interconnect_0_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_axi_interconnect_0_AWVALID;
M03_AXI_bready <= m03_couplers_to_axi_interconnect_0_BREADY;
M03_AXI_rready <= m03_couplers_to_axi_interconnect_0_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_axi_interconnect_0_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_axi_interconnect_0_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_axi_interconnect_0_AWVALID;
M04_AXI_bready <= m04_couplers_to_axi_interconnect_0_BREADY;
M04_AXI_rready <= m04_couplers_to_axi_interconnect_0_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= axi_interconnect_0_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= axi_interconnect_0_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= axi_interconnect_0_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_interconnect_0_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= axi_interconnect_0_to_s00_couplers_WREADY(0);
axi_interconnect_0_ACLK_net <= ACLK;
axi_interconnect_0_ARESETN_net <= ARESETN;
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
axi_interconnect_0_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
axi_interconnect_0_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
m02_couplers_to_axi_interconnect_0_ARREADY <= M02_AXI_arready;
m02_couplers_to_axi_interconnect_0_AWREADY <= M02_AXI_awready;
m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_axi_interconnect_0_BVALID <= M02_AXI_bvalid;
m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_axi_interconnect_0_RVALID <= M02_AXI_rvalid;
m02_couplers_to_axi_interconnect_0_WREADY <= M02_AXI_wready;
m03_couplers_to_axi_interconnect_0_ARREADY <= M03_AXI_arready;
m03_couplers_to_axi_interconnect_0_AWREADY <= M03_AXI_awready;
m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_BVALID <= M03_AXI_bvalid;
m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_RVALID <= M03_AXI_rvalid;
m03_couplers_to_axi_interconnect_0_WREADY <= M03_AXI_wready;
m04_couplers_to_axi_interconnect_0_ARREADY <= M04_AXI_arready;
m04_couplers_to_axi_interconnect_0_AWREADY <= M04_AXI_awready;
m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_axi_interconnect_0_BVALID <= M04_AXI_bvalid;
m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_axi_interconnect_0_RVALID <= M04_AXI_rvalid;
m04_couplers_to_axi_interconnect_0_WREADY <= M04_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_L30N86
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1MV3QBS
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1CM8QGB
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m02_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m02_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m02_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_DKAE7P
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m03_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m03_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m03_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_OP7ZFX
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m04_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m04_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m04_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
s00_couplers: entity work.s00_couplers_imp_1AM08ZQ
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN => axi_interconnect_0_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_interconnect_0_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => axi_interconnect_0_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => axi_interconnect_0_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => axi_interconnect_0_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => axi_interconnect_0_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_interconnect_0_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => axi_interconnect_0_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_interconnect_0_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => axi_interconnect_0_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_interconnect_0_to_s00_couplers_WVALID(0)
);
xbar: component mb_design_1_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net,
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0),
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0),
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1 is
port (
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk_in1 : in STD_LOGIC;
hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=15,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of mb_design_1 : entity is "mb_design_1.hwdef";
end mb_design_1;
architecture STRUCTURE of mb_design_1 is
component mb_design_1_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC
);
end component mb_design_1_microblaze_0_0;
component mb_design_1_clk_wiz_0_0 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_100mhz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component mb_design_1_clk_wiz_0_0;
component mb_design_1_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mb_design_1_proc_sys_reset_0_0;
component mb_design_1_lmb_v10_0_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component mb_design_1_lmb_v10_0_0;
component mb_design_1_ilmb_v10_0_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component mb_design_1_ilmb_v10_0_0;
component mb_design_1_lmb_bram_if_cntlr_0_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component mb_design_1_lmb_bram_if_cntlr_0_0;
component mb_design_1_lmb_bram_if_cntlr_0_1 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component mb_design_1_lmb_bram_if_cntlr_0_1;
component mb_design_1_blk_mem_gen_0_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC
);
end component mb_design_1_blk_mem_gen_0_0;
component mb_design_1_mdm_0_0 is
port (
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
Interrupt : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
end component mb_design_1_mdm_0_0;
component mb_design_1_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component mb_design_1_axi_gpio_0_0;
component mb_design_1_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component mb_design_1_axi_timer_0_0;
component mb_design_1_axi_intc_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 0 to 0 );
irq : out STD_LOGIC
);
end component mb_design_1_axi_intc_0_0;
component mb_design_1_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mb_design_1_xlconcat_0_0;
component mb_design_1_axi4lite_hog_build_i_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component mb_design_1_axi4lite_hog_build_i_0_0;
signal Conn1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_ADDRSTROBE : STD_LOGIC;
signal Conn1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal Conn1_CE : STD_LOGIC;
signal Conn1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_READSTROBE : STD_LOGIC;
signal Conn1_READY : STD_LOGIC;
signal Conn1_UE : STD_LOGIC;
signal Conn1_WAIT : STD_LOGIC;
signal Conn1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_WRITESTROBE : STD_LOGIC;
signal Conn_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn_ADDRSTROBE : STD_LOGIC;
signal Conn_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal Conn_CE : STD_LOGIC;
signal Conn_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn_READSTROBE : STD_LOGIC;
signal Conn_READY : STD_LOGIC;
signal Conn_UE : STD_LOGIC;
signal Conn_WAIT : STD_LOGIC;
signal Conn_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn_WRITESTROBE : STD_LOGIC;
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_intc_0_interrupt_INTERRUPT : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_timer_0_interrupt : STD_LOGIC;
signal clk_in1_0_1 : STD_LOGIC;
signal clk_wiz_0_clk_100mhz : STD_LOGIC;
signal clk_wiz_0_locked : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal dlmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal dlmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal hog_global_date_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hog_global_sha_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hog_global_time_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hog_global_ver_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal mdm_0_Debug_SYS_Rst : STD_LOGIC;
signal mdm_0_MBDEBUG_0_CAPTURE : STD_LOGIC;
signal mdm_0_MBDEBUG_0_CLK : STD_LOGIC;
signal mdm_0_MBDEBUG_0_DISABLE : STD_LOGIC;
signal mdm_0_MBDEBUG_0_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal mdm_0_MBDEBUG_0_RST : STD_LOGIC;
signal mdm_0_MBDEBUG_0_SHIFT : STD_LOGIC;
signal mdm_0_MBDEBUG_0_TDI : STD_LOGIC;
signal mdm_0_MBDEBUG_0_TDO : STD_LOGIC;
signal mdm_0_MBDEBUG_0_UPDATE : STD_LOGIC;
signal microblaze_0_DLMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_DLMB_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_DLMB_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_DLMB_CE : STD_LOGIC;
signal microblaze_0_DLMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_DLMB_READSTROBE : STD_LOGIC;
signal microblaze_0_DLMB_READY : STD_LOGIC;
signal microblaze_0_DLMB_UE : STD_LOGIC;
signal microblaze_0_DLMB_WAIT : STD_LOGIC;
signal microblaze_0_DLMB_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_DLMB_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ILMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ILMB_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ILMB_CE : STD_LOGIC;
signal microblaze_0_ILMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ILMB_READSTROBE : STD_LOGIC;
signal microblaze_0_ILMB_READY : STD_LOGIC;
signal microblaze_0_ILMB_UE : STD_LOGIC;
signal microblaze_0_ILMB_WAIT : STD_LOGIC;
signal proc_sys_reset_0_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_mb_reset : STD_LOGIC;
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal reset_0_1 : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_mdm_0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_Interrupt_Ack_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 1 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr_0 : label is "byte 0x00000000 32 > mb_design_1 blk_mem_gen_0";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr_0 : label is "yes";
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > mb_design_1 dlmb_bram_if_cntlr_0";
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of clk_in1 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_IN1 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of clk_in1 : signal is "XIL_INTERFACENAME CLK.CLK_IN1, ASSOCIATED_RESET reset, CLK_DOMAIN mb_design_1_clk_in1_0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 RST.RESET RST";
attribute X_INTERFACE_PARAMETER of reset : signal is "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of GPIO_0_tri_o : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O";
begin
GPIO_0_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
clk_in1_0_1 <= clk_in1;
hog_global_date_i_0_1(31 downto 0) <= hog_global_date_i_0(31 downto 0);
hog_global_sha_i_0_1(31 downto 0) <= hog_global_sha_i_0(31 downto 0);
hog_global_time_i_0_1(31 downto 0) <= hog_global_time_i_0(31 downto 0);
hog_global_ver_i_0_1(31 downto 0) <= hog_global_ver_i_0(31 downto 0);
reset_0_1 <= reset;
axi4lite_hog_build_i_0: component mb_design_1_axi4lite_hog_build_i_0_0
port map (
hog_global_date_i(31 downto 0) => hog_global_date_i_0_1(31 downto 0),
hog_global_sha_i(31 downto 0) => hog_global_sha_i_0_1(31 downto 0),
hog_global_time_i(31 downto 0) => hog_global_time_i_0_1(31 downto 0),
hog_global_ver_i(31 downto 0) => hog_global_ver_i_0_1(31 downto 0),
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M04_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
s_axi_awready => axi_interconnect_0_M04_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M04_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M04_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M04_AXI_WVALID
);
axi_gpio_0: component mb_design_1_axi_gpio_0_0
port map (
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
s_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
axi_intc_0: component mb_design_1_axi_intc_0_0
port map (
intr(0) => xlconcat_0_dout(0),
irq => axi_intc_0_interrupt_INTERRUPT,
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(8 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(8 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(8 downto 0),
s_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
port map (
ACLK => clk_wiz_0_clk_100mhz,
ARESETN => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => clk_wiz_0_clk_100mhz,
M00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => clk_wiz_0_clk_100mhz,
M01_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
M02_ACLK => clk_wiz_0_clk_100mhz,
M02_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_100mhz,
M03_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
M04_ACLK => clk_wiz_0_clk_100mhz,
M04_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_100mhz,
S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arready(0) => S00_AXI_1_ARREADY(0),
S00_AXI_arvalid(0) => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awready(0) => S00_AXI_1_AWREADY(0),
S00_AXI_awvalid(0) => S00_AXI_1_AWVALID,
S00_AXI_bready(0) => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid(0) => S00_AXI_1_BVALID(0),
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rready(0) => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid(0) => S00_AXI_1_RVALID(0),
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wready(0) => S00_AXI_1_WREADY(0),
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => S00_AXI_1_WVALID
);
axi_timer_0: component mb_design_1_axi_timer_0_0
port map (
capturetrig0 => '0',
capturetrig1 => '0',
freeze => '0',
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(4 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(4 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
s_axi_awaddr(4 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(4 downto 0),
s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
blk_mem_gen_0: component mb_design_1_blk_mem_gen_0_0
port map (
addra(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
addra(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
addra(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
addra(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
addra(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
addra(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
addra(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
addra(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
addra(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
addra(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
addra(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
addra(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
addra(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
addra(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
addra(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
addra(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
addra(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
addra(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
addra(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
addra(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
addra(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
addra(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
addra(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
addra(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
addra(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
addra(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
addra(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
addra(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
addra(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
addra(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
addra(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
addra(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
addrb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
addrb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
addrb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
addrb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
addrb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
addrb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
addrb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
addrb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
addrb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
addrb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
addrb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
addrb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
addrb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
addrb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
addrb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
addrb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
addrb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
addrb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
addrb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
addrb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
addrb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
addrb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
addrb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
addrb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
addrb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
addrb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
addrb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
addrb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
addrb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
addrb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
addrb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
addrb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
clka => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
clkb => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
dina(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
dina(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
dina(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
dina(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
dina(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
dina(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
dina(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
dina(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
dina(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
dina(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
dina(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
dina(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
dina(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
dina(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
dina(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
dina(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
dina(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
dina(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
dina(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
dina(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
dina(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
dina(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
dina(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
dina(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
dina(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
dina(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
dina(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
dina(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
dina(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
dina(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
dina(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
dina(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
dinb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
dinb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
dinb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
dinb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
dinb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
dinb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
dinb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
dinb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
dinb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
dinb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
dinb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
dinb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
dinb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
dinb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
dinb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
dinb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
dinb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
dinb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
dinb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
dinb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
dinb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
dinb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
dinb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
dinb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
dinb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
dinb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
dinb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
dinb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
dinb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
dinb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
dinb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
dinb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
douta(31 downto 0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
doutb(31 downto 0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
ena => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
enb => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
rsta => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
rsta_busy => NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED,
rstb => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
rstb_busy => NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED,
wea(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
wea(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
wea(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
wea(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(3),
web(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
web(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
web(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
web(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(3)
);
clk_wiz_0: component mb_design_1_clk_wiz_0_0
port map (
clk_100mhz => clk_wiz_0_clk_100mhz,
clk_in1 => clk_in1_0_1,
locked => clk_wiz_0_locked,
reset => reset_0_1
);
dlmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_0
port map (
BRAM_Addr_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
BRAM_Clk_A => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
BRAM_Din_A(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
BRAM_Din_A(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
BRAM_Din_A(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
BRAM_Din_A(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
BRAM_Din_A(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
BRAM_Din_A(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
BRAM_Din_A(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
BRAM_Din_A(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
BRAM_Din_A(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
BRAM_Din_A(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
BRAM_Din_A(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
BRAM_Din_A(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
BRAM_Din_A(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
BRAM_Din_A(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
BRAM_Din_A(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
BRAM_Din_A(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
BRAM_Din_A(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
BRAM_Din_A(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
BRAM_Din_A(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
BRAM_Din_A(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
BRAM_Din_A(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
BRAM_Din_A(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
BRAM_Din_A(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
BRAM_Din_A(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
BRAM_Din_A(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
BRAM_Din_A(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
BRAM_Din_A(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
BRAM_Din_A(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
BRAM_Din_A(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
BRAM_Din_A(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
BRAM_Din_A(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
BRAM_Din_A(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
BRAM_Dout_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
BRAM_EN_A => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
BRAM_Rst_A => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
BRAM_WEN_A(0 to 3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
LMB_AddrStrobe => Conn1_ADDRSTROBE,
LMB_BE(0 to 3) => Conn1_BE(0 to 3),
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadStrobe => Conn1_READSTROBE,
LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn1_WRITESTROBE,
Sl_CE => Conn1_CE,
Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
Sl_Ready => Conn1_READY,
Sl_UE => Conn1_UE,
Sl_Wait => Conn1_WAIT
);
dlmb_v10_0: component mb_design_1_ilmb_v10_0_0
port map (
LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
LMB_AddrStrobe => Conn1_ADDRSTROBE,
LMB_BE(0 to 3) => Conn1_BE(0 to 3),
LMB_CE => microblaze_0_DLMB_CE,
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadDBus(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
LMB_ReadStrobe => Conn1_READSTROBE,
LMB_Ready => microblaze_0_DLMB_READY,
LMB_Rst => NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_DLMB_UE,
LMB_Wait => microblaze_0_DLMB_WAIT,
LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn1_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_DLMB_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_DLMB_READSTROBE,
M_WriteStrobe => microblaze_0_DLMB_WRITESTROBE,
SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
Sl_CE(0) => Conn1_CE,
Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
Sl_Ready(0) => Conn1_READY,
Sl_UE(0) => Conn1_UE,
Sl_Wait(0) => Conn1_WAIT
);
ilmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_1
port map (
BRAM_Addr_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
BRAM_Clk_A => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
BRAM_Din_A(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
BRAM_Din_A(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
BRAM_Din_A(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
BRAM_Din_A(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
BRAM_Din_A(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
BRAM_Din_A(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
BRAM_Din_A(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
BRAM_Din_A(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
BRAM_Din_A(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
BRAM_Din_A(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
BRAM_Din_A(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
BRAM_Din_A(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
BRAM_Din_A(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
BRAM_Din_A(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
BRAM_Din_A(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
BRAM_Din_A(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
BRAM_Din_A(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
BRAM_Din_A(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
BRAM_Din_A(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
BRAM_Din_A(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
BRAM_Din_A(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
BRAM_Din_A(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
BRAM_Din_A(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
BRAM_Din_A(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
BRAM_Din_A(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
BRAM_Din_A(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
BRAM_Din_A(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
BRAM_Din_A(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
BRAM_Din_A(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
BRAM_Din_A(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
BRAM_Din_A(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
BRAM_Din_A(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
BRAM_Dout_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
BRAM_EN_A => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
BRAM_Rst_A => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
BRAM_WEN_A(0 to 3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
LMB_AddrStrobe => Conn_ADDRSTROBE,
LMB_BE(0 to 3) => Conn_BE(0 to 3),
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadStrobe => Conn_READSTROBE,
LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn_WRITESTROBE,
Sl_CE => Conn_CE,
Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
Sl_Ready => Conn_READY,
Sl_UE => Conn_UE,
Sl_Wait => Conn_WAIT
);
ilmb_v10_0: component mb_design_1_lmb_v10_0_0
port map (
LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
LMB_AddrStrobe => Conn_ADDRSTROBE,
LMB_BE(0 to 3) => Conn_BE(0 to 3),
LMB_CE => microblaze_0_ILMB_CE,
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadDBus(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
LMB_ReadStrobe => Conn_READSTROBE,
LMB_Ready => microblaze_0_ILMB_READY,
LMB_Rst => NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ILMB_UE,
LMB_Wait => microblaze_0_ILMB_WAIT,
LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ILMB_ADDRSTROBE,
M_BE(0 to 3) => B"0000",
M_DBus(0 to 31) => B"00000000000000000000000000000000",
M_ReadStrobe => microblaze_0_ILMB_READSTROBE,
M_WriteStrobe => '0',
SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
Sl_CE(0) => Conn_CE,
Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
Sl_Ready(0) => Conn_READY,
Sl_UE(0) => Conn_UE,
Sl_Wait(0) => Conn_WAIT
);
mdm_0: component mb_design_1_mdm_0_0
port map (
Dbg_Capture_0 => mdm_0_MBDEBUG_0_CAPTURE,
Dbg_Clk_0 => mdm_0_MBDEBUG_0_CLK,
Dbg_Disable_0 => mdm_0_MBDEBUG_0_DISABLE,
Dbg_Reg_En_0(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
Dbg_Rst_0 => mdm_0_MBDEBUG_0_RST,
Dbg_Shift_0 => mdm_0_MBDEBUG_0_SHIFT,
Dbg_TDI_0 => mdm_0_MBDEBUG_0_TDI,
Dbg_TDO_0 => mdm_0_MBDEBUG_0_TDO,
Dbg_Update_0 => mdm_0_MBDEBUG_0_UPDATE,
Debug_SYS_Rst => mdm_0_Debug_SYS_Rst,
Interrupt => NLW_mdm_0_Interrupt_UNCONNECTED,
S_AXI_ACLK => clk_wiz_0_clk_100mhz,
S_AXI_ARADDR(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
S_AXI_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S_AXI_ARREADY => axi_interconnect_0_M00_AXI_ARREADY,
S_AXI_ARVALID => axi_interconnect_0_M00_AXI_ARVALID,
S_AXI_AWADDR(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
S_AXI_AWREADY => axi_interconnect_0_M00_AXI_AWREADY,
S_AXI_AWVALID => axi_interconnect_0_M00_AXI_AWVALID,
S_AXI_BREADY => axi_interconnect_0_M00_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_0_M00_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
S_AXI_RREADY => axi_interconnect_0_M00_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_0_M00_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
S_AXI_WREADY => axi_interconnect_0_M00_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_0_M00_AXI_WVALID
);
microblaze_0: component mb_design_1_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
Clk => clk_wiz_0_clk_100mhz,
DCE => microblaze_0_DLMB_CE,
DReady => microblaze_0_DLMB_READY,
DUE => microblaze_0_DLMB_UE,
DWait => microblaze_0_DLMB_WAIT,
D_AS => microblaze_0_DLMB_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
Dbg_Capture => mdm_0_MBDEBUG_0_CAPTURE,
Dbg_Clk => mdm_0_MBDEBUG_0_CLK,
Dbg_Disable => mdm_0_MBDEBUG_0_DISABLE,
Dbg_Reg_En(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
Dbg_Shift => mdm_0_MBDEBUG_0_SHIFT,
Dbg_TDI => mdm_0_MBDEBUG_0_TDI,
Dbg_TDO => mdm_0_MBDEBUG_0_TDO,
Dbg_Update => mdm_0_MBDEBUG_0_UPDATE,
Debug_Rst => mdm_0_MBDEBUG_0_RST,
ICE => microblaze_0_ILMB_CE,
IFetch => microblaze_0_ILMB_READSTROBE,
IReady => microblaze_0_ILMB_READY,
IUE => microblaze_0_ILMB_UE,
IWAIT => microblaze_0_ILMB_WAIT,
I_AS => microblaze_0_ILMB_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
Interrupt => axi_intc_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => NLW_microblaze_0_Interrupt_Ack_UNCONNECTED(0 to 1),
Interrupt_Address(0 to 31) => B"00000000000000000000000000000000",
M_AXI_DP_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => S00_AXI_1_ARREADY(0),
M_AXI_DP_ARVALID => S00_AXI_1_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => S00_AXI_1_AWREADY(0),
M_AXI_DP_AWVALID => S00_AXI_1_AWVALID,
M_AXI_DP_BREADY => S00_AXI_1_BREADY,
M_AXI_DP_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
M_AXI_DP_BVALID => S00_AXI_1_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
M_AXI_DP_RREADY => S00_AXI_1_RREADY,
M_AXI_DP_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
M_AXI_DP_RVALID => S00_AXI_1_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
M_AXI_DP_WREADY => S00_AXI_1_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
M_AXI_DP_WVALID => S00_AXI_1_WVALID,
Read_Strobe => microblaze_0_DLMB_READSTROBE,
Reset => proc_sys_reset_0_mb_reset,
Write_Strobe => microblaze_0_DLMB_WRITESTROBE
);
proc_sys_reset_0: component mb_design_1_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => proc_sys_reset_0_bus_struct_reset(0),
dcm_locked => clk_wiz_0_locked,
ext_reset_in => reset_0_1,
interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_0_Debug_SYS_Rst,
mb_reset => proc_sys_reset_0_mb_reset,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => clk_wiz_0_clk_100mhz
);
xlconcat_0: component mb_design_1_xlconcat_0_0
port map (
In0(0) => axi_timer_0_interrupt,
dout(0) => xlconcat_0_dout(0)
);
end STRUCTURE;
microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd deleted 100644 → 0
View file @ e55b3b4a
--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--Date : Thu Mar 20 18:24:28 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1.bd
--Design : mb_design_1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_L30N86 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_L30N86;
architecture STRUCTURE of m00_couplers_imp_L30N86 is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1MV3QBS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1MV3QBS;
architecture STRUCTURE of m01_couplers_imp_1MV3QBS is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1CM8QGB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1CM8QGB;
architecture STRUCTURE of m02_couplers_imp_1CM8QGB is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_DKAE7P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_DKAE7P;
architecture STRUCTURE of m03_couplers_imp_DKAE7P is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_OP7ZFX is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_OP7ZFX;
architecture STRUCTURE of m04_couplers_imp_OP7ZFX is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1AM08ZQ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_1AM08ZQ;
architecture STRUCTURE of s00_couplers_imp_1AM08ZQ is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end mb_design_1_axi_interconnect_0_0;
architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
component mb_design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component mb_design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m04_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_axi_interconnect_0_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_axi_interconnect_0_AWVALID;
M02_AXI_bready <= m02_couplers_to_axi_interconnect_0_BREADY;
M02_AXI_rready <= m02_couplers_to_axi_interconnect_0_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_axi_interconnect_0_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_axi_interconnect_0_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_axi_interconnect_0_AWVALID;
M03_AXI_bready <= m03_couplers_to_axi_interconnect_0_BREADY;
M03_AXI_rready <= m03_couplers_to_axi_interconnect_0_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_axi_interconnect_0_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_axi_interconnect_0_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_axi_interconnect_0_AWVALID;
M04_AXI_bready <= m04_couplers_to_axi_interconnect_0_BREADY;
M04_AXI_rready <= m04_couplers_to_axi_interconnect_0_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= axi_interconnect_0_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= axi_interconnect_0_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= axi_interconnect_0_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_interconnect_0_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= axi_interconnect_0_to_s00_couplers_WREADY(0);
axi_interconnect_0_ACLK_net <= ACLK;
axi_interconnect_0_ARESETN_net <= ARESETN;
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
axi_interconnect_0_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
axi_interconnect_0_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
m02_couplers_to_axi_interconnect_0_ARREADY <= M02_AXI_arready;
m02_couplers_to_axi_interconnect_0_AWREADY <= M02_AXI_awready;
m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_axi_interconnect_0_BVALID <= M02_AXI_bvalid;
m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_axi_interconnect_0_RVALID <= M02_AXI_rvalid;
m02_couplers_to_axi_interconnect_0_WREADY <= M02_AXI_wready;
m03_couplers_to_axi_interconnect_0_ARREADY <= M03_AXI_arready;
m03_couplers_to_axi_interconnect_0_AWREADY <= M03_AXI_awready;
m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_BVALID <= M03_AXI_bvalid;
m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_RVALID <= M03_AXI_rvalid;
m03_couplers_to_axi_interconnect_0_WREADY <= M03_AXI_wready;
m04_couplers_to_axi_interconnect_0_ARREADY <= M04_AXI_arready;
m04_couplers_to_axi_interconnect_0_AWREADY <= M04_AXI_awready;
m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_axi_interconnect_0_BVALID <= M04_AXI_bvalid;
m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_axi_interconnect_0_RVALID <= M04_AXI_rvalid;
m04_couplers_to_axi_interconnect_0_WREADY <= M04_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_L30N86
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1MV3QBS
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1CM8QGB
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m02_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m02_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m02_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_DKAE7P
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m03_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m03_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m03_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_OP7ZFX
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m04_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m04_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m04_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
s00_couplers: entity work.s00_couplers_imp_1AM08ZQ
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN => axi_interconnect_0_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_interconnect_0_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => axi_interconnect_0_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => axi_interconnect_0_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => axi_interconnect_0_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => axi_interconnect_0_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => axi_interconnect_0_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => axi_interconnect_0_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_interconnect_0_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => axi_interconnect_0_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => axi_interconnect_0_to_s00_couplers_WVALID(0)
);
xbar: component mb_design_1_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net,
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0),
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0),
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mb_design_1 is
port (
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk_in1 : in STD_LOGIC;
hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=15,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of mb_design_1 : entity is "mb_design_1.hwdef";
end mb_design_1;
architecture STRUCTURE of mb_design_1 is
component mb_design_1_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC
);
end component mb_design_1_microblaze_0_0;
component mb_design_1_clk_wiz_0_0 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_100mhz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component mb_design_1_clk_wiz_0_0;
component mb_design_1_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mb_design_1_proc_sys_reset_0_0;
component mb_design_1_lmb_v10_0_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component mb_design_1_lmb_v10_0_0;
component mb_design_1_ilmb_v10_0_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component mb_design_1_ilmb_v10_0_0;
component mb_design_1_lmb_bram_if_cntlr_0_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component mb_design_1_lmb_bram_if_cntlr_0_0;
component mb_design_1_lmb_bram_if_cntlr_0_1 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component mb_design_1_lmb_bram_if_cntlr_0_1;
component mb_design_1_blk_mem_gen_0_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC
);
end component mb_design_1_blk_mem_gen_0_0;
component mb_design_1_mdm_0_0 is
port (
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
Interrupt : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
end component mb_design_1_mdm_0_0;
component mb_design_1_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component mb_design_1_axi_gpio_0_0;
component mb_design_1_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component mb_design_1_axi_timer_0_0;
component mb_design_1_axi_intc_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 0 to 0 );
irq : out STD_LOGIC
);
end component mb_design_1_axi_intc_0_0;
component mb_design_1_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mb_design_1_xlconcat_0_0;
component mb_design_1_axi4lite_hog_build_i_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component mb_design_1_axi4lite_hog_build_i_0_0;
signal Conn1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_ADDRSTROBE : STD_LOGIC;
signal Conn1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal Conn1_CE : STD_LOGIC;
signal Conn1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_READSTROBE : STD_LOGIC;
signal Conn1_READY : STD_LOGIC;
signal Conn1_UE : STD_LOGIC;
signal Conn1_WAIT : STD_LOGIC;
signal Conn1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_WRITESTROBE : STD_LOGIC;
signal Conn_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn_ADDRSTROBE : STD_LOGIC;
signal Conn_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal Conn_CE : STD_LOGIC;
signal Conn_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn_READSTROBE : STD_LOGIC;
signal Conn_READY : STD_LOGIC;
signal Conn_UE : STD_LOGIC;
signal Conn_WAIT : STD_LOGIC;
signal Conn_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn_WRITESTROBE : STD_LOGIC;
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_intc_0_interrupt_INTERRUPT : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M02_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_timer_0_interrupt : STD_LOGIC;
signal clk_in1_0_1 : STD_LOGIC;
signal clk_wiz_0_clk_100mhz : STD_LOGIC;
signal clk_wiz_0_locked : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal dlmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal dlmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal hog_global_date_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hog_global_sha_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hog_global_time_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hog_global_ver_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal mdm_0_Debug_SYS_Rst : STD_LOGIC;
signal mdm_0_MBDEBUG_0_CAPTURE : STD_LOGIC;
signal mdm_0_MBDEBUG_0_CLK : STD_LOGIC;
signal mdm_0_MBDEBUG_0_DISABLE : STD_LOGIC;
signal mdm_0_MBDEBUG_0_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal mdm_0_MBDEBUG_0_RST : STD_LOGIC;
signal mdm_0_MBDEBUG_0_SHIFT : STD_LOGIC;
signal mdm_0_MBDEBUG_0_TDI : STD_LOGIC;
signal mdm_0_MBDEBUG_0_TDO : STD_LOGIC;
signal mdm_0_MBDEBUG_0_UPDATE : STD_LOGIC;
signal microblaze_0_DLMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_DLMB_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_DLMB_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_DLMB_CE : STD_LOGIC;
signal microblaze_0_DLMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_DLMB_READSTROBE : STD_LOGIC;
signal microblaze_0_DLMB_READY : STD_LOGIC;
signal microblaze_0_DLMB_UE : STD_LOGIC;
signal microblaze_0_DLMB_WAIT : STD_LOGIC;
signal microblaze_0_DLMB_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_DLMB_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ILMB_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ILMB_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ILMB_CE : STD_LOGIC;
signal microblaze_0_ILMB_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ILMB_READSTROBE : STD_LOGIC;
signal microblaze_0_ILMB_READY : STD_LOGIC;
signal microblaze_0_ILMB_UE : STD_LOGIC;
signal microblaze_0_ILMB_WAIT : STD_LOGIC;
signal proc_sys_reset_0_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_mb_reset : STD_LOGIC;
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal reset_0_1 : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_mdm_0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_Interrupt_Ack_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 1 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr_0 : label is "byte 0x00000000 32 > mb_design_1 blk_mem_gen_0";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr_0 : label is "yes";
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > mb_design_1 dlmb_bram_if_cntlr_0";
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of clk_in1 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_IN1 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of clk_in1 : signal is "XIL_INTERFACENAME CLK.CLK_IN1, ASSOCIATED_RESET reset, CLK_DOMAIN mb_design_1_clk_in1_0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 RST.RESET RST";
attribute X_INTERFACE_PARAMETER of reset : signal is "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of GPIO_0_tri_o : signal is "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O";
begin
GPIO_0_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
clk_in1_0_1 <= clk_in1;
hog_global_date_i_0_1(31 downto 0) <= hog_global_date_i_0(31 downto 0);
hog_global_sha_i_0_1(31 downto 0) <= hog_global_sha_i_0(31 downto 0);
hog_global_time_i_0_1(31 downto 0) <= hog_global_time_i_0(31 downto 0);
hog_global_ver_i_0_1(31 downto 0) <= hog_global_ver_i_0(31 downto 0);
reset_0_1 <= reset;
axi4lite_hog_build_i_0: component mb_design_1_axi4lite_hog_build_i_0_0
port map (
hog_global_date_i(31 downto 0) => hog_global_date_i_0_1(31 downto 0),
hog_global_sha_i(31 downto 0) => hog_global_sha_i_0_1(31 downto 0),
hog_global_time_i(31 downto 0) => hog_global_time_i_0_1(31 downto 0),
hog_global_ver_i(31 downto 0) => hog_global_ver_i_0_1(31 downto 0),
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M04_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
s_axi_awready => axi_interconnect_0_M04_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M04_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M04_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M04_AXI_WVALID
);
axi_gpio_0: component mb_design_1_axi_gpio_0_0
port map (
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M01_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
s_axi_awready => axi_interconnect_0_M01_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M01_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M01_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
axi_intc_0: component mb_design_1_axi_intc_0_0
port map (
intr(0) => xlconcat_0_dout(0),
irq => axi_intc_0_interrupt_INTERRUPT,
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(8 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(8 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(8 downto 0),
s_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
port map (
ACLK => clk_wiz_0_clk_100mhz,
ARESETN => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => clk_wiz_0_clk_100mhz,
M00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => clk_wiz_0_clk_100mhz,
M01_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => axi_interconnect_0_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
M02_ACLK => clk_wiz_0_clk_100mhz,
M02_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => axi_interconnect_0_M02_AXI_ARREADY,
M02_AXI_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => axi_interconnect_0_M02_AXI_AWREADY,
M02_AXI_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
M02_AXI_bready => axi_interconnect_0_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => axi_interconnect_0_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => axi_interconnect_0_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => axi_interconnect_0_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => axi_interconnect_0_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_100mhz,
M03_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
M04_ACLK => clk_wiz_0_clk_100mhz,
M04_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_100mhz,
S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arready(0) => S00_AXI_1_ARREADY(0),
S00_AXI_arvalid(0) => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awready(0) => S00_AXI_1_AWREADY(0),
S00_AXI_awvalid(0) => S00_AXI_1_AWVALID,
S00_AXI_bready(0) => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid(0) => S00_AXI_1_BVALID(0),
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rready(0) => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid(0) => S00_AXI_1_RVALID(0),
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wready(0) => S00_AXI_1_WREADY(0),
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => S00_AXI_1_WVALID
);
axi_timer_0: component mb_design_1_axi_timer_0_0
port map (
capturetrig0 => '0',
capturetrig1 => '0',
freeze => '0',
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => clk_wiz_0_clk_100mhz,
s_axi_araddr(4 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(4 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
s_axi_awaddr(4 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(4 downto 0),
s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
blk_mem_gen_0: component mb_design_1_blk_mem_gen_0_0
port map (
addra(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
addra(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
addra(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
addra(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
addra(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
addra(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
addra(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
addra(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
addra(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
addra(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
addra(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
addra(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
addra(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
addra(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
addra(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
addra(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
addra(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
addra(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
addra(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
addra(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
addra(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
addra(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
addra(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
addra(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
addra(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
addra(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
addra(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
addra(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
addra(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
addra(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
addra(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
addra(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
addrb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0),
addrb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(1),
addrb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(2),
addrb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(3),
addrb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(4),
addrb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(5),
addrb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(6),
addrb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(7),
addrb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(8),
addrb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(9),
addrb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(10),
addrb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(11),
addrb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(12),
addrb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(13),
addrb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(14),
addrb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(15),
addrb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(16),
addrb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(17),
addrb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(18),
addrb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(19),
addrb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(20),
addrb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(21),
addrb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(22),
addrb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(23),
addrb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(24),
addrb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(25),
addrb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(26),
addrb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(27),
addrb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(28),
addrb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(29),
addrb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(30),
addrb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(31),
clka => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
clkb => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
dina(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
dina(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
dina(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
dina(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
dina(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
dina(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
dina(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
dina(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
dina(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
dina(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
dina(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
dina(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
dina(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
dina(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
dina(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
dina(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
dina(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
dina(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
dina(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
dina(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
dina(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
dina(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
dina(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
dina(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
dina(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
dina(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
dina(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
dina(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
dina(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
dina(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
dina(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
dina(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
dinb(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0),
dinb(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(1),
dinb(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(2),
dinb(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(3),
dinb(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(4),
dinb(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(5),
dinb(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(6),
dinb(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(7),
dinb(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(8),
dinb(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(9),
dinb(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(10),
dinb(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(11),
dinb(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(12),
dinb(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(13),
dinb(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(14),
dinb(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(15),
dinb(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(16),
dinb(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(17),
dinb(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(18),
dinb(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(19),
dinb(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(20),
dinb(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(21),
dinb(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(22),
dinb(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(23),
dinb(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(24),
dinb(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(25),
dinb(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(26),
dinb(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(27),
dinb(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(28),
dinb(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(29),
dinb(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(30),
dinb(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(31),
douta(31 downto 0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
doutb(31 downto 0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31 downto 0),
ena => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
enb => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
rsta => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
rsta_busy => NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED,
rstb => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
rstb_busy => NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED,
wea(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
wea(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
wea(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
wea(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(3),
web(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0),
web(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(1),
web(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(2),
web(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(3)
);
clk_wiz_0: component mb_design_1_clk_wiz_0_0
port map (
clk_100mhz => clk_wiz_0_clk_100mhz,
clk_in1 => clk_in1_0_1,
locked => clk_wiz_0_locked,
reset => reset_0_1
);
dlmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_0
port map (
BRAM_Addr_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
BRAM_Clk_A => dlmb_bram_if_cntlr_0_BRAM_PORT_CLK,
BRAM_Din_A(0) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
BRAM_Din_A(1) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
BRAM_Din_A(2) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
BRAM_Din_A(3) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
BRAM_Din_A(4) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
BRAM_Din_A(5) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
BRAM_Din_A(6) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
BRAM_Din_A(7) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
BRAM_Din_A(8) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
BRAM_Din_A(9) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
BRAM_Din_A(10) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
BRAM_Din_A(11) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
BRAM_Din_A(12) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
BRAM_Din_A(13) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
BRAM_Din_A(14) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
BRAM_Din_A(15) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
BRAM_Din_A(16) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
BRAM_Din_A(17) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
BRAM_Din_A(18) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
BRAM_Din_A(19) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
BRAM_Din_A(20) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
BRAM_Din_A(21) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
BRAM_Din_A(22) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
BRAM_Din_A(23) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
BRAM_Din_A(24) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
BRAM_Din_A(25) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
BRAM_Din_A(26) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
BRAM_Din_A(27) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
BRAM_Din_A(28) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
BRAM_Din_A(29) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
BRAM_Din_A(30) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
BRAM_Din_A(31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
BRAM_Dout_A(0 to 31) => dlmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
BRAM_EN_A => dlmb_bram_if_cntlr_0_BRAM_PORT_EN,
BRAM_Rst_A => dlmb_bram_if_cntlr_0_BRAM_PORT_RST,
BRAM_WEN_A(0 to 3) => dlmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
LMB_AddrStrobe => Conn1_ADDRSTROBE,
LMB_BE(0 to 3) => Conn1_BE(0 to 3),
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadStrobe => Conn1_READSTROBE,
LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn1_WRITESTROBE,
Sl_CE => Conn1_CE,
Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
Sl_Ready => Conn1_READY,
Sl_UE => Conn1_UE,
Sl_Wait => Conn1_WAIT
);
dlmb_v10_0: component mb_design_1_ilmb_v10_0_0
port map (
LMB_ABus(0 to 31) => Conn1_ABUS(0 to 31),
LMB_AddrStrobe => Conn1_ADDRSTROBE,
LMB_BE(0 to 3) => Conn1_BE(0 to 3),
LMB_CE => microblaze_0_DLMB_CE,
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadDBus(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
LMB_ReadStrobe => Conn1_READSTROBE,
LMB_Ready => microblaze_0_DLMB_READY,
LMB_Rst => NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_DLMB_UE,
LMB_Wait => microblaze_0_DLMB_WAIT,
LMB_WriteDBus(0 to 31) => Conn1_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn1_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_DLMB_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_DLMB_READSTROBE,
M_WriteStrobe => microblaze_0_DLMB_WRITESTROBE,
SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
Sl_CE(0) => Conn1_CE,
Sl_DBus(0 to 31) => Conn1_READDBUS(0 to 31),
Sl_Ready(0) => Conn1_READY,
Sl_UE(0) => Conn1_UE,
Sl_Wait(0) => Conn1_WAIT
);
ilmb_bram_if_cntlr_0: component mb_design_1_lmb_bram_if_cntlr_0_1
port map (
BRAM_Addr_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR(0 to 31),
BRAM_Clk_A => ilmb_bram_if_cntlr_0_BRAM_PORT_CLK,
BRAM_Din_A(0) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(31),
BRAM_Din_A(1) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(30),
BRAM_Din_A(2) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(29),
BRAM_Din_A(3) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(28),
BRAM_Din_A(4) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(27),
BRAM_Din_A(5) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(26),
BRAM_Din_A(6) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(25),
BRAM_Din_A(7) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(24),
BRAM_Din_A(8) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(23),
BRAM_Din_A(9) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(22),
BRAM_Din_A(10) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(21),
BRAM_Din_A(11) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(20),
BRAM_Din_A(12) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(19),
BRAM_Din_A(13) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(18),
BRAM_Din_A(14) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(17),
BRAM_Din_A(15) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(16),
BRAM_Din_A(16) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(15),
BRAM_Din_A(17) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(14),
BRAM_Din_A(18) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(13),
BRAM_Din_A(19) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(12),
BRAM_Din_A(20) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(11),
BRAM_Din_A(21) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(10),
BRAM_Din_A(22) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(9),
BRAM_Din_A(23) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(8),
BRAM_Din_A(24) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(7),
BRAM_Din_A(25) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(6),
BRAM_Din_A(26) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(5),
BRAM_Din_A(27) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(4),
BRAM_Din_A(28) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(3),
BRAM_Din_A(29) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(2),
BRAM_Din_A(30) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(1),
BRAM_Din_A(31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DOUT(0),
BRAM_Dout_A(0 to 31) => ilmb_bram_if_cntlr_0_BRAM_PORT_DIN(0 to 31),
BRAM_EN_A => ilmb_bram_if_cntlr_0_BRAM_PORT_EN,
BRAM_Rst_A => ilmb_bram_if_cntlr_0_BRAM_PORT_RST,
BRAM_WEN_A(0 to 3) => ilmb_bram_if_cntlr_0_BRAM_PORT_WE(0 to 3),
LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
LMB_AddrStrobe => Conn_ADDRSTROBE,
LMB_BE(0 to 3) => Conn_BE(0 to 3),
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadStrobe => Conn_READSTROBE,
LMB_Rst => proc_sys_reset_0_bus_struct_reset(0),
LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn_WRITESTROBE,
Sl_CE => Conn_CE,
Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
Sl_Ready => Conn_READY,
Sl_UE => Conn_UE,
Sl_Wait => Conn_WAIT
);
ilmb_v10_0: component mb_design_1_lmb_v10_0_0
port map (
LMB_ABus(0 to 31) => Conn_ABUS(0 to 31),
LMB_AddrStrobe => Conn_ADDRSTROBE,
LMB_BE(0 to 3) => Conn_BE(0 to 3),
LMB_CE => microblaze_0_ILMB_CE,
LMB_Clk => clk_wiz_0_clk_100mhz,
LMB_ReadDBus(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
LMB_ReadStrobe => Conn_READSTROBE,
LMB_Ready => microblaze_0_ILMB_READY,
LMB_Rst => NLW_ilmb_v10_0_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ILMB_UE,
LMB_Wait => microblaze_0_ILMB_WAIT,
LMB_WriteDBus(0 to 31) => Conn_WRITEDBUS(0 to 31),
LMB_WriteStrobe => Conn_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ILMB_ADDRSTROBE,
M_BE(0 to 3) => B"0000",
M_DBus(0 to 31) => B"00000000000000000000000000000000",
M_ReadStrobe => microblaze_0_ILMB_READSTROBE,
M_WriteStrobe => '0',
SYS_Rst => proc_sys_reset_0_bus_struct_reset(0),
Sl_CE(0) => Conn_CE,
Sl_DBus(0 to 31) => Conn_READDBUS(0 to 31),
Sl_Ready(0) => Conn_READY,
Sl_UE(0) => Conn_UE,
Sl_Wait(0) => Conn_WAIT
);
mdm_0: component mb_design_1_mdm_0_0
port map (
Dbg_Capture_0 => mdm_0_MBDEBUG_0_CAPTURE,
Dbg_Clk_0 => mdm_0_MBDEBUG_0_CLK,
Dbg_Disable_0 => mdm_0_MBDEBUG_0_DISABLE,
Dbg_Reg_En_0(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
Dbg_Rst_0 => mdm_0_MBDEBUG_0_RST,
Dbg_Shift_0 => mdm_0_MBDEBUG_0_SHIFT,
Dbg_TDI_0 => mdm_0_MBDEBUG_0_TDI,
Dbg_TDO_0 => mdm_0_MBDEBUG_0_TDO,
Dbg_Update_0 => mdm_0_MBDEBUG_0_UPDATE,
Debug_SYS_Rst => mdm_0_Debug_SYS_Rst,
Interrupt => NLW_mdm_0_Interrupt_UNCONNECTED,
S_AXI_ACLK => clk_wiz_0_clk_100mhz,
S_AXI_ARADDR(3 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(3 downto 0),
S_AXI_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S_AXI_ARREADY => axi_interconnect_0_M00_AXI_ARREADY,
S_AXI_ARVALID => axi_interconnect_0_M00_AXI_ARVALID,
S_AXI_AWADDR(3 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(3 downto 0),
S_AXI_AWREADY => axi_interconnect_0_M00_AXI_AWREADY,
S_AXI_AWVALID => axi_interconnect_0_M00_AXI_AWVALID,
S_AXI_BREADY => axi_interconnect_0_M00_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_0_M00_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
S_AXI_RREADY => axi_interconnect_0_M00_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_0_M00_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
S_AXI_WREADY => axi_interconnect_0_M00_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_0_M00_AXI_WVALID
);
microblaze_0: component mb_design_1_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_DLMB_BE(0 to 3),
Clk => clk_wiz_0_clk_100mhz,
DCE => microblaze_0_DLMB_CE,
DReady => microblaze_0_DLMB_READY,
DUE => microblaze_0_DLMB_UE,
DWait => microblaze_0_DLMB_WAIT,
D_AS => microblaze_0_DLMB_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_DLMB_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_DLMB_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_DLMB_WRITEDBUS(0 to 31),
Dbg_Capture => mdm_0_MBDEBUG_0_CAPTURE,
Dbg_Clk => mdm_0_MBDEBUG_0_CLK,
Dbg_Disable => mdm_0_MBDEBUG_0_DISABLE,
Dbg_Reg_En(0 to 7) => mdm_0_MBDEBUG_0_REG_EN(0 to 7),
Dbg_Shift => mdm_0_MBDEBUG_0_SHIFT,
Dbg_TDI => mdm_0_MBDEBUG_0_TDI,
Dbg_TDO => mdm_0_MBDEBUG_0_TDO,
Dbg_Update => mdm_0_MBDEBUG_0_UPDATE,
Debug_Rst => mdm_0_MBDEBUG_0_RST,
ICE => microblaze_0_ILMB_CE,
IFetch => microblaze_0_ILMB_READSTROBE,
IReady => microblaze_0_ILMB_READY,
IUE => microblaze_0_ILMB_UE,
IWAIT => microblaze_0_ILMB_WAIT,
I_AS => microblaze_0_ILMB_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ILMB_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ILMB_ABUS(0 to 31),
Interrupt => axi_intc_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => NLW_microblaze_0_Interrupt_Ack_UNCONNECTED(0 to 1),
Interrupt_Address(0 to 31) => B"00000000000000000000000000000000",
M_AXI_DP_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => S00_AXI_1_ARREADY(0),
M_AXI_DP_ARVALID => S00_AXI_1_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => S00_AXI_1_AWREADY(0),
M_AXI_DP_AWVALID => S00_AXI_1_AWVALID,
M_AXI_DP_BREADY => S00_AXI_1_BREADY,
M_AXI_DP_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
M_AXI_DP_BVALID => S00_AXI_1_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
M_AXI_DP_RREADY => S00_AXI_1_RREADY,
M_AXI_DP_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
M_AXI_DP_RVALID => S00_AXI_1_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
M_AXI_DP_WREADY => S00_AXI_1_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
M_AXI_DP_WVALID => S00_AXI_1_WVALID,
Read_Strobe => microblaze_0_DLMB_READSTROBE,
Reset => proc_sys_reset_0_mb_reset,
Write_Strobe => microblaze_0_DLMB_WRITESTROBE
);
proc_sys_reset_0: component mb_design_1_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => proc_sys_reset_0_bus_struct_reset(0),
dcm_locked => clk_wiz_0_locked,
ext_reset_in => reset_0_1,
interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_0_Debug_SYS_Rst,
mb_reset => proc_sys_reset_0_mb_reset,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => clk_wiz_0_clk_100mhz
);
xlconcat_0: component mb_design_1_xlconcat_0_0
port map (
In0(0) => axi_timer_0_interrupt,
dout(0) => xlconcat_0_dout(0)
);
end STRUCTURE;
microblaze-demo/microblaze-demo.srcs/sim_1/new/dummy_simu.vhd 0 → 100644
View file @ c10d4808
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/10/2025 07:21:40 AM
-- Design Name:
-- Module Name: dummy_simu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use std.textio.all;
entity dummy_simu is
Generic (
-- Global Generic Variables
GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_VER : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_SHA : std_logic_vector(31 downto 0) := (others => '0')
);
end dummy_simu;
architecture Behavioral of dummy_simu is
begin
assert false
report "GLOBAL_DATE: " & to_hstring(to_bitvector(GLOBAL_DATE))
severity note;
assert false
report "GLOBAL_TIME: " & to_hstring(to_bitvector(GLOBAL_TIME))
severity note;
assert false
report "GLOBAL_VER: " & to_hstring(to_bitvector(GLOBAL_VER))
severity note;
assert false
report "GLOBAL_SHA: " & to_hstring(to_bitvector(GLOBAL_SHA))
severity note;
end Behavioral;
microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
View file @ c10d4808
......@@ -8,11 +8,11 @@
"gen_directory": "../../../../../../microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0",
"parameters": {
"component_parameters": {
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_ADDR_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "mb_design_1_axi4lite_hog_build_i_0_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ]
"C_ADDR_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "artix7" } ],
......@@ -72,32 +72,32 @@
"mode": "slave",
"memory_map_ref": "s_axi",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
......@@ -146,7 +146,7 @@
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
......