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# This page is under construction!
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In this page you will find a description and all the technical documentation related to the SCALP platform.
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# SCALP: Self-configurable 3-D Cellular multi-FPGA Adaptive Platform.
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Parallel computation has appeared as the most promising technique to circumvent the limitations imposed by power consumption in order to continue increasing computation power, making thus manycore architectures a promising computer organization approach. Interconnecting and coordinating such high amount of computation nodes in an efficient manner is a hot research topic, several approaches to Network-on-chip architectures propose solutions for this. SCALP is a 3D multi-FPGA hardware platform permitting to prototype 3D NoC architectures with dynamic topologies.
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We intend to use it to prototype self-adaptive and self-organizing hardware architectures in which the computation performed by a node and the interconnections between these nodes can be dynamically modified, being these modifications triggered by the platform itself. However, SCALP can be used as an implementation testbed in several domains. Routing algorithms, cellular computation, scalable neural architectures, distributed computation, asynchonous systems, are just a few examples. Some of the features to be tackled by the systems implemented with SCALP are scalability, enhanced reconfigurability and distributedness.
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## The SCALP node
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The SCALP node is mainly composed of a Xilinx Zynq SoC( dual-core ARM Cortex-A9 @866~MHz + Artix-7 programmable logic with 74,000~cells), 2~Gb DDR3 SDRAM, a 5-port Ethernet switch, a PLL .
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<div align="center">
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<img src=uploads/da8a1a3710fb28f9380f0bd24ecda8e4/SCALP_top.jpg alt="SCALP_top" width=600>
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</div>
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## The SCALP base board
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The base board provides power supply for a SCALP node or a stack of nodes. It also contains an Ethernet phy permitting to access the Ethernet switch on the SCALP board, a MIPI interface, and an USB OTG.
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<div align="center">
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![stack_1x1x1](uploads/3aae2f3ba704ce396450e648e4e8f114/stack_1x1x1.jpg)
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</div>
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## Interconnectivity
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Each SCALP node has been designed to communicate with its four neighbors in a two dimensional grid through 4~high-speed serial interfaces capable to sustain data rates up to 6.25~Gb/s. The architecture also foresees serial links to the top and bottom modules, implemented with differential pairs LVDS allowing to reach data rates up to 928~Mb/s in both directions.
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<div align="center">
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![stack_stair_2x2x4](uploads/d04a148bb459b14b9024e9e057bc213f/stack_stair_2x2x4.jpg)
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</div>
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## NoC prototyping platform
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The stacking architecture permits to build arbitrary 3D grid multi-FPGA topologies. A routing algorithm (implemented in the FPGA) permits to communicate between remote nodes thanks by means of unicast, broadacst and reduce mecanisms.
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<!--- ![scalp_20](uploads/2acea5c9de6c2ae32e44d8c337ca4d8e/scalp_20.jpeg) --->
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<!--- ![scalp_29](uploads/81cf4d83c0cd1b0a49c42c6ec0480d9d/scalp_29.jpeg) --->
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<!--- ![scalp_33](uploads/969600e01e555359aa5528961079339a/scalp_33.jpeg) --->
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<!--- ![scalp_34](uploads/b75c26b0337d386470493c32cafdaf1d/scalp_34.jpeg) --->
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<div align="center">
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![stack_3x3x3_two_boards](uploads/75b3ba1fe3b726fd964999dad1591ee3/stack_3x3x3_two_boards.jpg)
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</div> |