Updated HDL template

config/scalp_fast_router_registers.json

 {
     "config" : {
         "entity_name"            : "scalp_fast_router_registers",
-        "entity_version"         : "1.4",
+        "entity_version"         : "1.6",
         "entity_reg_io_access"   : true,
         "block_name"             : "ScalpFastRouterRegisters",
         "bd_name"                : "/scalp_axi4lite_0/SAXILitexDIO",
@@ -123,7 +123,26 @@
         },
         {
             "register_status_active" : true,
-            "register_name"          : "QoSDMAInitOcpCtrl",
+            "register_name"          : "QoSDMAInitSetOcpCtrl",
+            "register_size"          : "32",
+            "register_type"          : "ocp",
+            "register_access_mode"   : "wo",
+            "register_multifield"    : true,
+            "register_initial_value" : 0,
+            "register_fields"        : {
+                "NORTH"              : 1,
+                "EAST"               : 1,
+                "SOUTH"              : 1,
+                "WEST"               : 1,
+                "TOP"                : 1,
+                "BOTTOM"             : 1,
+                "LOCAL"              : 1,
+                "RESERVED"           : 25
+            }   
+        },
+        {
+            "register_status_active" : true,
+            "register_name"          : "QoSDMAInitClrOcpCtrl",
             "register_size"          : "32",
             "register_type"          : "ocp",
             "register_access_mode"   : "wo",

src/templates/hdl/template_regbank.vhd

@@ -129,7 +129,7 @@ begin
         SAxiBValidxAS  : SAxiBValidxSO                              <= SAxiBValidxS;
         SAxiWReadyxAS  : SAxiWReadyxSO                              <= SAxiWReadyxS;
         SAxiAWReadyxAS : SAxiAWReadyxSO                             <= SAxiAWReadyxS;
-        WrValidxAS     : WrValidxS                                  <= SAxiWValidxSI and not SAxiAWValidxSI;;
+        WrValidxAS     : WrValidxS                                  <= SAxiWValidxSI and not SAxiAWValidxSI;
         WrDataxAS      : WrDataxD                                   <= SAxiWDataxDI;
         WrAddrOutxAS   : WrAddrxD                                   <= WrAddrxDP;
         WrAddrxAS      : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when