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Commit d47775f0 authored by joachim.schmidt's avatar joachim.schmidt
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Updated HDL template

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config/scalp_fast_router_registers.json
+ 21
− 2
View file @ d47775f0
{ {
"config" : { "config" : {
"entity_name" : "scalp_fast_router_registers", "entity_name" : "scalp_fast_router_registers",
"entity_version" : "1.4", "entity_version" : "1.6",
"entity_reg_io_access" : true, "entity_reg_io_access" : true,
"block_name" : "ScalpFastRouterRegisters", "block_name" : "ScalpFastRouterRegisters",
"bd_name" : "/scalp_axi4lite_0/SAXILitexDIO", "bd_name" : "/scalp_axi4lite_0/SAXILitexDIO",
...@@ -123,7 +123,26 @@ ...@@ -123,7 +123,26 @@
}, },
{ {
"register_status_active" : true, "register_status_active" : true,
"register_name" : "QoSDMAInitOcpCtrl", "register_name" : "QoSDMAInitSetOcpCtrl",
"register_size" : "32",
"register_type" : "ocp",
"register_access_mode" : "wo",
"register_multifield" : true,
"register_initial_value" : 0,
"register_fields" : {
"NORTH" : 1,
"EAST" : 1,
"SOUTH" : 1,
"WEST" : 1,
"TOP" : 1,
"BOTTOM" : 1,
"LOCAL" : 1,
"RESERVED" : 25
}
},
{
"register_status_active" : true,
"register_name" : "QoSDMAInitClrOcpCtrl",
"register_size" : "32", "register_size" : "32",
"register_type" : "ocp", "register_type" : "ocp",
"register_access_mode" : "wo", "register_access_mode" : "wo",
......
output/scalp_fast_router_registers/1.6/src/hdl/scalp_fast_router_registers.vhd 0 → 100644
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− 0
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-- THIS IS AN AUTOGENERATED FILE. DO NOT EDIT THIS FILE DIRECTLY.
-- scalp_regedit v0.1 - 05.2021
-- Author : Joachim Schmidt <joachim.schmidt@hesge.ch>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity scalp_fast_router_registers is
generic (
C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32;
C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32;
C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
C_AXI4_ADDR_SIZE : integer range 0 to 32 := 12;
C_AXI4_DATA_SIZE : integer range 0 to 32 := 32);
port (
-- Clock and reset
SAxiClkxCI : in std_ulogic;
SAxiRstxRANI : in std_ulogic;
-- AXI4 Lite
-- Read Channel
-- Read Address Channel
SAxiARAddrxDI : in std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
SAxiARValidxSI : in std_ulogic;
SAxiARReadyxSO : out std_ulogic;
-- Read Data Channel
SAxiRDataxDO : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
SAxiRRespxDO : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
SAxiRValidxSO : out std_ulogic;
SAxiRReadyxSI : in std_ulogic;
-- Write Channel
-- Write Address Channel
SAxiAWAddrxDI : in std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
SAxiAWValidxSI : in std_ulogic;
SAxiAWReadyxSO : out std_ulogic;
-- Write Data Channel
SAxiWDataxDI : in std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
SAxiWStrbxDI : in std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
SAxiWValidxSI : in std_ulogic;
SAxiWReadyxSO : out std_ulogic;
-- Write Response Channel
SAxiBRespxDO : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
SAxiBValidxSO : out std_ulogic;
SAxiBReadyxSI : in std_ulogic;
-- Registers list IO
LocalNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
RGBLed0xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
RGBLed1xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoTXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoTXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoTXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSDMAInitSetOcpCtrlxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSDMAInitClrOcpCtrlxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSDMAInitStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
end scalp_fast_router_registers;
architecture behavioral of scalp_fast_router_registers is
-- Constants
constant C_AXI4_RRESP_OKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
constant C_AXI4_BRESP_OKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_BRESP_EXOKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_BRESP_SLVERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_BRESP_DECERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
-- Signals
-- Clock and reset
signal SAxiClkxC : std_ulogic := '0';
signal SAxiRstxRAN : std_ulogic := '0';
-- AXI4 Lite
signal SAxiARReadyxS : std_ulogic := '0';
signal SAxiRValidxS : std_ulogic := '0';
signal SAxiBValidxS : std_ulogic := '0';
signal SAxiWReadyxS : std_ulogic := '0';
signal SAxiAWReadyxS : std_ulogic := '0';
signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- Signals of access to the register bank
signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RdValidxS : std_ulogic := '0';
signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal WrValidxS : std_ulogic := '0';
-- Registers list
signal LocalNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal LocalNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed0PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed0PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed1PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed1PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSPhyStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSPhyStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitSetOcpCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitSetOcpCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitClrOcpCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitClrOcpCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
-- Attributes
attribute mark_debug : string;
attribute keep : string;
--
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
begin
assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
report "RDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
report "ARADDR and ADDR vectors must be the same" severity failure;
assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
report "WDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
EntityIOxB : block is
begin -- block EntityIOxB
-- Clock and reset
SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
-- Read Channel
SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
RdValidxAS : RdValidxS <= SAxiARValidxSI;
RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
-- Write Channel
SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
WrValidxAS : WrValidxS <= SAxiWValidxSI and not SAxiAWValidxSI;
WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
SAxiAWValidxSI = '1' else
WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
end block EntityIOxB;
AXI4LitexB : block is
begin -- block AXI4LitexB
ReadChannelxB : block is
begin -- block ReadChannelxB
ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
variable StateAfterResetxS : boolean := true;
begin -- process ReadAddrChanxP
if SAxiRstxRAN = '0' then
SAxiARReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxC) then
if StateAfterResetxS = true then
SAxiARReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiARReadyxS <= SAxiARReadyxS;
end if;
if SAxiARValidxSI = '1' then
SAxiARReadyxS <= '0';
end if;
if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
SAxiARReadyxS <= '1';
end if;
end if;
end process ReadAddrChanxP;
ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process ReadDataChanxP
if SAxiRstxRAN = '0' then
SAxiRValidxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiRValidxS <= SAxiRValidxS;
if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
SAxiRValidxS <= '1';
end if;
if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
SAxiRValidxS <= '0';
end if;
end if;
end process ReadDataChanxP;
end block ReadChannelxB;
WriteChannelxB : block is
begin --block WriteChannelxB
WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WrAddrRegxP
if SAxiRstxRAN = '0' then
WrAddrxDP <= (others => '0');
elsif rising_edge(SAxiClkxC) then
WrAddrxDP <= WrAddrxDN;
end if;
end process WrAddrRegxP;
WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
variable StateAfterResetxS : boolean := true;
begin -- process WriteAddrChanxP
if SAxiRstxRAN = '0' then
SAxiAWReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxC) then
if StateAfterResetxS = true then
SAxiAWReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiAWReadyxS <= SAxiAWReadyxS;
end if;
if SAxiAWValidxSI = '1' then
SAxiAWReadyxS <= '0';
end if;
if SAxiWValidxSI = '1' then
SAxiAWReadyxS <= '1';
end if;
end if;
end process WriteAddrChanxP;
WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WriteDataChanxP
if SAxiRstxRAN = '0' then
SAxiWReadyxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiWReadyxS <= SAxiWReadyxS;
if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
SAxiWReadyxS <= '1';
end if;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiWReadyxS <= '0';
end if;
end if;
end process WriteDataChanxP;
WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WriteRespChanxP
if SAxiRstxRAN = '0' then
SAxiBValidxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiBValidxS <= SAxiBValidxS;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiBValidxS <= '1';
end if;
if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
SAxiBValidxS <= '0';
end if;
end if;
end process WriteRespChanxP;
end block WriteChannelxB;
end block AXI4LitexB;
ScalpFastRouterRegistersxB : block is
begin -- block ScalpFastRouterRegistersxB
WriteRegPortxP : process (DMAFifoRXRrDataCntxDI, DMAFifoRXStatusxDI,
DMAFifoRXWrDataCntxDI, DMAFifoTXRrDataCntxDI,
DMAFifoTXStatusxDI, DMAFifoTXWrDataCntxDI,
LocalNetAddrPortxDP,
QoSDMAInitClrOcpCtrlPortxDP,
QoSDMAInitSetOcpCtrlPortxDP,
QoSDMAInitStatusxDI, QoSPhyStatusxDI,
RGBLed0PortxDP, RGBLed1PortxDP, WrAddrxD,
WrDataxD, WrValidxS) is
begin -- process WriteRegPortxP
LocalNetAddrPortxDN <= LocalNetAddrPortxDP;
LocalNetAddrxDO <= LocalNetAddrPortxDP;
RGBLed0PortxDN <= RGBLed0PortxDP;
RGBLed0xDO <= RGBLed0PortxDP;
RGBLed1PortxDN <= RGBLed1PortxDP;
RGBLed1xDO <= RGBLed1PortxDP;
DMAFifoTXWrDataCntPortxDN <= DMAFifoTXWrDataCntxDI;
DMAFifoTXRrDataCntPortxDN <= DMAFifoTXRrDataCntxDI;
DMAFifoTXStatusPortxDN <= DMAFifoTXStatusxDI;
DMAFifoRXWrDataCntPortxDN <= DMAFifoRXWrDataCntxDI;
DMAFifoRXRrDataCntPortxDN <= DMAFifoRXRrDataCntxDI;
DMAFifoRXStatusPortxDN <= DMAFifoRXStatusxDI;
QoSPhyStatusPortxDN <= QoSPhyStatusxDI;
QoSDMAInitSetOcpCtrlPortxDN <= (others => '0');
QoSDMAInitSetOcpCtrlxDO <= QoSDMAInitSetOcpCtrlPortxDP;
QoSDMAInitClrOcpCtrlPortxDN <= (others => '0');
QoSDMAInitClrOcpCtrlxDO <= QoSDMAInitClrOcpCtrlPortxDP;
QoSDMAInitStatusPortxDN <= QoSDMAInitStatusxDI;
if WrValidxS = '1' then
case WrAddrxD is
when x"000" => LocalNetAddrPortxDN <= WrDataxD;
when x"004" => RGBLed0PortxDN <= WrDataxD;
when x"008" => RGBLed1PortxDN <= WrDataxD;
when x"028" => QoSDMAInitSetOcpCtrlPortxDN <= WrDataxD;
when x"02C" => QoSDMAInitClrOcpCtrlPortxDN <= WrDataxD;
when others => null;
end case;
end if;
end process WriteRegPortxP;
ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process ReadRegPortxP
if SAxiRstxRAN = '0' then
RdDataxD <= (others => '0');
elsif rising_edge(SAxiClkxC) then
RdDataxD <= RdDataxD;
if RdValidxS = '1' then
case RdAddrxD is
when x"000" => RdDataxD <= LocalNetAddrPortxDP;
when x"004" => RdDataxD <= RGBLed0PortxDP;
when x"008" => RdDataxD <= RGBLed1PortxDP;
when x"00C" => RdDataxD <= DMAFifoTXWrDataCntPortxDP;
when x"010" => RdDataxD <= DMAFifoTXRrDataCntPortxDP;
when x"014" => RdDataxD <= DMAFifoTXStatusPortxDP;
when x"018" => RdDataxD <= DMAFifoRXWrDataCntPortxDP;
when x"01C" => RdDataxD <= DMAFifoRXRrDataCntPortxDP;
when x"020" => RdDataxD <= DMAFifoRXStatusPortxDP;
when x"024" => RdDataxD <= QoSPhyStatusPortxDP;
when x"030" => RdDataxD <= QoSDMAInitStatusPortxDP;
when others => RdDataxD <= (others => '0');
end case;
end if;
end if;
end process ReadRegPortxP;
UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process UpdateRegBankxP
if SAxiRstxRAN = '0' then
LocalNetAddrPortxDP <= x"00000000";
RGBLed0PortxDP <= x"00000000";
RGBLed1PortxDP <= x"00000000";
DMAFifoTXWrDataCntPortxDP <= x"00000000";
DMAFifoTXRrDataCntPortxDP <= x"00000000";
DMAFifoTXStatusPortxDP <= x"00000000";
DMAFifoRXWrDataCntPortxDP <= x"00000000";
DMAFifoRXRrDataCntPortxDP <= x"00000000";
DMAFifoRXStatusPortxDP <= x"00000000";
QoSPhyStatusPortxDP <= x"00000000";
QoSDMAInitSetOcpCtrlPortxDP <= x"00000000";
QoSDMAInitClrOcpCtrlPortxDP <= x"00000000";
QoSDMAInitStatusPortxDP <= x"00000000";
elsif rising_edge(SAxiClkxC) then
LocalNetAddrPortxDP <= LocalNetAddrPortxDN;
RGBLed0PortxDP <= RGBLed0PortxDN;
RGBLed1PortxDP <= RGBLed1PortxDN;
DMAFifoTXWrDataCntPortxDP <= DMAFifoTXWrDataCntPortxDN;
DMAFifoTXRrDataCntPortxDP <= DMAFifoTXRrDataCntPortxDN;
DMAFifoTXStatusPortxDP <= DMAFifoTXStatusPortxDN;
DMAFifoRXWrDataCntPortxDP <= DMAFifoRXWrDataCntPortxDN;
DMAFifoRXRrDataCntPortxDP <= DMAFifoRXRrDataCntPortxDN;
DMAFifoRXStatusPortxDP <= DMAFifoRXStatusPortxDN;
QoSPhyStatusPortxDP <= QoSPhyStatusPortxDN;
QoSDMAInitSetOcpCtrlPortxDP <= QoSDMAInitSetOcpCtrlPortxDN;
QoSDMAInitClrOcpCtrlPortxDP <= QoSDMAInitClrOcpCtrlPortxDN;
QoSDMAInitStatusPortxDP <= QoSDMAInitStatusPortxDN;
end if;
end process UpdateRegBankxP;
end block ScalpFastRouterRegistersxB;
end behavioral;
src/templates/hdl/template_regbank.vhd
+ 1
− 1
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...@@ -129,7 +129,7 @@ begin ...@@ -129,7 +129,7 @@ begin
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS; SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS; SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS; SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
WrValidxAS : WrValidxS <= SAxiWValidxSI and not SAxiAWValidxSI;; WrValidxAS : WrValidxS <= SAxiWValidxSI and not SAxiAWValidxSI;
WrDataxAS : WrDataxD <= SAxiWDataxDI; WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP; WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
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