Registers bank: Rename the reset input (and update test bench)

hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd

@@ -38,7 +38,7 @@ architecture Behavioral of tb_hog_build_info_regs is
     
     port (
       clk_i             : in std_logic; -- Clock in
-      resetn            : in std_logic; -- Reset in
+      resetn_i          : in std_logic; -- Reset in
       rd_valid_i        : in std_logic; -- AXI4-lite R interface, validation
       rd_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
       rd_data_o         : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
@@ -130,7 +130,7 @@ begin
       )
     port map (
       clk_i => clk_s,
-      resetn => resetn_s,
+      resetn_i => resetn_s,
       rd_valid_i => rd_valid_s,
       rd_addr_i => rd_addr_s,
       rd_data_o => rd_data_s,

hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd

@@ -25,12 +25,12 @@ use IEEE.numeric_std.all;
 
 entity hog_build_info_regs is
   generic (
-    C_ADDR_WIDTH: integer := 32   -- Width of the addresses
+    C_ADDR_WIDTH: integer := 4   -- Width of the addresses
     );
   
   port (
     clk_i             : in std_logic; -- Clock in
-    resetn            : in std_logic; -- Reset in
+    resetn_i          : in std_logic; -- Reset in
     rd_valid_i        : in std_logic; -- AXI4-lite R interface, validation
     rd_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
     rd_data_o         : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
@@ -76,6 +76,7 @@ architecture Behavioral of hog_build_info_regs is
 
 -- Read address integer
   signal rd_addr_s : integer := 0;
+  
 -- Read data
   signal rd_data_s : std_logic_vector(31 downto 0);
   
@@ -88,7 +89,7 @@ begin
   rd_regigters_proc: process(clk_i)
   begin
     if rising_edge(clk_i) then
-      if resetn = '0' then
+      if resetn_i = '0' then
         -- If reset, set data read to 0x00
         rd_data_s <= (others => '0');
       else