Top/hog-build-info/list/sim_1.sim

+hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd 93 lib=xil_defaultlib
 hog-build-info/hog-build-info.srcs/sim_1/new/explore_build_info.vhd 93 lib=xil_defaultlib

Top/hog-build-info/sim.conf

 [sim_1]
 ACTIVE=1
-TOP=explore_build_info
-
-[generics]
-BANANA=01234567
+TOP=tb_hog_build_info_regs
 
+[hog]
+HOG_SIMPASS_STR=">>> Simulation completed successfully"

hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/13/2025 01:17:53 PM
+-- Design Name: Test bench Hog build info registers bank
+-- Module Name: tb_hog_build_info_regs - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: Test bench for the Hog build info register bank
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use std.env.finish;
+
+entity tb_hog_build_info_regs is
+end tb_hog_build_info_regs;
+
+architecture Behavioral of tb_hog_build_info_regs is
+  
+  -- External components
+  --- Hog build info register bank
+  component hog_build_info_regs is
+    generic (
+      C_ADDR_WIDTH: integer := 32   -- Width of the addresses
+      );
+    
+    port (
+      clk_i             : in std_logic; -- Clock in
+      resetn            : in std_logic; -- Reset in
+      rd_valid_i        : in std_logic; -- AXI4-lite R interface, validation
+      rd_addr_i         : in std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- AXI4-lite R, address
+      rd_data_o         : out std_logic_vector(31 downto 0); -- AXI4-lite R, data
+      hog_global_date_i : in std_logic_vector(31 downto 0); -- Hog build global date
+      hog_global_time_i : in std_logic_vector(31 downto 0) -- Hog build global time
+      );
+  end component;
+
+  -- Clock signal and period
+  constant CLK_PERIOD : time := 10 ns;
+  signal clk_s : std_logic := '0';
+
+  -- Resetn signal
+  signal resetn_s : std_logic := '1';
+
+  -- Config
+  constant C_ADDR_WIDTH: integer := 32;
+
+  -- Registers addresses
+  constant GDR_BASEADDR : integer := 0; -- Global date register
+  constant GTR_BASEADDR : integer := 4; -- Global time register
+  constant UNK_BASEADDR : integer := 100; -- Unknown register
+
+  -- Fake Hog build info
+  constant hog_global_date : std_logic_vector(31 downto 0) := X"13032025";
+  constant hog_global_time : std_logic_vector(31 downto 0) := X"00123456";
+
+  -- AXI4-lite interface bus
+  signal rd_valid_s : std_logic := '0';
+  signal rd_addr_s  : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
+  signal rd_data_s  : std_logic_vector(31 downto 0) := (others => '0');
+
+  -- Hog build info inputs
+  signal hog_global_date_s : std_logic_vector(31 downto 0) := (others => '0');
+  signal hog_global_time_s : std_logic_vector(31 downto 0) := (others => '0');
+
+  -- Test bench steps
+  signal reset_done_s: std_logic := '0';
+  signal check_reg_0_data_s: std_logic := '0';
+  signal check_reg_1_data_s: std_logic := '0';
+  signal check_reg_unk_data_s: std_logic := '0';
+
+  procedure request_access_to_reg(
+    constant reg_addr : in integer;
+    signal rd_valid : out std_logic;
+    signal rd_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0);
+    signal monitor_step : out std_logic
+    ) is
+  begin
+    
+    --- Write the register address
+    rd_addr <= std_logic_vector(to_unsigned(reg_addr, rd_addr'length));
+    --- Validate the address
+    rd_valid <= '1';
+    -- Wait 1 cycle
+    wait for CLK_PERIOD;
+    -- Tell monitor process to check data for reg 0
+    monitor_step <= '1';
+    -- Put validation back to 0
+    rd_valid <= '0';
+    -- Let time to monitor process to check rd_data_o
+    wait for CLK_PERIOD;
+
+  end procedure request_access_to_reg;
+
+begin
+
+  -- Instance of the register bank
+  hog_b_i_regs_test:hog_build_info_regs
+    generic map (
+      C_ADDR_WIDTH => C_ADDR_WIDTH
+      )
+  port map (
+    clk_i => clk_s,
+    resetn => resetn_s,
+    rd_valid_i => rd_valid_s,
+    rd_addr_i => rd_addr_s,
+    rd_data_o => rd_data_s,
+    hog_global_date_i => hog_global_date_s,
+    hog_global_time_i => hog_global_time_s
+    );
+
+  -- Feed the register bank with fake Hog build info
+  hog_global_date_s <=hog_global_date;
+  hog_global_time_s <=hog_global_time;
+  
+
+  -- Clock generator process
+  clk_process : clk_s <= not clk_s after CLK_PERIOD / 2;
+
+  -- Reset process
+  reset_process: process
+  begin
+    resetn_s <= '0';
+    wait for CLK_PERIOD * 10;
+    resetn_s <= '1';
+    wait for CLK_PERIOD;
+    reset_done_s <= '1';
+    wait;
+  end process;
+
+  -- Stimulus process
+  stimulus_process: process
+  begin
+    -- Wait until reset is done
+    wait until reset_done_s = '1';
+    wait for CLK_PERIOD; -- Let monitor process check rd_data_o is 0x0
+    
+    -- Write the addr of the reg 0, validate it and wait a bit
+    request_access_to_reg(GDR_BASEADDR, rd_valid_s, rd_addr_s, check_reg_0_data_s);
+    
+    -- Write the addr of the reg 1, validate it and wait a bit
+    request_access_to_reg(GTR_BASEADDR, rd_valid_s, rd_addr_s, check_reg_1_data_s);
+    
+    -- Write the addr of an unknown reg, validate it and wait a bit
+    request_access_to_reg(UNK_BASEADDR, rd_valid_s, rd_addr_s, check_reg_unk_data_s);
+    
+    -- Wait endlessly
+    wait;
+  end process stimulus_process;
+
+  -- Monitor process
+  monitor_process: process
+  begin
+    -- Check after reset the data out is 0x0
+    wait until reset_done_s = '1';
+    assert rd_data_s = X"00000000"
+      report ">>> rd_data_o is not at 0x0 after a reset. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+
+    -- Check we get register 0 value on data out
+    wait until check_reg_0_data_s = '1';
+    wait for CLK_PERIOD;
+    assert rd_data_s = hog_global_date
+      report ">>> register 0 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+
+    -- Check we get register 1 value on data out
+    wait until check_reg_1_data_s = '1';
+    assert rd_data_s = hog_global_time
+      report ">>> register 1 value do not correspond to the value feed to the register bank. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+
+    -- Check we get 0x0 on data out because of unknown register requested
+    wait until check_reg_unk_data_s = '1';
+    assert rd_data_s = X"00000000"
+      report ">>> rd_data_s is not at 0x0 when unknown register is requested. Instead, get: " & to_hstring(to_bitvector(rd_data_s))
+      severity failure;
+
+    -- If arrive here, the simulation have completed successfully
+    wait for CLK_PERIOD * 10;
+    report ">>> Simulation completed successfully";
+    finish;
+    
+  end process monitor_process;
+
+
+end Behavioral;

hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_regs.vhd

@@ -48,14 +48,14 @@ architecture Behavioral of hog_build_info_regs is
 --     [31 - 0] Date in hexa, with digits in format: ddmmyyyy
   signal global_date_reg : std_logic_vector(31 downto 0) := (others => '0');
 
--- Global time register (GTR) @ 0x00 - R
+-- Global time register (GTR) @ 0x04 - R
 --     Time of last commit when the project was modified.
 --     [31 - 0] Time in hexa, with digits in format: 00HHMMSS
   signal global_time_reg : std_logic_vector(31 downto 0) := (others => '0');
 
 -- Registers addresses
   constant GDR_BASEADDR : integer := 0; -- Global date register
-  constant GTR_BASEADDR : integer := 0; -- Global time register
+  constant GTR_BASEADDR : integer := 4; -- Global time register
 
 -- Read address integer
   signal rd_addr_s : integer := 0;