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Commit 93b8a638 authored by sebastie.gendre's avatar sebastie.gendre
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Bank register: Fix missing address for the 2nd register

parent 4d595d8d
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......@@ -48,14 +48,14 @@ architecture Behavioral of hog_build_info_regs is
-- [31 - 0] Date in hexa, with digits in format: ddmmyyyy
signal global_date_reg : std_logic_vector(31 downto 0) := (others => '0');
-- Global time register (GTR) @ 0x00 - R
-- Global time register (GTR) @ 0x04 - R
-- Time of last commit when the project was modified.
-- [31 - 0] Time in hexa, with digits in format: 00HHMMSS
signal global_time_reg : std_logic_vector(31 downto 0) := (others => '0');
-- Registers addresses
constant GDR_BASEADDR : integer := 0; -- Global date register
constant GTR_BASEADDR : integer := 0; -- Global time register
constant GTR_BASEADDR : integer := 4; -- Global time register
-- Read address integer
signal rd_addr_s : integer := 0;
......
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