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Travail semestre SG
hog-build-info-register
Commits
977af9dd
Commit
977af9dd
authored
1 month ago
by
sebastie.gendre
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AXI4-lite periph: Set correct wait time between accesses and bad step value
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1d97f32b
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hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd
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