AXI4-lite periph: Set correct wait time between accesses and bad step value

hog-build-info/hog-build-info.srcs/sim/axi4lite_interface_tb/tb_axi4lite_hog_build_info.vhd

@@ -221,28 +221,28 @@ begin
 
     -- Request to read register 0
     axi4lite_read(GDR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
-    check_reg_0_data_s <= '0';
-    wait for CLK_PERIOD;
+    check_reg_0_data_s <= '1';
+    wait for CLK_PERIOD * 2;
 
     -- Request to read register 1
     axi4lite_read(GTR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
-    check_reg_1_data_s <= '0';
-    wait for CLK_PERIOD;
+    check_reg_1_data_s <= '1';
+    wait for CLK_PERIOD * 2;
     
     -- Request to read register 2
     axi4lite_read(GVR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
-    check_reg_2_data_s <= '0';
-    wait for CLK_PERIOD;
+    check_reg_2_data_s <= '1';
+    wait for CLK_PERIOD * 2;
     
     -- Request to read register 3
     axi4lite_read(GSR_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
-    check_reg_3_data_s <= '0';
-    wait for CLK_PERIOD;
+    check_reg_3_data_s <= '1';
+    wait for CLK_PERIOD * 2;
     
     -- Request to read unknown register 
     axi4lite_read(UNK_BASEADDR, rd_data_s, axi4lite_rd_bus_i, axi4lite_rd_bus_o);
-    check_reg_unk_data_s <= '0';
-    wait for CLK_PERIOD;
+    check_reg_unk_data_s <= '1';
+    wait for CLK_PERIOD * 2;
 
     -- Wait endlessly
     wait;